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63#ifndef __iwl_csr_h__
64#define __iwl_csr_h__
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82
83#define CSR_BASE (0x000)
84
85#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000)
86#define CSR_INT_COALESCING (CSR_BASE+0x004)
87#define CSR_INT (CSR_BASE+0x008)
88#define CSR_INT_MASK (CSR_BASE+0x00c)
89#define CSR_FH_INT_STATUS (CSR_BASE+0x010)
90#define CSR_GPIO_IN (CSR_BASE+0x018)
91#define CSR_RESET (CSR_BASE+0x020)
92#define CSR_GP_CNTRL (CSR_BASE+0x024)
93
94
95#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
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105#define CSR_HW_REV (CSR_BASE+0x028)
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116#define CSR_HW_RF_ID (CSR_BASE+0x09c)
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124#define CSR_EEPROM_REG (CSR_BASE+0x02c)
125#define CSR_EEPROM_GP (CSR_BASE+0x030)
126#define CSR_OTP_GP_REG (CSR_BASE+0x034)
127
128#define CSR_GIO_REG (CSR_BASE+0x03C)
129#define CSR_GP_UCODE_REG (CSR_BASE+0x048)
130#define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
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135
136#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
137#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
138#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
139#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
140
141#define CSR_MBOX_SET_REG (CSR_BASE + 0x88)
142
143#define CSR_LED_REG (CSR_BASE+0x094)
144#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
145#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8)
146#define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20)
147#define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC)
148#define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF
149
150
151#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
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153
154#define CSR_HOST_CHICKEN (CSR_BASE + 0x204)
155#define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME BIT(19)
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157
158#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
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163#define CSR_MONITOR_CFG_REG (CSR_BASE+0x214)
164#define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228)
165#define CSR_MONITOR_XTAL_RESOURCES (0x00000010)
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175#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
176
177#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
178#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
179
180
181#define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
182#define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
183#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
184#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
185#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
186#define CSR_HW_IF_CONFIG_REG_D3_DEBUG (0x00000200)
187#define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
188#define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
189#define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
190
191#define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
192#define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
193#define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
194#define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
195#define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
196#define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
197
198#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
199#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
200#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000)
201#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000)
202#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000)
203#define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
204#define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000)
205
206#define CSR_MBOX_SET_REG_OS_ALIVE BIT(5)
207
208#define CSR_INT_PERIODIC_DIS (0x00)
209#define CSR_INT_PERIODIC_ENA (0xFF)
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212
213#define CSR_INT_BIT_FH_RX (1 << 31)
214#define CSR_INT_BIT_HW_ERR (1 << 29)
215#define CSR_INT_BIT_RX_PERIODIC (1 << 28)
216#define CSR_INT_BIT_FH_TX (1 << 27)
217#define CSR_INT_BIT_SCD (1 << 26)
218#define CSR_INT_BIT_SW_ERR (1 << 25)
219#define CSR_INT_BIT_RF_KILL (1 << 7)
220#define CSR_INT_BIT_CT_KILL (1 << 6)
221#define CSR_INT_BIT_SW_RX (1 << 3)
222#define CSR_INT_BIT_WAKEUP (1 << 1)
223#define CSR_INT_BIT_ALIVE (1 << 0)
224
225#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
226 CSR_INT_BIT_HW_ERR | \
227 CSR_INT_BIT_FH_TX | \
228 CSR_INT_BIT_SW_ERR | \
229 CSR_INT_BIT_RF_KILL | \
230 CSR_INT_BIT_SW_RX | \
231 CSR_INT_BIT_WAKEUP | \
232 CSR_INT_BIT_ALIVE | \
233 CSR_INT_BIT_RX_PERIODIC)
234
235
236#define CSR_FH_INT_BIT_ERR (1 << 31)
237#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30)
238#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17)
239#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16)
240#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1)
241#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0)
242
243#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
244 CSR_FH_INT_BIT_RX_CHNL1 | \
245 CSR_FH_INT_BIT_RX_CHNL0)
246
247#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
248 CSR_FH_INT_BIT_TX_CHNL0)
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250
251#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
252#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
253#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
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255
256#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
257#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
258#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
259#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
260#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
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281#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
282#define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400)
283
284#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
285#define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)
286#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
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290#define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
291#define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
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294#define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0)
295#define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4)
296#define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8)
297#define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12)
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302enum {
303 SILICON_A_STEP = 0,
304 SILICON_B_STEP,
305 SILICON_C_STEP,
306};
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308
309#define CSR_HW_REV_TYPE_MSK (0x000FFF0)
310#define CSR_HW_REV_TYPE_5300 (0x0000020)
311#define CSR_HW_REV_TYPE_5350 (0x0000030)
312#define CSR_HW_REV_TYPE_5100 (0x0000050)
313#define CSR_HW_REV_TYPE_5150 (0x0000040)
314#define CSR_HW_REV_TYPE_1000 (0x0000060)
315#define CSR_HW_REV_TYPE_6x00 (0x0000070)
316#define CSR_HW_REV_TYPE_6x50 (0x0000080)
317#define CSR_HW_REV_TYPE_6150 (0x0000084)
318#define CSR_HW_REV_TYPE_6x05 (0x00000B0)
319#define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05
320#define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05
321#define CSR_HW_REV_TYPE_2x30 (0x00000C0)
322#define CSR_HW_REV_TYPE_2x00 (0x0000100)
323#define CSR_HW_REV_TYPE_105 (0x0000110)
324#define CSR_HW_REV_TYPE_135 (0x0000120)
325#define CSR_HW_REV_TYPE_7265D (0x0000210)
326#define CSR_HW_REV_TYPE_NONE (0x00001F0)
327#define CSR_HW_REV_TYPE_QNJ (0x0000360)
328#define CSR_HW_REV_TYPE_HR_CDB (0x0000340)
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330
331#define CSR_HW_RF_ID_TYPE_JF (0x00105100)
332#define CSR_HW_RF_ID_TYPE_HR (0x0010A000)
333#define CSR_HW_RF_ID_TYPE_HRCDB (0x00109F00)
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336#define CSR_HW_RF_ID_TYPE_CHIP_ID(_val) (((_val) >> 12) & 0xFFF)
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339#define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF)
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342#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
343#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
344#define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
345#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
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348#define CSR_EEPROM_GP_VALID_MSK (0x00000007)
349#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
350#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
351#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
352#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
353#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
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356#define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000)
357#define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000)
358#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000)
359#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000)
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362#define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000)
363#define CSR_GP_REG_NO_POWER_SAVE (0x00000000)
364#define CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
365#define CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
366#define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
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370#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
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400#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
401#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
402#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
403#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
404#define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
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407#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
408#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
409#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
410#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
411#define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
412#define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
413
414#define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
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417#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
418#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
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421#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
422#define CSR_LED_REG_TURN_ON (0x60)
423#define CSR_LED_REG_TURN_OFF (0x20)
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425
426#define CSR50_ANA_PLL_CFG_VAL (0x00880300)
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429#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
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432#define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
433#define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
434#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
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461#define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec)
462#define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4)
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479#define HBUS_BASE (0x400)
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490#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
491#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
492#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
493#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
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496#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
497#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
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507#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
508#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
509#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
510#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
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513#define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c)
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522#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
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534#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
535#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
536#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
537#define IWL_HOST_INT_OPER_MODE BIT(31)
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544enum dtd_diode_reg {
545 DTS_DIODE_REG_DIG_VAL = 0x000000FF,
546 DTS_DIODE_REG_VREF_LOW = 0x0000FF00,
547 DTS_DIODE_REG_VREF_HIGH = 0x00FF0000,
548 DTS_DIODE_REG_VREF_ID = 0x03000000,
549 DTS_DIODE_REG_PASS_ONCE = 0x80000000,
550 DTS_DIODE_REG_FLAGS_MSK = 0xFF000000,
551
552 DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
553 DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003,
554 DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
555 DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080,
556};
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561
562#define CSR_MSIX_BASE (0x2000)
563#define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800)
564#define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804)
565#define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808)
566#define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C)
567#define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810)
568#define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880)
569#define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890)
570#define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000)
571#define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause))
572#define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause))
573
574#define MSIX_FH_INT_CAUSES_Q(q) (q)
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579enum msix_fh_int_causes {
580 MSIX_FH_INT_CAUSES_Q0 = BIT(0),
581 MSIX_FH_INT_CAUSES_Q1 = BIT(1),
582 MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16),
583 MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17),
584 MSIX_FH_INT_CAUSES_S2D = BIT(19),
585 MSIX_FH_INT_CAUSES_FH_ERR = BIT(21),
586};
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591enum msix_hw_int_causes {
592 MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0),
593 MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1),
594 MSIX_HW_INT_CAUSES_REG_IPC = BIT(1),
595 MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = BIT(5),
596 MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6),
597 MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7),
598 MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8),
599 MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25),
600 MSIX_HW_INT_CAUSES_REG_SCD = BIT(26),
601 MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27),
602 MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29),
603 MSIX_HW_INT_CAUSES_REG_HAP = BIT(30),
604};
605
606#define MSIX_MIN_INTERRUPT_VECTORS 2
607#define MSIX_AUTO_CLEAR_CAUSE 0
608#define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7)
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614#define CSR_ADDR_BASE (0x380)
615#define CSR_MAC_ADDR0_OTP (CSR_ADDR_BASE)
616#define CSR_MAC_ADDR1_OTP (CSR_ADDR_BASE + 4)
617#define CSR_MAC_ADDR0_STRAP (CSR_ADDR_BASE + 8)
618#define CSR_MAC_ADDR1_STRAP (CSR_ADDR_BASE + 0xC)
619
620#endif
621