1
2
3
4
5
6
7
8
9
10
11
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_device.h>
19#include <linux/phy/phy.h>
20#include <linux/regmap.h>
21#include <linux/spinlock.h>
22#include <linux/soc/samsung/exynos-regs-pmu.h>
23#include <linux/mfd/syscon.h>
24
25enum exynos_mipi_phy_id {
26 EXYNOS_MIPI_PHY_ID_NONE = -1,
27 EXYNOS_MIPI_PHY_ID_CSIS0,
28 EXYNOS_MIPI_PHY_ID_DSIM0,
29 EXYNOS_MIPI_PHY_ID_CSIS1,
30 EXYNOS_MIPI_PHY_ID_DSIM1,
31 EXYNOS_MIPI_PHY_ID_CSIS2,
32 EXYNOS_MIPI_PHYS_NUM
33};
34
35enum exynos_mipi_phy_regmap_id {
36 EXYNOS_MIPI_REGMAP_PMU,
37 EXYNOS_MIPI_REGMAP_DISP,
38 EXYNOS_MIPI_REGMAP_CAM0,
39 EXYNOS_MIPI_REGMAP_CAM1,
40 EXYNOS_MIPI_REGMAPS_NUM
41};
42
43struct mipi_phy_device_desc {
44 int num_phys;
45 int num_regmaps;
46 const char *regmap_names[EXYNOS_MIPI_REGMAPS_NUM];
47 struct exynos_mipi_phy_desc {
48 enum exynos_mipi_phy_id coupled_phy_id;
49 u32 enable_val;
50 unsigned int enable_reg;
51 enum exynos_mipi_phy_regmap_id enable_map;
52 u32 resetn_val;
53 unsigned int resetn_reg;
54 enum exynos_mipi_phy_regmap_id resetn_map;
55 } phys[EXYNOS_MIPI_PHYS_NUM];
56};
57
58static const struct mipi_phy_device_desc s5pv210_mipi_phy = {
59 .num_regmaps = 1,
60 .regmap_names = {"syscon"},
61 .num_phys = 4,
62 .phys = {
63 {
64
65 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
66 .enable_val = EXYNOS4_PHY_ENABLE,
67 .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
68 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
69 .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
70 .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
71 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
72 }, {
73
74 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
75 .enable_val = EXYNOS4_PHY_ENABLE,
76 .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
77 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
78 .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
79 .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
80 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
81 }, {
82
83 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
84 .enable_val = EXYNOS4_PHY_ENABLE,
85 .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
86 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
87 .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
88 .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
89 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
90 }, {
91
92 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
93 .enable_val = EXYNOS4_PHY_ENABLE,
94 .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
95 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
96 .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
97 .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
98 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
99 },
100 },
101};
102
103static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
104 .num_regmaps = 1,
105 .regmap_names = {"syscon"},
106 .num_phys = 5,
107 .phys = {
108 {
109
110 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
111 .enable_val = EXYNOS4_PHY_ENABLE,
112 .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
113 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
114 .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
115 .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
116 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
117 }, {
118
119 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
120 .enable_val = EXYNOS4_PHY_ENABLE,
121 .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
122 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
123 .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
124 .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
125 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
126 }, {
127
128 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
129 .enable_val = EXYNOS4_PHY_ENABLE,
130 .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
131 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
132 .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
133 .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
134 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
135 }, {
136
137 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
138 .enable_val = EXYNOS4_PHY_ENABLE,
139 .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
140 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
141 .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
142 .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
143 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
144 }, {
145
146 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
147 .enable_val = EXYNOS4_PHY_ENABLE,
148 .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
149 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
150 .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
151 .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
152 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
153 },
154 },
155};
156
157#define EXYNOS5433_SYSREG_DISP_MIPI_PHY 0x100C
158#define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON 0x1014
159#define EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON 0x1020
160
161static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
162 .num_regmaps = 4,
163 .regmap_names = {
164 "samsung,pmu-syscon",
165 "samsung,disp-sysreg",
166 "samsung,cam0-sysreg",
167 "samsung,cam1-sysreg"
168 },
169 .num_phys = 5,
170 .phys = {
171 {
172
173 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
174 .enable_val = EXYNOS4_PHY_ENABLE,
175 .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
176 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
177 .resetn_val = BIT(0),
178 .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
179 .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
180 }, {
181
182 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
183 .enable_val = EXYNOS4_PHY_ENABLE,
184 .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
185 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
186 .resetn_val = BIT(0),
187 .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
188 .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
189 }, {
190
191 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
192 .enable_val = EXYNOS4_PHY_ENABLE,
193 .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
194 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
195 .resetn_val = BIT(1),
196 .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
197 .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
198 }, {
199
200 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
201 .enable_val = EXYNOS4_PHY_ENABLE,
202 .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
203 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
204 .resetn_val = BIT(1),
205 .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
206 .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
207 }, {
208
209 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
210 .enable_val = EXYNOS4_PHY_ENABLE,
211 .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(2),
212 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
213 .resetn_val = BIT(0),
214 .resetn_reg = EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON,
215 .resetn_map = EXYNOS_MIPI_REGMAP_CAM1,
216 },
217 },
218};
219
220struct exynos_mipi_video_phy {
221 struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
222 int num_phys;
223 struct video_phy_desc {
224 struct phy *phy;
225 unsigned int index;
226 const struct exynos_mipi_phy_desc *data;
227 } phys[EXYNOS_MIPI_PHYS_NUM];
228 spinlock_t slock;
229};
230
231static int __set_phy_state(const struct exynos_mipi_phy_desc *data,
232 struct exynos_mipi_video_phy *state, unsigned int on)
233{
234 struct regmap *enable_map = state->regmaps[data->enable_map];
235 struct regmap *resetn_map = state->regmaps[data->resetn_map];
236
237 spin_lock(&state->slock);
238
239
240 if (!on && data->coupled_phy_id >= 0 &&
241 state->phys[data->coupled_phy_id].phy->power_count == 0)
242 regmap_update_bits(enable_map, data->enable_reg,
243 data->enable_val, 0);
244
245 if (on)
246 regmap_update_bits(resetn_map, data->resetn_reg,
247 data->resetn_val, data->resetn_val);
248 else
249 regmap_update_bits(resetn_map, data->resetn_reg,
250 data->resetn_val, 0);
251
252 if (on)
253 regmap_update_bits(enable_map, data->enable_reg,
254 data->enable_val, data->enable_val);
255
256 spin_unlock(&state->slock);
257
258 return 0;
259}
260
261#define to_mipi_video_phy(desc) \
262 container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index])
263
264static int exynos_mipi_video_phy_power_on(struct phy *phy)
265{
266 struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
267 struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
268
269 return __set_phy_state(phy_desc->data, state, 1);
270}
271
272static int exynos_mipi_video_phy_power_off(struct phy *phy)
273{
274 struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
275 struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
276
277 return __set_phy_state(phy_desc->data, state, 0);
278}
279
280static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
281 struct of_phandle_args *args)
282{
283 struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
284
285 if (WARN_ON(args->args[0] >= state->num_phys))
286 return ERR_PTR(-ENODEV);
287
288 return state->phys[args->args[0]].phy;
289}
290
291static const struct phy_ops exynos_mipi_video_phy_ops = {
292 .power_on = exynos_mipi_video_phy_power_on,
293 .power_off = exynos_mipi_video_phy_power_off,
294 .owner = THIS_MODULE,
295};
296
297static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
298{
299 const struct mipi_phy_device_desc *phy_dev;
300 struct exynos_mipi_video_phy *state;
301 struct device *dev = &pdev->dev;
302 struct device_node *np = dev->of_node;
303 struct phy_provider *phy_provider;
304 unsigned int i;
305
306 phy_dev = of_device_get_match_data(dev);
307 if (!phy_dev)
308 return -ENODEV;
309
310 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
311 if (!state)
312 return -ENOMEM;
313
314 for (i = 0; i < phy_dev->num_regmaps; i++) {
315 state->regmaps[i] = syscon_regmap_lookup_by_phandle(np,
316 phy_dev->regmap_names[i]);
317 if (IS_ERR(state->regmaps[i]))
318 return PTR_ERR(state->regmaps[i]);
319 }
320 state->num_phys = phy_dev->num_phys;
321 spin_lock_init(&state->slock);
322
323 dev_set_drvdata(dev, state);
324
325 for (i = 0; i < state->num_phys; i++) {
326 struct phy *phy = devm_phy_create(dev, NULL,
327 &exynos_mipi_video_phy_ops);
328 if (IS_ERR(phy)) {
329 dev_err(dev, "failed to create PHY %d\n", i);
330 return PTR_ERR(phy);
331 }
332
333 state->phys[i].phy = phy;
334 state->phys[i].index = i;
335 state->phys[i].data = &phy_dev->phys[i];
336 phy_set_drvdata(phy, &state->phys[i]);
337 }
338
339 phy_provider = devm_of_phy_provider_register(dev,
340 exynos_mipi_video_phy_xlate);
341
342 return PTR_ERR_OR_ZERO(phy_provider);
343}
344
345static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
346 {
347 .compatible = "samsung,s5pv210-mipi-video-phy",
348 .data = &s5pv210_mipi_phy,
349 }, {
350 .compatible = "samsung,exynos5420-mipi-video-phy",
351 .data = &exynos5420_mipi_phy,
352 }, {
353 .compatible = "samsung,exynos5433-mipi-video-phy",
354 .data = &exynos5433_mipi_phy,
355 },
356 { },
357};
358MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
359
360static struct platform_driver exynos_mipi_video_phy_driver = {
361 .probe = exynos_mipi_video_phy_probe,
362 .driver = {
363 .of_match_table = exynos_mipi_video_phy_of_match,
364 .name = "exynos-mipi-video-phy",
365 }
366};
367module_platform_driver(exynos_mipi_video_phy_driver);
368
369MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI CSI-2/DSI PHY driver");
370MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
371MODULE_LICENSE("GPL v2");
372
