LXR linux/drivers/reset/reset-hsdk.c

   1/*
   2 * Copyright (C) 2017 Synopsys.
   3 *
   4 * Synopsys HSDK Development platform reset driver.
   5 *
   6 * This file is licensed under the terms of the GNU General Public
   7 * License version 2. This program is licensed "as is" without any
   8 * warranty of any kind, whether express or implied.
   9 */
  10
  11#include <linux/delay.h>
  12#include <linux/io.h>
  13#include <linux/iopoll.h>
  14#include <linux/module.h>
  15#include <linux/of.h>
  16#include <linux/platform_device.h>
  17#include <linux/reset-controller.h>
  18#include <linux/slab.h>
  19#include <linux/types.h>
  20
  21#define to_hsdk_rst(p)  container_of((p), struct hsdk_rst, rcdev)
  22
  23struct hsdk_rst {
  24        void __iomem                    *regs_ctl;
  25        void __iomem                    *regs_rst;
  26        spinlock_t                      lock;
  27        struct reset_controller_dev     rcdev;
  28};
  29
  30static const u32 rst_map[] = {
  31        BIT(16), /* APB_RST  */
  32        BIT(17), /* AXI_RST  */
  33        BIT(18), /* ETH_RST  */
  34        BIT(19), /* USB_RST  */
  35        BIT(20), /* SDIO_RST */
  36        BIT(21), /* HDMI_RST */
  37        BIT(22), /* GFX_RST  */
  38        BIT(25), /* DMAC_RST */
  39        BIT(31), /* EBI_RST  */
  40};
  41
  42#define HSDK_MAX_RESETS                 ARRAY_SIZE(rst_map)
  43
  44#define CGU_SYS_RST_CTRL                0x0
  45#define CGU_IP_SW_RESET                 0x0
  46#define CGU_IP_SW_RESET_DELAY_SHIFT     16
  47#define CGU_IP_SW_RESET_DELAY_MASK      GENMASK(31, CGU_IP_SW_RESET_DELAY_SHIFT)
  48#define CGU_IP_SW_RESET_DELAY           0
  49#define CGU_IP_SW_RESET_RESET           BIT(0)
  50#define SW_RESET_TIMEOUT                10000
  51
  52static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id)
  53{
  54        writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL);
  55}
  56
  57static int hsdk_reset_do(struct hsdk_rst *rst)
  58{
  59        u32 reg;
  60
  61        reg = readl(rst->regs_rst + CGU_IP_SW_RESET);
  62        reg &= ~CGU_IP_SW_RESET_DELAY_MASK;
  63        reg |= CGU_IP_SW_RESET_DELAY << CGU_IP_SW_RESET_DELAY_SHIFT;
  64        reg |= CGU_IP_SW_RESET_RESET;
  65        writel(reg, rst->regs_rst + CGU_IP_SW_RESET);
  66
  67        /* wait till reset bit is back to 0 */
  68        return readl_poll_timeout_atomic(rst->regs_rst + CGU_IP_SW_RESET, reg,
  69                !(reg & CGU_IP_SW_RESET_RESET), 5, SW_RESET_TIMEOUT);
  70}
  71
  72static int hsdk_reset_reset(struct reset_controller_dev *rcdev,
  73                              unsigned long id)
  74{
  75        struct hsdk_rst *rst = to_hsdk_rst(rcdev);
  76        unsigned long flags;
  77        int ret;
  78
  79        spin_lock_irqsave(&rst->lock, flags);
  80        hsdk_reset_config(rst, id);
  81        ret = hsdk_reset_do(rst);
  82        spin_unlock_irqrestore(&rst->lock, flags);
  83
  84        return ret;
  85}
  86
  87static const struct reset_control_ops hsdk_reset_ops = {
  88        .reset  = hsdk_reset_reset,
  89};
  90
  91static int hsdk_reset_probe(struct platform_device *pdev)
  92{
  93        struct hsdk_rst *rst;
  94        struct resource *mem;
  95
  96        rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL);
  97        if (!rst)
  98                return -ENOMEM;
  99
 100        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 101        rst->regs_ctl = devm_ioremap_resource(&pdev->dev, mem);
 102        if (IS_ERR(rst->regs_ctl))
 103                return PTR_ERR(rst->regs_ctl);
 104
 105        mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 106        rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem);
 107        if (IS_ERR(rst->regs_rst))
 108                return PTR_ERR(rst->regs_rst);
 109
 110        spin_lock_init(&rst->lock);
 111
 112        rst->rcdev.owner = THIS_MODULE;
 113        rst->rcdev.ops = &hsdk_reset_ops;
 114        rst->rcdev.of_node = pdev->dev.of_node;
 115        rst->rcdev.nr_resets = HSDK_MAX_RESETS;
 116        rst->rcdev.of_reset_n_cells = 1;
 117
 118        return reset_controller_register(&rst->rcdev);
 119}
 120
 121static const struct of_device_id hsdk_reset_dt_match[] = {
 122        { .compatible = "snps,hsdk-reset" },
 123        { },
 124};
 125
 126static struct platform_driver hsdk_reset_driver = {
 127        .probe  = hsdk_reset_probe,
 128        .driver = {
 129                .name = "hsdk-reset",
 130                .of_match_table = hsdk_reset_dt_match,
 131        },
 132};
 133builtin_platform_driver(hsdk_reset_driver);
 134
 135MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>");
 136MODULE_DESCRIPTION("Synopsys HSDK SDP reset driver");
 137MODULE_LICENSE("GPL v2");
 138