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9#ifndef __QETH_CORE_MPC_H__
10#define __QETH_CORE_MPC_H__
11
12#include <asm/qeth.h>
13#include <uapi/linux/if_ether.h>
14
15#define IPA_PDU_HEADER_SIZE 0x40
16#define QETH_IPA_PDU_LEN_TOTAL(buffer) (buffer + 0x0e)
17#define QETH_IPA_PDU_LEN_PDU1(buffer) (buffer + 0x26)
18#define QETH_IPA_PDU_LEN_PDU2(buffer) (buffer + 0x29)
19#define QETH_IPA_PDU_LEN_PDU3(buffer) (buffer + 0x3a)
20
21extern unsigned char IPA_PDU_HEADER[];
22#define QETH_IPA_CMD_DEST_ADDR(buffer) (buffer + 0x2c)
23
24#define IPA_CMD_LENGTH (IPA_PDU_HEADER_SIZE + sizeof(struct qeth_ipa_cmd))
25
26#define QETH_SEQ_NO_LENGTH 4
27#define QETH_MPC_TOKEN_LENGTH 4
28#define QETH_MCL_LENGTH 4
29
30#define QETH_TIMEOUT (10 * HZ)
31#define QETH_IPA_TIMEOUT (45 * HZ)
32#define QETH_IDX_COMMAND_SEQNO 0xffff0000
33
34#define QETH_CLEAR_CHANNEL_PARM -10
35#define QETH_HALT_CHANNEL_PARM -11
36#define QETH_RCD_PARM -12
37
38static inline bool qeth_intparm_is_iob(unsigned long intparm)
39{
40 switch (intparm) {
41 case QETH_CLEAR_CHANNEL_PARM:
42 case QETH_HALT_CHANNEL_PARM:
43 case QETH_RCD_PARM:
44 case 0:
45 return false;
46 }
47 return true;
48}
49
50
51
52
53#define IPA_CMD_INITIATOR_HOST 0x00
54#define IPA_CMD_INITIATOR_OSA 0x01
55#define IPA_CMD_INITIATOR_HOST_REPLY 0x80
56#define IPA_CMD_INITIATOR_OSA_REPLY 0x81
57#define IPA_CMD_PRIM_VERSION_NO 0x01
58
59struct qeth_ipa_caps {
60 u32 supported;
61 u32 enabled;
62};
63
64static inline bool qeth_ipa_caps_supported(struct qeth_ipa_caps *caps, u32 mask)
65{
66 return (caps->supported & mask) == mask;
67}
68
69static inline bool qeth_ipa_caps_enabled(struct qeth_ipa_caps *caps, u32 mask)
70{
71 return (caps->enabled & mask) == mask;
72}
73
74enum qeth_card_types {
75 QETH_CARD_TYPE_OSD = 1,
76 QETH_CARD_TYPE_IQD = 5,
77 QETH_CARD_TYPE_OSN = 6,
78 QETH_CARD_TYPE_OSM = 3,
79 QETH_CARD_TYPE_OSX = 2,
80};
81
82#define IS_IQD(card) ((card)->info.type == QETH_CARD_TYPE_IQD)
83#define IS_OSN(card) ((card)->info.type == QETH_CARD_TYPE_OSN)
84
85#define QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE 0x18
86
87enum qeth_link_types {
88 QETH_LINK_TYPE_FAST_ETH = 0x01,
89 QETH_LINK_TYPE_HSTR = 0x02,
90 QETH_LINK_TYPE_GBIT_ETH = 0x03,
91 QETH_LINK_TYPE_OSN = 0x04,
92 QETH_LINK_TYPE_10GBIT_ETH = 0x10,
93 QETH_LINK_TYPE_25GBIT_ETH = 0x12,
94 QETH_LINK_TYPE_LANE_ETH100 = 0x81,
95 QETH_LINK_TYPE_LANE_TR = 0x82,
96 QETH_LINK_TYPE_LANE_ETH1000 = 0x83,
97 QETH_LINK_TYPE_LANE = 0x88,
98};
99
100
101
102
103#define RESET_ROUTING_FLAG 0x10
104enum qeth_routing_types {
105
106 NO_ROUTER = 0,
107 PRIMARY_ROUTER = 1,
108 SECONDARY_ROUTER = 2,
109 MULTICAST_ROUTER = 3,
110 PRIMARY_CONNECTOR = 4,
111 SECONDARY_CONNECTOR = 5,
112};
113
114
115enum qeth_ipa_cmds {
116 IPA_CMD_STARTLAN = 0x01,
117 IPA_CMD_STOPLAN = 0x02,
118 IPA_CMD_SETVMAC = 0x21,
119 IPA_CMD_DELVMAC = 0x22,
120 IPA_CMD_SETGMAC = 0x23,
121 IPA_CMD_DELGMAC = 0x24,
122 IPA_CMD_SETVLAN = 0x25,
123 IPA_CMD_DELVLAN = 0x26,
124 IPA_CMD_VNICC = 0x2a,
125 IPA_CMD_SETBRIDGEPORT_OSA = 0x2b,
126 IPA_CMD_SETCCID = 0x41,
127 IPA_CMD_DELCCID = 0x42,
128 IPA_CMD_MODCCID = 0x43,
129 IPA_CMD_SETIP = 0xb1,
130 IPA_CMD_QIPASSIST = 0xb2,
131 IPA_CMD_SETASSPARMS = 0xb3,
132 IPA_CMD_SETIPM = 0xb4,
133 IPA_CMD_DELIPM = 0xb5,
134 IPA_CMD_SETRTG = 0xb6,
135 IPA_CMD_DELIP = 0xb7,
136 IPA_CMD_SETADAPTERPARMS = 0xb8,
137 IPA_CMD_SET_DIAG_ASS = 0xb9,
138 IPA_CMD_SETBRIDGEPORT_IQD = 0xbe,
139 IPA_CMD_CREATE_ADDR = 0xc3,
140 IPA_CMD_DESTROY_ADDR = 0xc4,
141 IPA_CMD_REGISTER_LOCAL_ADDR = 0xd1,
142 IPA_CMD_UNREGISTER_LOCAL_ADDR = 0xd2,
143 IPA_CMD_ADDRESS_CHANGE_NOTIF = 0xd3,
144 IPA_CMD_UNKNOWN = 0x00
145};
146
147enum qeth_ip_ass_cmds {
148 IPA_CMD_ASS_START = 0x0001,
149 IPA_CMD_ASS_STOP = 0x0002,
150 IPA_CMD_ASS_CONFIGURE = 0x0003,
151 IPA_CMD_ASS_ENABLE = 0x0004,
152};
153
154enum qeth_arp_process_subcmds {
155 IPA_CMD_ASS_ARP_SET_NO_ENTRIES = 0x0003,
156 IPA_CMD_ASS_ARP_QUERY_CACHE = 0x0004,
157 IPA_CMD_ASS_ARP_ADD_ENTRY = 0x0005,
158 IPA_CMD_ASS_ARP_REMOVE_ENTRY = 0x0006,
159 IPA_CMD_ASS_ARP_FLUSH_CACHE = 0x0007,
160 IPA_CMD_ASS_ARP_QUERY_INFO = 0x0104,
161 IPA_CMD_ASS_ARP_QUERY_STATS = 0x0204,
162};
163
164
165
166
167
168enum qeth_ipa_return_codes {
169 IPA_RC_SUCCESS = 0x0000,
170 IPA_RC_NOTSUPP = 0x0001,
171 IPA_RC_IP_TABLE_FULL = 0x0002,
172 IPA_RC_UNKNOWN_ERROR = 0x0003,
173 IPA_RC_UNSUPPORTED_COMMAND = 0x0004,
174 IPA_RC_TRACE_ALREADY_ACTIVE = 0x0005,
175 IPA_RC_INVALID_FORMAT = 0x0006,
176 IPA_RC_DUP_IPV6_REMOTE = 0x0008,
177 IPA_RC_SBP_IQD_NOT_CONFIGURED = 0x000C,
178 IPA_RC_DUP_IPV6_HOME = 0x0010,
179 IPA_RC_UNREGISTERED_ADDR = 0x0011,
180 IPA_RC_NO_ID_AVAILABLE = 0x0012,
181 IPA_RC_ID_NOT_FOUND = 0x0013,
182 IPA_RC_SBP_IQD_ANO_DEV_PRIMARY = 0x0014,
183 IPA_RC_SBP_IQD_CURRENT_SECOND = 0x0018,
184 IPA_RC_SBP_IQD_LIMIT_SECOND = 0x001C,
185 IPA_RC_INVALID_IP_VERSION = 0x0020,
186 IPA_RC_SBP_IQD_CURRENT_PRIMARY = 0x0024,
187 IPA_RC_LAN_FRAME_MISMATCH = 0x0040,
188 IPA_RC_SBP_IQD_NO_QDIO_QUEUES = 0x00EB,
189 IPA_RC_L2_UNSUPPORTED_CMD = 0x2003,
190 IPA_RC_L2_DUP_MAC = 0x2005,
191 IPA_RC_L2_ADDR_TABLE_FULL = 0x2006,
192 IPA_RC_L2_DUP_LAYER3_MAC = 0x200a,
193 IPA_RC_L2_GMAC_NOT_FOUND = 0x200b,
194 IPA_RC_L2_MAC_NOT_AUTH_BY_HYP = 0x200c,
195 IPA_RC_L2_MAC_NOT_AUTH_BY_ADP = 0x200d,
196 IPA_RC_L2_MAC_NOT_FOUND = 0x2010,
197 IPA_RC_L2_INVALID_VLAN_ID = 0x2015,
198 IPA_RC_L2_DUP_VLAN_ID = 0x2016,
199 IPA_RC_L2_VLAN_ID_NOT_FOUND = 0x2017,
200 IPA_RC_L2_VLAN_ID_NOT_ALLOWED = 0x2050,
201 IPA_RC_VNICC_VNICBP = 0x20B0,
202 IPA_RC_SBP_OSA_NOT_CONFIGURED = 0x2B0C,
203 IPA_RC_SBP_OSA_OS_MISMATCH = 0x2B10,
204 IPA_RC_SBP_OSA_ANO_DEV_PRIMARY = 0x2B14,
205 IPA_RC_SBP_OSA_CURRENT_SECOND = 0x2B18,
206 IPA_RC_SBP_OSA_LIMIT_SECOND = 0x2B1C,
207 IPA_RC_SBP_OSA_NOT_AUTHD_BY_ZMAN = 0x2B20,
208 IPA_RC_SBP_OSA_CURRENT_PRIMARY = 0x2B24,
209 IPA_RC_SBP_OSA_NO_QDIO_QUEUES = 0x2BEB,
210 IPA_RC_DATA_MISMATCH = 0xe001,
211 IPA_RC_INVALID_MTU_SIZE = 0xe002,
212 IPA_RC_INVALID_LANTYPE = 0xe003,
213 IPA_RC_INVALID_LANNUM = 0xe004,
214 IPA_RC_DUPLICATE_IP_ADDRESS = 0xe005,
215 IPA_RC_IP_ADDR_TABLE_FULL = 0xe006,
216 IPA_RC_LAN_PORT_STATE_ERROR = 0xe007,
217 IPA_RC_SETIP_NO_STARTLAN = 0xe008,
218 IPA_RC_SETIP_ALREADY_RECEIVED = 0xe009,
219 IPA_RC_IP_ADDR_ALREADY_USED = 0xe00a,
220 IPA_RC_MC_ADDR_NOT_FOUND = 0xe00b,
221 IPA_RC_SETIP_INVALID_VERSION = 0xe00d,
222 IPA_RC_UNSUPPORTED_SUBCMD = 0xe00e,
223 IPA_RC_ARP_ASSIST_NO_ENABLE = 0xe00f,
224 IPA_RC_PRIMARY_ALREADY_DEFINED = 0xe010,
225 IPA_RC_SECOND_ALREADY_DEFINED = 0xe011,
226 IPA_RC_INVALID_SETRTG_INDICATOR = 0xe012,
227 IPA_RC_MC_ADDR_ALREADY_DEFINED = 0xe013,
228 IPA_RC_LAN_OFFLINE = 0xe080,
229 IPA_RC_VEPA_TO_VEB_TRANSITION = 0xe090,
230 IPA_RC_INVALID_IP_VERSION2 = 0xf001,
231 IPA_RC_ENOMEM = 0xfffe,
232 IPA_RC_FFFF = 0xffff
233};
234
235#define IPA_RC_VNICC_OOSEQ 0x0005
236
237
238#define IPA_RC_INVALID_SUBCMD IPA_RC_IP_TABLE_FULL
239#define IPA_RC_HARDWARE_AUTH_ERROR IPA_RC_UNKNOWN_ERROR
240
241
242#define IPA_RC_SBP_IQD_OS_MISMATCH IPA_RC_DUP_IPV6_HOME
243#define IPA_RC_SBP_IQD_NOT_AUTHD_BY_ZMAN IPA_RC_INVALID_IP_VERSION
244
245
246enum qeth_ipa_funcs {
247 IPA_ARP_PROCESSING = 0x00000001L,
248 IPA_INBOUND_CHECKSUM = 0x00000002L,
249 IPA_OUTBOUND_CHECKSUM = 0x00000004L,
250
251 IPA_FILTERING = 0x00000010L,
252 IPA_IPV6 = 0x00000020L,
253 IPA_MULTICASTING = 0x00000040L,
254 IPA_IP_REASSEMBLY = 0x00000080L,
255 IPA_QUERY_ARP_COUNTERS = 0x00000100L,
256 IPA_QUERY_ARP_ADDR_INFO = 0x00000200L,
257 IPA_SETADAPTERPARMS = 0x00000400L,
258 IPA_VLAN_PRIO = 0x00000800L,
259 IPA_PASSTHRU = 0x00001000L,
260 IPA_FLUSH_ARP_SUPPORT = 0x00002000L,
261 IPA_FULL_VLAN = 0x00004000L,
262 IPA_INBOUND_PASSTHRU = 0x00008000L,
263 IPA_SOURCE_MAC = 0x00010000L,
264 IPA_OSA_MC_ROUTER = 0x00020000L,
265 IPA_QUERY_ARP_ASSIST = 0x00040000L,
266 IPA_INBOUND_TSO = 0x00080000L,
267 IPA_OUTBOUND_TSO = 0x00100000L,
268 IPA_INBOUND_CHECKSUM_V6 = 0x00400000L,
269 IPA_OUTBOUND_CHECKSUM_V6 = 0x00800000L,
270};
271
272
273enum qeth_ipa_setdelip_flags {
274 QETH_IPA_SETDELIP_DEFAULT = 0x00L,
275 QETH_IPA_SETIP_VIPA_FLAG = 0x01L,
276 QETH_IPA_SETIP_TAKEOVER_FLAG = 0x02L,
277 QETH_IPA_DELIP_ADDR_2_B_TAKEN_OVER = 0x20L,
278 QETH_IPA_DELIP_VIPA_FLAG = 0x40L,
279 QETH_IPA_DELIP_ADDR_NEEDS_SETIP = 0x80L,
280};
281
282
283enum qeth_ipa_setadp_cmd {
284 IPA_SETADP_QUERY_COMMANDS_SUPPORTED = 0x00000001L,
285 IPA_SETADP_ALTER_MAC_ADDRESS = 0x00000002L,
286 IPA_SETADP_ADD_DELETE_GROUP_ADDRESS = 0x00000004L,
287 IPA_SETADP_ADD_DELETE_FUNCTIONAL_ADDR = 0x00000008L,
288 IPA_SETADP_SET_ADDRESSING_MODE = 0x00000010L,
289 IPA_SETADP_SET_CONFIG_PARMS = 0x00000020L,
290 IPA_SETADP_SET_CONFIG_PARMS_EXTENDED = 0x00000040L,
291 IPA_SETADP_SET_BROADCAST_MODE = 0x00000080L,
292 IPA_SETADP_SEND_OSA_MESSAGE = 0x00000100L,
293 IPA_SETADP_SET_SNMP_CONTROL = 0x00000200L,
294 IPA_SETADP_QUERY_CARD_INFO = 0x00000400L,
295 IPA_SETADP_SET_PROMISC_MODE = 0x00000800L,
296 IPA_SETADP_SET_DIAG_ASSIST = 0x00002000L,
297 IPA_SETADP_SET_ACCESS_CONTROL = 0x00010000L,
298 IPA_SETADP_QUERY_OAT = 0x00080000L,
299 IPA_SETADP_QUERY_SWITCH_ATTRIBUTES = 0x00100000L,
300};
301enum qeth_ipa_mac_ops {
302 CHANGE_ADDR_READ_MAC = 0,
303 CHANGE_ADDR_REPLACE_MAC = 1,
304 CHANGE_ADDR_ADD_MAC = 2,
305 CHANGE_ADDR_DEL_MAC = 4,
306 CHANGE_ADDR_RESET_MAC = 8,
307};
308enum qeth_ipa_addr_ops {
309 CHANGE_ADDR_READ_ADDR = 0,
310 CHANGE_ADDR_ADD_ADDR = 1,
311 CHANGE_ADDR_DEL_ADDR = 2,
312 CHANGE_ADDR_FLUSH_ADDR_TABLE = 4,
313};
314enum qeth_ipa_promisc_modes {
315 SET_PROMISC_MODE_OFF = 0,
316 SET_PROMISC_MODE_ON = 1,
317};
318enum qeth_ipa_isolation_modes {
319 ISOLATION_MODE_NONE = 0x00000000L,
320 ISOLATION_MODE_FWD = 0x00000001L,
321 ISOLATION_MODE_DROP = 0x00000002L,
322};
323enum qeth_ipa_set_access_mode_rc {
324 SET_ACCESS_CTRL_RC_SUCCESS = 0x0000,
325 SET_ACCESS_CTRL_RC_NOT_SUPPORTED = 0x0004,
326 SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED = 0x0008,
327 SET_ACCESS_CTRL_RC_ALREADY_ISOLATED = 0x0010,
328 SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER = 0x0014,
329 SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF = 0x0018,
330 SET_ACCESS_CTRL_RC_REFLREL_UNSUPPORTED = 0x0022,
331 SET_ACCESS_CTRL_RC_REFLREL_FAILED = 0x0024,
332 SET_ACCESS_CTRL_RC_REFLREL_DEACT_FAILED = 0x0028,
333};
334enum qeth_card_info_card_type {
335 CARD_INFO_TYPE_1G_COPPER_A = 0x61,
336 CARD_INFO_TYPE_1G_FIBRE_A = 0x71,
337 CARD_INFO_TYPE_10G_FIBRE_A = 0x91,
338 CARD_INFO_TYPE_1G_COPPER_B = 0xb1,
339 CARD_INFO_TYPE_1G_FIBRE_B = 0xa1,
340 CARD_INFO_TYPE_10G_FIBRE_B = 0xc1,
341};
342enum qeth_card_info_port_mode {
343 CARD_INFO_PORTM_HALFDUPLEX = 0x0002,
344 CARD_INFO_PORTM_FULLDUPLEX = 0x0003,
345};
346enum qeth_card_info_port_speed {
347 CARD_INFO_PORTS_10M = 0x00000005,
348 CARD_INFO_PORTS_100M = 0x00000006,
349 CARD_INFO_PORTS_1G = 0x00000007,
350 CARD_INFO_PORTS_10G = 0x00000008,
351 CARD_INFO_PORTS_25G = 0x0000000A,
352};
353
354
355struct qeth_ipacmd_setdelip4 {
356 __u8 ip_addr[4];
357 __u8 mask[4];
358 __u32 flags;
359} __attribute__ ((packed));
360
361struct qeth_ipacmd_setdelip6 {
362 __u8 ip_addr[16];
363 __u8 mask[16];
364 __u32 flags;
365} __attribute__ ((packed));
366
367struct qeth_ipacmd_setdelipm {
368 __u8 mac[6];
369 __u8 padding[2];
370 __u8 ip6[12];
371 __u8 ip4[4];
372} __attribute__ ((packed));
373
374struct qeth_ipacmd_layer2setdelmac {
375 __u32 mac_length;
376 __u8 mac[6];
377} __attribute__ ((packed));
378
379struct qeth_ipacmd_layer2setdelvlan {
380 __u16 vlan_id;
381} __attribute__ ((packed));
382
383
384struct qeth_ipacmd_setassparms_hdr {
385 __u32 assist_no;
386 __u16 length;
387 __u16 command_code;
388 __u16 return_code;
389 __u8 number_of_replies;
390 __u8 seq_no;
391} __attribute__((packed));
392
393struct qeth_arp_query_data {
394 __u16 request_bits;
395 __u16 reply_bits;
396 __u32 no_entries;
397 char data;
398} __attribute__((packed));
399
400
401struct qeth_arp_query_info {
402 __u32 udata_len;
403 __u16 mask_bits;
404 __u32 udata_offset;
405 __u32 no_entries;
406 char *udata;
407};
408
409
410
411
412enum qeth_ipa_checksum_bits {
413 QETH_IPA_CHECKSUM_IP_HDR = 0x0002,
414 QETH_IPA_CHECKSUM_UDP = 0x0008,
415 QETH_IPA_CHECKSUM_TCP = 0x0010,
416 QETH_IPA_CHECKSUM_LP2LP = 0x0020
417};
418
419
420struct qeth_checksum_cmd {
421 __u32 supported;
422 __u32 enabled;
423} __packed;
424
425enum qeth_ipa_large_send_caps {
426 QETH_IPA_LARGE_SEND_TCP = 0x00000001,
427};
428
429struct qeth_tso_start_data {
430 u32 mss;
431 u32 supported;
432};
433
434
435struct qeth_ipacmd_setassparms {
436 struct qeth_ipacmd_setassparms_hdr hdr;
437 union {
438 __u32 flags_32bit;
439 struct qeth_ipa_caps caps;
440 struct qeth_checksum_cmd chksum;
441 struct qeth_arp_cache_entry arp_entry;
442 struct qeth_arp_query_data query_arp;
443 struct qeth_tso_start_data tso;
444 __u8 ip[16];
445 } data;
446} __attribute__ ((packed));
447
448
449
450struct qeth_set_routing {
451 __u8 type;
452};
453
454
455struct qeth_query_cmds_supp {
456 __u32 no_lantypes_supp;
457 __u8 lan_type;
458 __u8 reserved1[3];
459 __u32 supported_cmds;
460 __u8 reserved2[8];
461} __attribute__ ((packed));
462
463struct qeth_change_addr {
464 u32 cmd;
465 u32 addr_size;
466 u32 no_macs;
467 u8 addr[ETH_ALEN];
468};
469
470struct qeth_snmp_cmd {
471 __u8 token[16];
472 __u32 request;
473 __u32 interface;
474 __u32 returncode;
475 __u32 firmwarelevel;
476 __u32 seqno;
477 __u8 data;
478} __attribute__ ((packed));
479
480struct qeth_snmp_ureq_hdr {
481 __u32 data_len;
482 __u32 req_len;
483 __u32 reserved1;
484 __u32 reserved2;
485} __attribute__ ((packed));
486
487struct qeth_snmp_ureq {
488 struct qeth_snmp_ureq_hdr hdr;
489 struct qeth_snmp_cmd cmd;
490} __attribute__((packed));
491
492
493struct qeth_set_access_ctrl {
494 __u32 subcmd_code;
495 __u8 reserved[8];
496} __attribute__((packed));
497
498struct qeth_query_oat {
499 __u32 subcmd_code;
500 __u8 reserved[12];
501} __packed;
502
503struct qeth_qoat_priv {
504 __u32 buffer_len;
505 __u32 response_len;
506 char *buffer;
507};
508
509struct qeth_query_card_info {
510 __u8 card_type;
511 __u8 reserved1;
512 __u16 port_mode;
513 __u32 port_speed;
514 __u32 reserved2;
515};
516
517#define QETH_SWITCH_FORW_802_1 0x00000001
518#define QETH_SWITCH_FORW_REFL_RELAY 0x00000002
519#define QETH_SWITCH_CAP_RTE 0x00000004
520#define QETH_SWITCH_CAP_ECP 0x00000008
521#define QETH_SWITCH_CAP_VDP 0x00000010
522
523struct qeth_query_switch_attributes {
524 __u8 version;
525 __u8 reserved1;
526 __u16 reserved2;
527 __u32 capabilities;
528 __u32 settings;
529 __u8 reserved3[8];
530};
531
532struct qeth_ipacmd_setadpparms_hdr {
533 __u32 supp_hw_cmds;
534 __u32 reserved1;
535 __u16 cmdlength;
536 __u16 reserved2;
537 __u32 command_code;
538 __u16 return_code;
539 __u8 used_total;
540 __u8 seq_no;
541 __u32 reserved3;
542} __attribute__ ((packed));
543
544struct qeth_ipacmd_setadpparms {
545 struct qeth_ipacmd_setadpparms_hdr hdr;
546 union {
547 struct qeth_query_cmds_supp query_cmds_supp;
548 struct qeth_change_addr change_addr;
549 struct qeth_snmp_cmd snmp;
550 struct qeth_set_access_ctrl set_access_ctrl;
551 struct qeth_query_oat query_oat;
552 struct qeth_query_card_info card_info;
553 struct qeth_query_switch_attributes query_switch_attributes;
554 __u32 mode;
555 } data;
556} __attribute__ ((packed));
557
558
559struct qeth_create_destroy_address {
560 __u8 unique_id[8];
561} __attribute__ ((packed));
562
563
564
565enum qeth_diags_cmds {
566 QETH_DIAGS_CMD_QUERY = 0x0001,
567 QETH_DIAGS_CMD_TRAP = 0x0002,
568 QETH_DIAGS_CMD_TRACE = 0x0004,
569 QETH_DIAGS_CMD_NOLOG = 0x0008,
570 QETH_DIAGS_CMD_DUMP = 0x0010,
571};
572
573enum qeth_diags_trace_types {
574 QETH_DIAGS_TYPE_HIPERSOCKET = 0x02,
575};
576
577enum qeth_diags_trace_cmds {
578 QETH_DIAGS_CMD_TRACE_ENABLE = 0x0001,
579 QETH_DIAGS_CMD_TRACE_DISABLE = 0x0002,
580 QETH_DIAGS_CMD_TRACE_MODIFY = 0x0004,
581 QETH_DIAGS_CMD_TRACE_REPLACE = 0x0008,
582 QETH_DIAGS_CMD_TRACE_QUERY = 0x0010,
583};
584
585enum qeth_diags_trap_action {
586 QETH_DIAGS_TRAP_ARM = 0x01,
587 QETH_DIAGS_TRAP_DISARM = 0x02,
588 QETH_DIAGS_TRAP_CAPTURE = 0x04,
589};
590
591struct qeth_ipacmd_diagass {
592 __u32 host_tod2;
593 __u32:32;
594 __u16 subcmd_len;
595 __u16:16;
596 __u32 subcmd;
597 __u8 type;
598 __u8 action;
599 __u16 options;
600 __u32 ext;
601 __u8 cdata[64];
602} __attribute__ ((packed));
603
604
605
606#define IPA_VNICC_QUERY_CHARS 0x00000000L
607#define IPA_VNICC_QUERY_CMDS 0x00000001L
608#define IPA_VNICC_ENABLE 0x00000002L
609#define IPA_VNICC_DISABLE 0x00000004L
610#define IPA_VNICC_SET_TIMEOUT 0x00000008L
611#define IPA_VNICC_GET_TIMEOUT 0x00000010L
612
613
614#define QETH_VNICC_FLOODING 0x80000000
615#define QETH_VNICC_MCAST_FLOODING 0x40000000
616#define QETH_VNICC_LEARNING 0x20000000
617#define QETH_VNICC_TAKEOVER_SETVMAC 0x10000000
618#define QETH_VNICC_TAKEOVER_LEARNING 0x08000000
619#define QETH_VNICC_BRIDGE_INVISIBLE 0x04000000
620#define QETH_VNICC_RX_BCAST 0x02000000
621
622
623#define QETH_VNICC_ALL 0xff000000
624#define QETH_VNICC_DEFAULT QETH_VNICC_RX_BCAST
625
626#define QETH_VNICC_DEFAULT_TIMEOUT 600
627
628
629struct qeth_ipacmd_vnicc_hdr {
630 u32 sup;
631 u32 cur;
632};
633
634
635struct qeth_vnicc_sub_hdr {
636 u16 data_length;
637 u16 reserved;
638 u32 sub_command;
639};
640
641
642struct qeth_vnicc_query_cmds {
643 u32 vnic_char;
644 u32 sup_cmds;
645};
646
647
648struct qeth_vnicc_set_char {
649 u32 vnic_char;
650};
651
652
653struct qeth_vnicc_getset_timeout {
654 u32 vnic_char;
655 u32 timeout;
656};
657
658
659struct qeth_ipacmd_vnicc {
660 struct qeth_ipacmd_vnicc_hdr hdr;
661 struct qeth_vnicc_sub_hdr sub_hdr;
662 union {
663 struct qeth_vnicc_query_cmds query_cmds;
664 struct qeth_vnicc_set_char set_char;
665 struct qeth_vnicc_getset_timeout getset_timeout;
666 };
667};
668
669
670enum qeth_ipa_sbp_cmd {
671 IPA_SBP_QUERY_COMMANDS_SUPPORTED = 0x00000000L,
672 IPA_SBP_RESET_BRIDGE_PORT_ROLE = 0x00000001L,
673 IPA_SBP_SET_PRIMARY_BRIDGE_PORT = 0x00000002L,
674 IPA_SBP_SET_SECONDARY_BRIDGE_PORT = 0x00000004L,
675 IPA_SBP_QUERY_BRIDGE_PORTS = 0x00000008L,
676 IPA_SBP_BRIDGE_PORT_STATE_CHANGE = 0x00000010L,
677};
678
679struct net_if_token {
680 __u16 devnum;
681 __u8 cssid;
682 __u8 iid;
683 __u8 ssid;
684 __u8 chpid;
685 __u16 chid;
686} __packed;
687
688struct mac_addr_lnid {
689 __u8 mac[6];
690 __u16 lnid;
691} __packed;
692
693struct qeth_ipacmd_sbp_hdr {
694 __u32 supported_sbp_cmds;
695 __u32 enabled_sbp_cmds;
696 __u16 cmdlength;
697 __u16 reserved1;
698 __u32 command_code;
699 __u16 return_code;
700 __u8 used_total;
701 __u8 seq_no;
702 __u32 reserved2;
703} __packed;
704
705struct qeth_sbp_query_cmds_supp {
706 __u32 supported_cmds;
707 __u32 reserved;
708} __packed;
709
710struct qeth_sbp_reset_role {
711} __packed;
712
713struct qeth_sbp_set_primary {
714 struct net_if_token token;
715} __packed;
716
717struct qeth_sbp_set_secondary {
718} __packed;
719
720struct qeth_sbp_port_entry {
721 __u8 role;
722 __u8 state;
723 __u8 reserved1;
724 __u8 reserved2;
725 struct net_if_token token;
726} __packed;
727
728struct qeth_sbp_query_ports {
729 __u8 primary_bp_supported;
730 __u8 secondary_bp_supported;
731 __u8 num_entries;
732 __u8 entry_length;
733 struct qeth_sbp_port_entry entry[];
734} __packed;
735
736struct qeth_sbp_state_change {
737 __u8 primary_bp_supported;
738 __u8 secondary_bp_supported;
739 __u8 num_entries;
740 __u8 entry_length;
741 struct qeth_sbp_port_entry entry[];
742} __packed;
743
744struct qeth_ipacmd_setbridgeport {
745 struct qeth_ipacmd_sbp_hdr hdr;
746 union {
747 struct qeth_sbp_query_cmds_supp query_cmds_supp;
748 struct qeth_sbp_reset_role reset_role;
749 struct qeth_sbp_set_primary set_primary;
750 struct qeth_sbp_set_secondary set_secondary;
751 struct qeth_sbp_query_ports query_ports;
752 struct qeth_sbp_state_change state_change;
753 } data;
754} __packed;
755
756
757
758enum qeth_ipa_addr_change_code {
759 IPA_ADDR_CHANGE_CODE_VLANID = 0x01,
760 IPA_ADDR_CHANGE_CODE_MACADDR = 0x02,
761 IPA_ADDR_CHANGE_CODE_REMOVAL = 0x80,
762};
763
764struct qeth_ipacmd_addr_change_entry {
765 struct net_if_token token;
766 struct mac_addr_lnid addr_lnid;
767 __u8 change_code;
768 __u8 reserved1;
769 __u16 reserved2;
770} __packed;
771
772struct qeth_ipacmd_addr_change {
773 __u8 lost_event_mask;
774 __u8 reserved;
775 __u16 num_entries;
776 struct qeth_ipacmd_addr_change_entry entry[];
777} __packed;
778
779
780struct qeth_ipacmd_hdr {
781 __u8 command;
782 __u8 initiator;
783 __u16 seqno;
784 __u16 return_code;
785 __u8 adapter_type;
786 __u8 rel_adapter_no;
787 __u8 prim_version_no;
788 __u8 param_count;
789 __u16 prot_version;
790 __u32 ipa_supported;
791 __u32 ipa_enabled;
792} __attribute__ ((packed));
793
794
795struct qeth_ipa_cmd {
796 struct qeth_ipacmd_hdr hdr;
797 union {
798 struct qeth_ipacmd_setdelip4 setdelip4;
799 struct qeth_ipacmd_setdelip6 setdelip6;
800 struct qeth_ipacmd_setdelipm setdelipm;
801 struct qeth_ipacmd_setassparms setassparms;
802 struct qeth_ipacmd_layer2setdelmac setdelmac;
803 struct qeth_ipacmd_layer2setdelvlan setdelvlan;
804 struct qeth_create_destroy_address create_destroy_addr;
805 struct qeth_ipacmd_setadpparms setadapterparms;
806 struct qeth_set_routing setrtg;
807 struct qeth_ipacmd_diagass diagass;
808 struct qeth_ipacmd_setbridgeport sbp;
809 struct qeth_ipacmd_addr_change addrchange;
810 struct qeth_ipacmd_vnicc vnicc;
811 } data;
812} __attribute__ ((packed));
813
814
815
816
817
818
819enum qeth_ipa_arp_return_codes {
820 QETH_IPA_ARP_RC_SUCCESS = 0x0000,
821 QETH_IPA_ARP_RC_FAILED = 0x0001,
822 QETH_IPA_ARP_RC_NOTSUPP = 0x0002,
823 QETH_IPA_ARP_RC_OUT_OF_RANGE = 0x0003,
824 QETH_IPA_ARP_RC_Q_NOTSUPP = 0x0004,
825 QETH_IPA_ARP_RC_Q_NO_DATA = 0x0008,
826};
827
828extern const char *qeth_get_ipa_msg(enum qeth_ipa_return_codes rc);
829extern const char *qeth_get_ipa_cmd_name(enum qeth_ipa_cmds cmd);
830
831#define QETH_SETASS_BASE_LEN (sizeof(struct qeth_ipacmd_hdr) + \
832 sizeof(struct qeth_ipacmd_setassparms_hdr))
833#define QETH_IPA_ARP_DATA_POS(buffer) (buffer + IPA_PDU_HEADER_SIZE + \
834 QETH_SETASS_BASE_LEN)
835#define QETH_SETADP_BASE_LEN (sizeof(struct qeth_ipacmd_hdr) + \
836 sizeof(struct qeth_ipacmd_setadpparms_hdr))
837#define QETH_SNMP_SETADP_CMDLENGTH 16
838
839#define QETH_ARP_DATA_SIZE 3968
840#define QETH_ARP_CMD_LEN (QETH_ARP_DATA_SIZE + 8)
841
842#define IS_IPA_REPLY(cmd) ((cmd->hdr.initiator == IPA_CMD_INITIATOR_HOST) || \
843 (cmd->hdr.initiator == IPA_CMD_INITIATOR_OSA_REPLY))
844
845
846
847
848
849extern unsigned char CM_ENABLE[];
850#define CM_ENABLE_SIZE 0x63
851#define QETH_CM_ENABLE_ISSUER_RM_TOKEN(buffer) (buffer + 0x2c)
852#define QETH_CM_ENABLE_FILTER_TOKEN(buffer) (buffer + 0x53)
853#define QETH_CM_ENABLE_USER_DATA(buffer) (buffer + 0x5b)
854
855#define QETH_CM_ENABLE_RESP_FILTER_TOKEN(buffer) \
856 (PDU_ENCAPSULATION(buffer) + 0x13)
857
858
859extern unsigned char CM_SETUP[];
860#define CM_SETUP_SIZE 0x64
861#define QETH_CM_SETUP_DEST_ADDR(buffer) (buffer + 0x2c)
862#define QETH_CM_SETUP_CONNECTION_TOKEN(buffer) (buffer + 0x51)
863#define QETH_CM_SETUP_FILTER_TOKEN(buffer) (buffer + 0x5a)
864
865#define QETH_CM_SETUP_RESP_DEST_ADDR(buffer) \
866 (PDU_ENCAPSULATION(buffer) + 0x1a)
867
868extern unsigned char ULP_ENABLE[];
869#define ULP_ENABLE_SIZE 0x6b
870#define QETH_ULP_ENABLE_LINKNUM(buffer) (buffer + 0x61)
871#define QETH_ULP_ENABLE_DEST_ADDR(buffer) (buffer + 0x2c)
872#define QETH_ULP_ENABLE_FILTER_TOKEN(buffer) (buffer + 0x53)
873#define QETH_ULP_ENABLE_PORTNAME_AND_LL(buffer) (buffer + 0x62)
874#define QETH_ULP_ENABLE_RESP_FILTER_TOKEN(buffer) \
875 (PDU_ENCAPSULATION(buffer) + 0x13)
876#define QETH_ULP_ENABLE_RESP_MAX_MTU(buffer) \
877 (PDU_ENCAPSULATION(buffer) + 0x1f)
878#define QETH_ULP_ENABLE_RESP_DIFINFO_LEN(buffer) \
879 (PDU_ENCAPSULATION(buffer) + 0x17)
880#define QETH_ULP_ENABLE_RESP_LINK_TYPE(buffer) \
881 (PDU_ENCAPSULATION(buffer) + 0x2b)
882
883#define QETH_PROT_LAYER2 0x08
884#define QETH_PROT_TCPIP 0x03
885#define QETH_PROT_OSN2 0x0a
886#define QETH_ULP_ENABLE_PROT_TYPE(buffer) (buffer + 0x50)
887#define QETH_IPA_CMD_PROT_TYPE(buffer) (buffer + 0x19)
888
889extern unsigned char ULP_SETUP[];
890#define ULP_SETUP_SIZE 0x6c
891#define QETH_ULP_SETUP_DEST_ADDR(buffer) (buffer + 0x2c)
892#define QETH_ULP_SETUP_CONNECTION_TOKEN(buffer) (buffer + 0x51)
893#define QETH_ULP_SETUP_FILTER_TOKEN(buffer) (buffer + 0x5a)
894#define QETH_ULP_SETUP_CUA(buffer) (buffer + 0x68)
895#define QETH_ULP_SETUP_REAL_DEVADDR(buffer) (buffer + 0x6a)
896
897#define QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(buffer) \
898 (PDU_ENCAPSULATION(buffer) + 0x1a)
899
900
901extern unsigned char DM_ACT[];
902#define DM_ACT_SIZE 0x55
903#define QETH_DM_ACT_DEST_ADDR(buffer) (buffer + 0x2c)
904#define QETH_DM_ACT_CONNECTION_TOKEN(buffer) (buffer + 0x51)
905
906
907
908#define QETH_TRANSPORT_HEADER_SEQ_NO(buffer) (buffer + 4)
909#define QETH_PDU_HEADER_SEQ_NO(buffer) (buffer + 0x1c)
910#define QETH_PDU_HEADER_ACK_SEQ_NO(buffer) (buffer + 0x20)
911
912extern unsigned char IDX_ACTIVATE_READ[];
913extern unsigned char IDX_ACTIVATE_WRITE[];
914
915#define IDX_ACTIVATE_SIZE 0x22
916#define QETH_IDX_ACT_PNO(buffer) (buffer+0x0b)
917#define QETH_IDX_ACT_ISSUER_RM_TOKEN(buffer) (buffer + 0x0c)
918#define QETH_IDX_NO_PORTNAME_REQUIRED(buffer) ((buffer)[0x0b] & 0x80)
919#define QETH_IDX_ACT_FUNC_LEVEL(buffer) (buffer + 0x10)
920#define QETH_IDX_ACT_DATASET_NAME(buffer) (buffer + 0x16)
921#define QETH_IDX_ACT_QDIO_DEV_CUA(buffer) (buffer + 0x1e)
922#define QETH_IDX_ACT_QDIO_DEV_REALADDR(buffer) (buffer + 0x20)
923#define QETH_IS_IDX_ACT_POS_REPLY(buffer) (((buffer)[0x08] & 3) == 2)
924#define QETH_IDX_REPLY_LEVEL(buffer) (buffer + 0x12)
925#define QETH_IDX_ACT_CAUSE_CODE(buffer) (buffer)[0x09]
926#define QETH_IDX_ACT_ERR_EXCL 0x19
927#define QETH_IDX_ACT_ERR_AUTH 0x1E
928#define QETH_IDX_ACT_ERR_AUTH_USER 0x20
929
930#define PDU_ENCAPSULATION(buffer) \
931 (buffer + *(buffer + (*(buffer + 0x0b)) + \
932 *(buffer + *(buffer + 0x0b) + 0x11) + 0x07))
933
934#define IS_IPA(buffer) \
935 ((buffer) && \
936 (*(buffer + ((*(buffer + 0x0b)) + 4)) == 0xc1))
937
938#endif
939
