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35#include <linux/kernel.h>
36#include <linux/types.h>
37#include <linux/pci.h>
38#include <linux/list.h>
39#include <linux/moduleparam.h>
40#include <linux/module.h>
41#include <linux/spinlock.h>
42#include <linux/interrupt.h>
43#include <linux/delay.h>
44#include <linux/uio.h>
45#include <linux/uaccess.h>
46#include <linux/fs.h>
47#include <linux/compat.h>
48#include <linux/blkdev.h>
49#include <linux/poll.h>
50
51#include <scsi/scsi.h>
52#include <scsi/scsi_cmnd.h>
53#include <scsi/scsi_device.h>
54#include <scsi/scsi_host.h>
55
56#include "megaraid_sas_fusion.h"
57#include "megaraid_sas.h"
58#include <asm/div64.h>
59
60#define LB_PENDING_CMDS_DEFAULT 4
61static unsigned int lb_pending_cmds = LB_PENDING_CMDS_DEFAULT;
62module_param(lb_pending_cmds, int, S_IRUGO);
63MODULE_PARM_DESC(lb_pending_cmds, "Change raid-1 load balancing outstanding "
64 "threshold. Valid Values are 1-128. Default: 4");
65
66
67#define ABS_DIFF(a, b) (((a) > (b)) ? ((a) - (b)) : ((b) - (a)))
68#define MR_LD_STATE_OPTIMAL 3
69
70#define SPAN_ROW_SIZE(map, ld, index_) (MR_LdSpanPtrGet(ld, index_, map)->spanRowSize)
71#define SPAN_ROW_DATA_SIZE(map_, ld, index_) (MR_LdSpanPtrGet(ld, index_, map)->spanRowDataSize)
72#define SPAN_INVALID 0xff
73
74
75static void mr_update_span_set(struct MR_DRV_RAID_MAP_ALL *map,
76 PLD_SPAN_INFO ldSpanInfo);
77static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld,
78 u64 stripRow, u16 stripRef, struct IO_REQUEST_INFO *io_info,
79 struct RAID_CONTEXT *pRAID_Context, struct MR_DRV_RAID_MAP_ALL *map);
80static u64 get_row_from_strip(struct megasas_instance *instance, u32 ld,
81 u64 strip, struct MR_DRV_RAID_MAP_ALL *map);
82
83u32 mega_mod64(u64 dividend, u32 divisor)
84{
85 u64 d;
86 u32 remainder;
87
88 if (!divisor)
89 printk(KERN_ERR "megasas : DIVISOR is zero, in div fn\n");
90 d = dividend;
91 remainder = do_div(d, divisor);
92 return remainder;
93}
94
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99
100
101u64 mega_div64_32(uint64_t dividend, uint32_t divisor)
102{
103 u32 remainder;
104 u64 d;
105
106 if (!divisor)
107 printk(KERN_ERR "megasas : DIVISOR is zero in mod fn\n");
108
109 d = dividend;
110 remainder = do_div(d, divisor);
111
112 return d;
113}
114
115struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map)
116{
117 return &map->raidMap.ldSpanMap[ld].ldRaid;
118}
119
120static struct MR_SPAN_BLOCK_INFO *MR_LdSpanInfoGet(u32 ld,
121 struct MR_DRV_RAID_MAP_ALL
122 *map)
123{
124 return &map->raidMap.ldSpanMap[ld].spanBlock[0];
125}
126
127static u8 MR_LdDataArmGet(u32 ld, u32 armIdx, struct MR_DRV_RAID_MAP_ALL *map)
128{
129 return map->raidMap.ldSpanMap[ld].dataArmMap[armIdx];
130}
131
132u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map)
133{
134 return le16_to_cpu(map->raidMap.arMapInfo[ar].pd[arm]);
135}
136
137u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map)
138{
139 return le16_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].span.arrayRef);
140}
141
142__le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map)
143{
144 return map->raidMap.devHndlInfo[pd].curDevHdl;
145}
146
147static u8 MR_PdInterfaceTypeGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map)
148{
149 return map->raidMap.devHndlInfo[pd].interfaceType;
150}
151
152u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map)
153{
154 return le16_to_cpu(map->raidMap.ldSpanMap[ld].ldRaid.targetId);
155}
156
157u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map)
158{
159 return map->raidMap.ldTgtIdToLd[ldTgtId];
160}
161
162static struct MR_LD_SPAN *MR_LdSpanPtrGet(u32 ld, u32 span,
163 struct MR_DRV_RAID_MAP_ALL *map)
164{
165 return &map->raidMap.ldSpanMap[ld].spanBlock[span].span;
166}
167
168
169
170
171static int MR_PopulateDrvRaidMap(struct megasas_instance *instance, u64 map_id)
172{
173 struct fusion_context *fusion = instance->ctrl_context;
174 struct MR_FW_RAID_MAP_ALL *fw_map_old = NULL;
175 struct MR_FW_RAID_MAP *pFwRaidMap = NULL;
176 int i, j;
177 u16 ld_count;
178 struct MR_FW_RAID_MAP_DYNAMIC *fw_map_dyn;
179 struct MR_FW_RAID_MAP_EXT *fw_map_ext;
180 struct MR_RAID_MAP_DESC_TABLE *desc_table;
181
182
183 struct MR_DRV_RAID_MAP_ALL *drv_map =
184 fusion->ld_drv_map[(map_id & 1)];
185 struct MR_DRV_RAID_MAP *pDrvRaidMap = &drv_map->raidMap;
186 void *raid_map_data = NULL;
187
188 memset(drv_map, 0, fusion->drv_map_sz);
189 memset(pDrvRaidMap->ldTgtIdToLd,
190 0xff, (sizeof(u16) * MAX_LOGICAL_DRIVES_DYN));
191
192 if (instance->max_raid_mapsize) {
193 fw_map_dyn = fusion->ld_map[(map_id & 1)];
194 desc_table =
195 (struct MR_RAID_MAP_DESC_TABLE *)((void *)fw_map_dyn + le32_to_cpu(fw_map_dyn->desc_table_offset));
196 if (desc_table != fw_map_dyn->raid_map_desc_table)
197 dev_dbg(&instance->pdev->dev, "offsets of desc table are not matching desc %p original %p\n",
198 desc_table, fw_map_dyn->raid_map_desc_table);
199
200 ld_count = (u16)le16_to_cpu(fw_map_dyn->ld_count);
201 pDrvRaidMap->ldCount = (__le16)cpu_to_le16(ld_count);
202 pDrvRaidMap->fpPdIoTimeoutSec =
203 fw_map_dyn->fp_pd_io_timeout_sec;
204 pDrvRaidMap->totalSize =
205 cpu_to_le32(sizeof(struct MR_DRV_RAID_MAP_ALL));
206
207 raid_map_data = (void *)fw_map_dyn +
208 le32_to_cpu(fw_map_dyn->desc_table_offset) +
209 le32_to_cpu(fw_map_dyn->desc_table_size);
210
211 for (i = 0; i < le32_to_cpu(fw_map_dyn->desc_table_num_elements); ++i) {
212 switch (le32_to_cpu(desc_table->raid_map_desc_type)) {
213 case RAID_MAP_DESC_TYPE_DEVHDL_INFO:
214 fw_map_dyn->dev_hndl_info =
215 (struct MR_DEV_HANDLE_INFO *)(raid_map_data + le32_to_cpu(desc_table->raid_map_desc_offset));
216 memcpy(pDrvRaidMap->devHndlInfo,
217 fw_map_dyn->dev_hndl_info,
218 sizeof(struct MR_DEV_HANDLE_INFO) *
219 le32_to_cpu(desc_table->raid_map_desc_elements));
220 break;
221 case RAID_MAP_DESC_TYPE_TGTID_INFO:
222 fw_map_dyn->ld_tgt_id_to_ld =
223 (u16 *)(raid_map_data +
224 le32_to_cpu(desc_table->raid_map_desc_offset));
225 for (j = 0; j < le32_to_cpu(desc_table->raid_map_desc_elements); j++) {
226 pDrvRaidMap->ldTgtIdToLd[j] =
227 le16_to_cpu(fw_map_dyn->ld_tgt_id_to_ld[j]);
228 }
229 break;
230 case RAID_MAP_DESC_TYPE_ARRAY_INFO:
231 fw_map_dyn->ar_map_info =
232 (struct MR_ARRAY_INFO *)
233 (raid_map_data + le32_to_cpu(desc_table->raid_map_desc_offset));
234 memcpy(pDrvRaidMap->arMapInfo,
235 fw_map_dyn->ar_map_info,
236 sizeof(struct MR_ARRAY_INFO) *
237 le32_to_cpu(desc_table->raid_map_desc_elements));
238 break;
239 case RAID_MAP_DESC_TYPE_SPAN_INFO:
240 fw_map_dyn->ld_span_map =
241 (struct MR_LD_SPAN_MAP *)
242 (raid_map_data +
243 le32_to_cpu(desc_table->raid_map_desc_offset));
244 memcpy(pDrvRaidMap->ldSpanMap,
245 fw_map_dyn->ld_span_map,
246 sizeof(struct MR_LD_SPAN_MAP) *
247 le32_to_cpu(desc_table->raid_map_desc_elements));
248 break;
249 default:
250 dev_dbg(&instance->pdev->dev, "wrong number of desctableElements %d\n",
251 fw_map_dyn->desc_table_num_elements);
252 }
253 ++desc_table;
254 }
255
256 } else if (instance->supportmax256vd) {
257 fw_map_ext =
258 (struct MR_FW_RAID_MAP_EXT *)fusion->ld_map[(map_id & 1)];
259 ld_count = (u16)le16_to_cpu(fw_map_ext->ldCount);
260 if (ld_count > MAX_LOGICAL_DRIVES_EXT) {
261 dev_dbg(&instance->pdev->dev, "megaraid_sas: LD count exposed in RAID map in not valid\n");
262 return 1;
263 }
264
265 pDrvRaidMap->ldCount = (__le16)cpu_to_le16(ld_count);
266 pDrvRaidMap->fpPdIoTimeoutSec = fw_map_ext->fpPdIoTimeoutSec;
267 for (i = 0; i < (MAX_LOGICAL_DRIVES_EXT); i++)
268 pDrvRaidMap->ldTgtIdToLd[i] =
269 (u16)fw_map_ext->ldTgtIdToLd[i];
270 memcpy(pDrvRaidMap->ldSpanMap, fw_map_ext->ldSpanMap,
271 sizeof(struct MR_LD_SPAN_MAP) * ld_count);
272 memcpy(pDrvRaidMap->arMapInfo, fw_map_ext->arMapInfo,
273 sizeof(struct MR_ARRAY_INFO) * MAX_API_ARRAYS_EXT);
274 memcpy(pDrvRaidMap->devHndlInfo, fw_map_ext->devHndlInfo,
275 sizeof(struct MR_DEV_HANDLE_INFO) *
276 MAX_RAIDMAP_PHYSICAL_DEVICES);
277
278
279
280
281 pDrvRaidMap->totalSize =
282 cpu_to_le32(sizeof(struct MR_FW_RAID_MAP_EXT));
283 } else {
284 fw_map_old = (struct MR_FW_RAID_MAP_ALL *)
285 fusion->ld_map[(map_id & 1)];
286 pFwRaidMap = &fw_map_old->raidMap;
287 ld_count = (u16)le32_to_cpu(pFwRaidMap->ldCount);
288 if (ld_count > MAX_LOGICAL_DRIVES) {
289 dev_dbg(&instance->pdev->dev,
290 "LD count exposed in RAID map in not valid\n");
291 return 1;
292 }
293
294 pDrvRaidMap->totalSize = pFwRaidMap->totalSize;
295 pDrvRaidMap->ldCount = (__le16)cpu_to_le16(ld_count);
296 pDrvRaidMap->fpPdIoTimeoutSec = pFwRaidMap->fpPdIoTimeoutSec;
297 for (i = 0; i < MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS; i++)
298 pDrvRaidMap->ldTgtIdToLd[i] =
299 (u8)pFwRaidMap->ldTgtIdToLd[i];
300 for (i = 0; i < ld_count; i++) {
301 pDrvRaidMap->ldSpanMap[i] = pFwRaidMap->ldSpanMap[i];
302 }
303 memcpy(pDrvRaidMap->arMapInfo, pFwRaidMap->arMapInfo,
304 sizeof(struct MR_ARRAY_INFO) * MAX_RAIDMAP_ARRAYS);
305 memcpy(pDrvRaidMap->devHndlInfo, pFwRaidMap->devHndlInfo,
306 sizeof(struct MR_DEV_HANDLE_INFO) *
307 MAX_RAIDMAP_PHYSICAL_DEVICES);
308 }
309
310 return 0;
311}
312
313
314
315
316u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id)
317{
318 struct fusion_context *fusion;
319 struct MR_DRV_RAID_MAP_ALL *drv_map;
320 struct MR_DRV_RAID_MAP *pDrvRaidMap;
321 struct LD_LOAD_BALANCE_INFO *lbInfo;
322 PLD_SPAN_INFO ldSpanInfo;
323 struct MR_LD_RAID *raid;
324 u16 num_lds, i;
325 u16 ld;
326 u32 expected_size;
327
328 if (MR_PopulateDrvRaidMap(instance, map_id))
329 return 0;
330
331 fusion = instance->ctrl_context;
332 drv_map = fusion->ld_drv_map[(map_id & 1)];
333 pDrvRaidMap = &drv_map->raidMap;
334
335 lbInfo = fusion->load_balance_info;
336 ldSpanInfo = fusion->log_to_span;
337
338 if (instance->max_raid_mapsize)
339 expected_size = sizeof(struct MR_DRV_RAID_MAP_ALL);
340 else if (instance->supportmax256vd)
341 expected_size = sizeof(struct MR_FW_RAID_MAP_EXT);
342 else
343 expected_size =
344 (sizeof(struct MR_FW_RAID_MAP) - sizeof(struct MR_LD_SPAN_MAP) +
345 (sizeof(struct MR_LD_SPAN_MAP) * le16_to_cpu(pDrvRaidMap->ldCount)));
346
347 if (le32_to_cpu(pDrvRaidMap->totalSize) != expected_size) {
348 dev_dbg(&instance->pdev->dev, "megasas: map info structure size 0x%x",
349 le32_to_cpu(pDrvRaidMap->totalSize));
350 dev_dbg(&instance->pdev->dev, "is not matching expected size 0x%x\n",
351 (unsigned int)expected_size);
352 dev_err(&instance->pdev->dev, "megasas: span map %x, pDrvRaidMap->totalSize : %x\n",
353 (unsigned int)sizeof(struct MR_LD_SPAN_MAP),
354 le32_to_cpu(pDrvRaidMap->totalSize));
355 return 0;
356 }
357
358 if (instance->UnevenSpanSupport)
359 mr_update_span_set(drv_map, ldSpanInfo);
360
361 if (lbInfo)
362 mr_update_load_balance_params(drv_map, lbInfo);
363
364 num_lds = le16_to_cpu(drv_map->raidMap.ldCount);
365
366
367 for (i = 0; (num_lds > 0) && (i < MAX_LOGICAL_DRIVES_EXT); i++) {
368 ld = MR_TargetIdToLdGet(i, drv_map);
369
370
371 if (ld >= (MAX_LOGICAL_DRIVES_EXT - 1))
372 continue;
373
374 raid = MR_LdRaidGet(ld, drv_map);
375 le32_to_cpus((u32 *)&raid->capability);
376
377 num_lds--;
378 }
379
380 return 1;
381}
382
383u32 MR_GetSpanBlock(u32 ld, u64 row, u64 *span_blk,
384 struct MR_DRV_RAID_MAP_ALL *map)
385{
386 struct MR_SPAN_BLOCK_INFO *pSpanBlock = MR_LdSpanInfoGet(ld, map);
387 struct MR_QUAD_ELEMENT *quad;
388 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
389 u32 span, j;
390
391 for (span = 0; span < raid->spanDepth; span++, pSpanBlock++) {
392
393 for (j = 0; j < le32_to_cpu(pSpanBlock->block_span_info.noElements); j++) {
394 quad = &pSpanBlock->block_span_info.quad[j];
395
396 if (le32_to_cpu(quad->diff) == 0)
397 return SPAN_INVALID;
398 if (le64_to_cpu(quad->logStart) <= row && row <=
399 le64_to_cpu(quad->logEnd) && (mega_mod64(row - le64_to_cpu(quad->logStart),
400 le32_to_cpu(quad->diff))) == 0) {
401 if (span_blk != NULL) {
402 u64 blk, debugBlk;
403 blk = mega_div64_32((row-le64_to_cpu(quad->logStart)), le32_to_cpu(quad->diff));
404 debugBlk = blk;
405
406 blk = (blk + le64_to_cpu(quad->offsetInSpan)) << raid->stripeShift;
407 *span_blk = blk;
408 }
409 return span;
410 }
411 }
412 }
413 return SPAN_INVALID;
414}
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433
434u32 mr_spanset_get_span_block(struct megasas_instance *instance,
435 u32 ld, u64 row, u64 *span_blk, struct MR_DRV_RAID_MAP_ALL *map)
436{
437 struct fusion_context *fusion = instance->ctrl_context;
438 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
439 LD_SPAN_SET *span_set;
440 struct MR_QUAD_ELEMENT *quad;
441 u32 span, info;
442 PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span;
443
444 for (info = 0; info < MAX_QUAD_DEPTH; info++) {
445 span_set = &(ldSpanInfo[ld].span_set[info]);
446
447 if (span_set->span_row_data_width == 0)
448 break;
449
450 if (row > span_set->data_row_end)
451 continue;
452
453 for (span = 0; span < raid->spanDepth; span++)
454 if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
455 block_span_info.noElements) >= info+1) {
456 quad = &map->raidMap.ldSpanMap[ld].
457 spanBlock[span].
458 block_span_info.quad[info];
459 if (le32_to_cpu(quad->diff) == 0)
460 return SPAN_INVALID;
461 if (le64_to_cpu(quad->logStart) <= row &&
462 row <= le64_to_cpu(quad->logEnd) &&
463 (mega_mod64(row - le64_to_cpu(quad->logStart),
464 le32_to_cpu(quad->diff))) == 0) {
465 if (span_blk != NULL) {
466 u64 blk;
467 blk = mega_div64_32
468 ((row - le64_to_cpu(quad->logStart)),
469 le32_to_cpu(quad->diff));
470 blk = (blk + le64_to_cpu(quad->offsetInSpan))
471 << raid->stripeShift;
472 *span_blk = blk;
473 }
474 return span;
475 }
476 }
477 }
478 return SPAN_INVALID;
479}
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497static u64 get_row_from_strip(struct megasas_instance *instance,
498 u32 ld, u64 strip, struct MR_DRV_RAID_MAP_ALL *map)
499{
500 struct fusion_context *fusion = instance->ctrl_context;
501 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
502 LD_SPAN_SET *span_set;
503 PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span;
504 u32 info, strip_offset, span, span_offset;
505 u64 span_set_Strip, span_set_Row, retval;
506
507 for (info = 0; info < MAX_QUAD_DEPTH; info++) {
508 span_set = &(ldSpanInfo[ld].span_set[info]);
509
510 if (span_set->span_row_data_width == 0)
511 break;
512 if (strip > span_set->data_strip_end)
513 continue;
514
515 span_set_Strip = strip - span_set->data_strip_start;
516 strip_offset = mega_mod64(span_set_Strip,
517 span_set->span_row_data_width);
518 span_set_Row = mega_div64_32(span_set_Strip,
519 span_set->span_row_data_width) * span_set->diff;
520 for (span = 0, span_offset = 0; span < raid->spanDepth; span++)
521 if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
522 block_span_info.noElements) >= info+1) {
523 if (strip_offset >=
524 span_set->strip_offset[span])
525 span_offset++;
526 else
527 break;
528 }
529
530 retval = (span_set->data_row_start + span_set_Row +
531 (span_offset - 1));
532 return retval;
533 }
534 return -1LLU;
535}
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554static u64 get_strip_from_row(struct megasas_instance *instance,
555 u32 ld, u64 row, struct MR_DRV_RAID_MAP_ALL *map)
556{
557 struct fusion_context *fusion = instance->ctrl_context;
558 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
559 LD_SPAN_SET *span_set;
560 struct MR_QUAD_ELEMENT *quad;
561 PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span;
562 u32 span, info;
563 u64 strip;
564
565 for (info = 0; info < MAX_QUAD_DEPTH; info++) {
566 span_set = &(ldSpanInfo[ld].span_set[info]);
567
568 if (span_set->span_row_data_width == 0)
569 break;
570 if (row > span_set->data_row_end)
571 continue;
572
573 for (span = 0; span < raid->spanDepth; span++)
574 if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
575 block_span_info.noElements) >= info+1) {
576 quad = &map->raidMap.ldSpanMap[ld].
577 spanBlock[span].block_span_info.quad[info];
578 if (le64_to_cpu(quad->logStart) <= row &&
579 row <= le64_to_cpu(quad->logEnd) &&
580 mega_mod64((row - le64_to_cpu(quad->logStart)),
581 le32_to_cpu(quad->diff)) == 0) {
582 strip = mega_div64_32
583 (((row - span_set->data_row_start)
584 - le64_to_cpu(quad->logStart)),
585 le32_to_cpu(quad->diff));
586 strip *= span_set->span_row_data_width;
587 strip += span_set->data_strip_start;
588 strip += span_set->strip_offset[span];
589 return strip;
590 }
591 }
592 }
593 dev_err(&instance->pdev->dev, "get_strip_from_row"
594 "returns invalid strip for ld=%x, row=%lx\n",
595 ld, (long unsigned int)row);
596 return -1;
597}
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615static u32 get_arm_from_strip(struct megasas_instance *instance,
616 u32 ld, u64 strip, struct MR_DRV_RAID_MAP_ALL *map)
617{
618 struct fusion_context *fusion = instance->ctrl_context;
619 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
620 LD_SPAN_SET *span_set;
621 PLD_SPAN_INFO ldSpanInfo = fusion->log_to_span;
622 u32 info, strip_offset, span, span_offset, retval;
623
624 for (info = 0 ; info < MAX_QUAD_DEPTH; info++) {
625 span_set = &(ldSpanInfo[ld].span_set[info]);
626
627 if (span_set->span_row_data_width == 0)
628 break;
629 if (strip > span_set->data_strip_end)
630 continue;
631
632 strip_offset = (uint)mega_mod64
633 ((strip - span_set->data_strip_start),
634 span_set->span_row_data_width);
635
636 for (span = 0, span_offset = 0; span < raid->spanDepth; span++)
637 if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
638 block_span_info.noElements) >= info+1) {
639 if (strip_offset >=
640 span_set->strip_offset[span])
641 span_offset =
642 span_set->strip_offset[span];
643 else
644 break;
645 }
646
647 retval = (strip_offset - span_offset);
648 return retval;
649 }
650
651 dev_err(&instance->pdev->dev, "get_arm_from_strip"
652 "returns invalid arm for ld=%x strip=%lx\n",
653 ld, (long unsigned int)strip);
654
655 return -1;
656}
657
658
659u8 get_arm(struct megasas_instance *instance, u32 ld, u8 span, u64 stripe,
660 struct MR_DRV_RAID_MAP_ALL *map)
661{
662 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
663
664 u32 arm = 0;
665
666 switch (raid->level) {
667 case 0:
668 case 5:
669 case 6:
670 arm = mega_mod64(stripe, SPAN_ROW_SIZE(map, ld, span));
671 break;
672 case 1:
673
674 arm = get_arm_from_strip(instance, ld, stripe, map);
675 if (arm != -1U)
676 arm *= 2;
677 break;
678 }
679
680 return arm;
681}
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701static u8 mr_spanset_get_phy_params(struct megasas_instance *instance, u32 ld,
702 u64 stripRow, u16 stripRef, struct IO_REQUEST_INFO *io_info,
703 struct RAID_CONTEXT *pRAID_Context,
704 struct MR_DRV_RAID_MAP_ALL *map)
705{
706 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
707 u32 pd, arRef, r1_alt_pd;
708 u8 physArm, span;
709 u64 row;
710 u8 retval = true;
711 u64 *pdBlock = &io_info->pdBlock;
712 __le16 *pDevHandle = &io_info->devHandle;
713 u8 *pPdInterface = &io_info->pd_interface;
714 u32 logArm, rowMod, armQ, arm;
715 struct fusion_context *fusion;
716
717 fusion = instance->ctrl_context;
718 *pDevHandle = cpu_to_le16(MR_DEVHANDLE_INVALID);
719
720
721 row = io_info->start_row;
722 span = io_info->start_span;
723
724
725 if (raid->level == 6) {
726 logArm = get_arm_from_strip(instance, ld, stripRow, map);
727 if (logArm == -1U)
728 return false;
729 rowMod = mega_mod64(row, SPAN_ROW_SIZE(map, ld, span));
730 armQ = SPAN_ROW_SIZE(map, ld, span) - 1 - rowMod;
731 arm = armQ + 1 + logArm;
732 if (arm >= SPAN_ROW_SIZE(map, ld, span))
733 arm -= SPAN_ROW_SIZE(map, ld, span);
734 physArm = (u8)arm;
735 } else
736
737 physArm = get_arm(instance, ld, span, stripRow, map);
738 if (physArm == 0xFF)
739 return false;
740
741 arRef = MR_LdSpanArrayGet(ld, span, map);
742 pd = MR_ArPdGet(arRef, physArm, map);
743
744 if (pd != MR_PD_INVALID) {
745 *pDevHandle = MR_PdDevHandleGet(pd, map);
746 *pPdInterface = MR_PdInterfaceTypeGet(pd, map);
747
748 if ((instance->adapter_type == VENTURA_SERIES) &&
749 (raid->level == 1) &&
750 !io_info->isRead) {
751 r1_alt_pd = MR_ArPdGet(arRef, physArm + 1, map);
752 if (r1_alt_pd != MR_PD_INVALID)
753 io_info->r1_alt_dev_handle =
754 MR_PdDevHandleGet(r1_alt_pd, map);
755 }
756 } else {
757 if ((raid->level >= 5) &&
758 ((instance->adapter_type == THUNDERBOLT_SERIES) ||
759 ((instance->adapter_type == INVADER_SERIES) &&
760 (raid->regTypeReqOnRead != REGION_TYPE_UNUSED))))
761 pRAID_Context->reg_lock_flags = REGION_TYPE_EXCLUSIVE;
762 else if (raid->level == 1) {
763 physArm = physArm + 1;
764 pd = MR_ArPdGet(arRef, physArm, map);
765 if (pd != MR_PD_INVALID) {
766 *pDevHandle = MR_PdDevHandleGet(pd, map);
767 *pPdInterface = MR_PdInterfaceTypeGet(pd, map);
768 }
769 }
770 }
771
772 *pdBlock += stripRef + le64_to_cpu(MR_LdSpanPtrGet(ld, span, map)->startBlk);
773 if (instance->adapter_type == VENTURA_SERIES) {
774 ((struct RAID_CONTEXT_G35 *)pRAID_Context)->span_arm =
775 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
776 io_info->span_arm =
777 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
778 } else {
779 pRAID_Context->span_arm =
780 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
781 io_info->span_arm = pRAID_Context->span_arm;
782 }
783 io_info->pd_after_lb = pd;
784 return retval;
785}
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804u8 MR_GetPhyParams(struct megasas_instance *instance, u32 ld, u64 stripRow,
805 u16 stripRef, struct IO_REQUEST_INFO *io_info,
806 struct RAID_CONTEXT *pRAID_Context,
807 struct MR_DRV_RAID_MAP_ALL *map)
808{
809 struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
810 u32 pd, arRef, r1_alt_pd;
811 u8 physArm, span;
812 u64 row;
813 u8 retval = true;
814 u64 *pdBlock = &io_info->pdBlock;
815 __le16 *pDevHandle = &io_info->devHandle;
816 u8 *pPdInterface = &io_info->pd_interface;
817 struct fusion_context *fusion;
818
819 fusion = instance->ctrl_context;
820 *pDevHandle = cpu_to_le16(MR_DEVHANDLE_INVALID);
821
822 row = mega_div64_32(stripRow, raid->rowDataSize);
823
824 if (raid->level == 6) {
825
826 u32 logArm = mega_mod64(stripRow, raid->rowDataSize);
827 u32 rowMod, armQ, arm;
828
829 if (raid->rowSize == 0)
830 return false;
831
832 rowMod = mega_mod64(row, raid->rowSize);
833 armQ = raid->rowSize-1-rowMod;
834 arm = armQ+1+logArm;
835 if (arm >= raid->rowSize)
836 arm -= raid->rowSize;
837 physArm = (u8)arm;
838 } else {
839 if (raid->modFactor == 0)
840 return false;
841 physArm = MR_LdDataArmGet(ld, mega_mod64(stripRow,
842 raid->modFactor),
843 map);
844 }
845
846 if (raid->spanDepth == 1) {
847 span = 0;
848 *pdBlock = row << raid->stripeShift;
849 } else {
850 span = (u8)MR_GetSpanBlock(ld, row, pdBlock, map);
851 if (span == SPAN_INVALID)
852 return false;
853 }
854
855
856 arRef = MR_LdSpanArrayGet(ld, span, map);
857 pd = MR_ArPdGet(arRef, physArm, map);
858
859 if (pd != MR_PD_INVALID) {
860
861 *pDevHandle = MR_PdDevHandleGet(pd, map);
862 *pPdInterface = MR_PdInterfaceTypeGet(pd, map);
863
864 if ((instance->adapter_type == VENTURA_SERIES) &&
865 (raid->level == 1) &&
866 !io_info->isRead) {
867 r1_alt_pd = MR_ArPdGet(arRef, physArm + 1, map);
868 if (r1_alt_pd != MR_PD_INVALID)
869 io_info->r1_alt_dev_handle =
870 MR_PdDevHandleGet(r1_alt_pd, map);
871 }
872 } else {
873 if ((raid->level >= 5) &&
874 ((instance->adapter_type == THUNDERBOLT_SERIES) ||
875 ((instance->adapter_type == INVADER_SERIES) &&
876 (raid->regTypeReqOnRead != REGION_TYPE_UNUSED))))
877 pRAID_Context->reg_lock_flags = REGION_TYPE_EXCLUSIVE;
878 else if (raid->level == 1) {
879
880 physArm = physArm + 1;
881 pd = MR_ArPdGet(arRef, physArm, map);
882 if (pd != MR_PD_INVALID) {
883
884 *pDevHandle = MR_PdDevHandleGet(pd, map);
885 *pPdInterface = MR_PdInterfaceTypeGet(pd, map);
886 }
887 }
888 }
889
890 *pdBlock += stripRef + le64_to_cpu(MR_LdSpanPtrGet(ld, span, map)->startBlk);
891 if (instance->adapter_type == VENTURA_SERIES) {
892 ((struct RAID_CONTEXT_G35 *)pRAID_Context)->span_arm =
893 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
894 io_info->span_arm =
895 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
896 } else {
897 pRAID_Context->span_arm =
898 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm;
899 io_info->span_arm = pRAID_Context->span_arm;
900 }
901 io_info->pd_after_lb = pd;
902 return retval;
903}
904
905
906
907
908
909
910
911
912
913
914u8
915MR_BuildRaidContext(struct megasas_instance *instance,
916 struct IO_REQUEST_INFO *io_info,
917 struct RAID_CONTEXT *pRAID_Context,
918 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN)
919{
920 struct fusion_context *fusion;
921 struct MR_LD_RAID *raid;
922 u32 stripSize, stripe_mask;
923 u64 endLba, endStrip, endRow, start_row, start_strip;
924 u64 regStart;
925 u32 regSize;
926 u8 num_strips, numRows;
927 u16 ref_in_start_stripe, ref_in_end_stripe;
928 u64 ldStartBlock;
929 u32 numBlocks, ldTgtId;
930 u8 isRead;
931 u8 retval = 0;
932 u8 startlba_span = SPAN_INVALID;
933 u64 *pdBlock = &io_info->pdBlock;
934 u16 ld;
935
936 ldStartBlock = io_info->ldStartBlock;
937 numBlocks = io_info->numBlocks;
938 ldTgtId = io_info->ldTgtId;
939 isRead = io_info->isRead;
940 io_info->IoforUnevenSpan = 0;
941 io_info->start_span = SPAN_INVALID;
942 fusion = instance->ctrl_context;
943
944 ld = MR_TargetIdToLdGet(ldTgtId, map);
945 raid = MR_LdRaidGet(ld, map);
946
947 io_info->ra_capable = raid->capability.ra_capable;
948
949
950
951
952
953 if (raid->rowDataSize == 0) {
954 if (MR_LdSpanPtrGet(ld, 0, map)->spanRowDataSize == 0)
955 return false;
956 else if (instance->UnevenSpanSupport) {
957 io_info->IoforUnevenSpan = 1;
958 } else {
959 dev_info(&instance->pdev->dev,
960 "raid->rowDataSize is 0, but has SPAN[0]"
961 "rowDataSize = 0x%0x,"
962 "but there is _NO_ UnevenSpanSupport\n",
963 MR_LdSpanPtrGet(ld, 0, map)->spanRowDataSize);
964 return false;
965 }
966 }
967
968 stripSize = 1 << raid->stripeShift;
969 stripe_mask = stripSize-1;
970
971
972
973
974
975 start_strip = ldStartBlock >> raid->stripeShift;
976 ref_in_start_stripe = (u16)(ldStartBlock & stripe_mask);
977 endLba = ldStartBlock + numBlocks - 1;
978 ref_in_end_stripe = (u16)(endLba & stripe_mask);
979 endStrip = endLba >> raid->stripeShift;
980 num_strips = (u8)(endStrip - start_strip + 1);
981
982 if (io_info->IoforUnevenSpan) {
983 start_row = get_row_from_strip(instance, ld, start_strip, map);
984 endRow = get_row_from_strip(instance, ld, endStrip, map);
985 if (start_row == -1ULL || endRow == -1ULL) {
986 dev_info(&instance->pdev->dev, "return from %s %d."
987 "Send IO w/o region lock.\n",
988 __func__, __LINE__);
989 return false;
990 }
991
992 if (raid->spanDepth == 1) {
993 startlba_span = 0;
994 *pdBlock = start_row << raid->stripeShift;
995 } else
996 startlba_span = (u8)mr_spanset_get_span_block(instance,
997 ld, start_row, pdBlock, map);
998 if (startlba_span == SPAN_INVALID) {
999 dev_info(&instance->pdev->dev, "return from %s %d"
1000 "for row 0x%llx,start strip %llx"
1001 "endSrip %llx\n", __func__, __LINE__,
1002 (unsigned long long)start_row,
1003 (unsigned long long)start_strip,
1004 (unsigned long long)endStrip);
1005 return false;
1006 }
1007 io_info->start_span = startlba_span;
1008 io_info->start_row = start_row;
1009 } else {
1010 start_row = mega_div64_32(start_strip, raid->rowDataSize);
1011 endRow = mega_div64_32(endStrip, raid->rowDataSize);
1012 }
1013 numRows = (u8)(endRow - start_row + 1);
1014
1015
1016
1017
1018
1019
1020 regStart = start_row << raid->stripeShift;
1021
1022 regSize = stripSize;
1023
1024 io_info->do_fp_rlbypass = raid->capability.fpBypassRegionLock;
1025
1026
1027 if (raid->capability.fpCapable) {
1028 if (isRead)
1029 io_info->fpOkForIo = (raid->capability.fpReadCapable &&
1030 ((num_strips == 1) ||
1031 raid->capability.
1032 fpReadAcrossStripe));
1033 else
1034 io_info->fpOkForIo = (raid->capability.fpWriteCapable &&
1035 ((num_strips == 1) ||
1036 raid->capability.
1037 fpWriteAcrossStripe));
1038 } else
1039 io_info->fpOkForIo = false;
1040
1041 if (numRows == 1) {
1042
1043 if (num_strips == 1) {
1044 regStart += ref_in_start_stripe;
1045 regSize = numBlocks;
1046 }
1047
1048 } else if (io_info->IoforUnevenSpan == 0) {
1049
1050
1051
1052
1053 if (start_strip == (start_row + 1) * raid->rowDataSize - 1) {
1054 regStart += ref_in_start_stripe;
1055
1056
1057 regSize = stripSize - ref_in_start_stripe;
1058 }
1059
1060
1061 if (numRows > 2)
1062 regSize += (numRows-2) << raid->stripeShift;
1063
1064
1065 if (endStrip == endRow*raid->rowDataSize)
1066 regSize += ref_in_end_stripe+1;
1067 else
1068 regSize += stripSize;
1069 } else {
1070
1071
1072
1073
1074 if (start_strip == (get_strip_from_row(instance, ld, start_row, map) +
1075 SPAN_ROW_DATA_SIZE(map, ld, startlba_span) - 1)) {
1076 regStart += ref_in_start_stripe;
1077
1078
1079
1080 regSize = stripSize - ref_in_start_stripe;
1081 }
1082
1083
1084 if (numRows > 2)
1085
1086 regSize += (numRows-2) << raid->stripeShift;
1087
1088
1089 if (endStrip == get_strip_from_row(instance, ld, endRow, map))
1090 regSize += ref_in_end_stripe + 1;
1091 else
1092 regSize += stripSize;
1093 }
1094
1095 pRAID_Context->timeout_value =
1096 cpu_to_le16(raid->fpIoTimeoutForLd ?
1097 raid->fpIoTimeoutForLd :
1098 map->raidMap.fpPdIoTimeoutSec);
1099 if (instance->adapter_type == INVADER_SERIES)
1100 pRAID_Context->reg_lock_flags = (isRead) ?
1101 raid->regTypeReqOnRead : raid->regTypeReqOnWrite;
1102 else if (instance->adapter_type == THUNDERBOLT_SERIES)
1103 pRAID_Context->reg_lock_flags = (isRead) ?
1104 REGION_TYPE_SHARED_READ : raid->regTypeReqOnWrite;
1105 pRAID_Context->virtual_disk_tgt_id = raid->targetId;
1106 pRAID_Context->reg_lock_row_lba = cpu_to_le64(regStart);
1107 pRAID_Context->reg_lock_length = cpu_to_le32(regSize);
1108 pRAID_Context->config_seq_num = raid->seqNum;
1109
1110 *raidLUN = raid->LUN;
1111
1112
1113
1114
1115 if (io_info->fpOkForIo) {
1116 retval = io_info->IoforUnevenSpan ?
1117 mr_spanset_get_phy_params(instance, ld,
1118 start_strip, ref_in_start_stripe,
1119 io_info, pRAID_Context, map) :
1120 MR_GetPhyParams(instance, ld, start_strip,
1121 ref_in_start_stripe, io_info,
1122 pRAID_Context, map);
1123
1124 if (io_info->devHandle == MR_DEVHANDLE_INVALID)
1125 io_info->fpOkForIo = false;
1126 return retval;
1127 } else if (isRead) {
1128 uint stripIdx;
1129 for (stripIdx = 0; stripIdx < num_strips; stripIdx++) {
1130 retval = io_info->IoforUnevenSpan ?
1131 mr_spanset_get_phy_params(instance, ld,
1132 start_strip + stripIdx,
1133 ref_in_start_stripe, io_info,
1134 pRAID_Context, map) :
1135 MR_GetPhyParams(instance, ld,
1136 start_strip + stripIdx, ref_in_start_stripe,
1137 io_info, pRAID_Context, map);
1138 if (!retval)
1139 return true;
1140 }
1141 }
1142 return true;
1143}
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156void mr_update_span_set(struct MR_DRV_RAID_MAP_ALL *map,
1157 PLD_SPAN_INFO ldSpanInfo)
1158{
1159 u8 span, count;
1160 u32 element, span_row_width;
1161 u64 span_row;
1162 struct MR_LD_RAID *raid;
1163 LD_SPAN_SET *span_set, *span_set_prev;
1164 struct MR_QUAD_ELEMENT *quad;
1165 int ldCount;
1166 u16 ld;
1167
1168
1169 for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) {
1170 ld = MR_TargetIdToLdGet(ldCount, map);
1171 if (ld >= (MAX_LOGICAL_DRIVES_EXT - 1))
1172 continue;
1173 raid = MR_LdRaidGet(ld, map);
1174 for (element = 0; element < MAX_QUAD_DEPTH; element++) {
1175 for (span = 0; span < raid->spanDepth; span++) {
1176 if (le32_to_cpu(map->raidMap.ldSpanMap[ld].spanBlock[span].
1177 block_span_info.noElements) <
1178 element + 1)
1179 continue;
1180 span_set = &(ldSpanInfo[ld].span_set[element]);
1181 quad = &map->raidMap.ldSpanMap[ld].
1182 spanBlock[span].block_span_info.
1183 quad[element];
1184
1185 span_set->diff = le32_to_cpu(quad->diff);
1186
1187 for (count = 0, span_row_width = 0;
1188 count < raid->spanDepth; count++) {
1189 if (le32_to_cpu(map->raidMap.ldSpanMap[ld].
1190 spanBlock[count].
1191 block_span_info.
1192 noElements) >= element + 1) {
1193 span_set->strip_offset[count] =
1194 span_row_width;
1195 span_row_width +=
1196 MR_LdSpanPtrGet
1197 (ld, count, map)->spanRowDataSize;
1198 }
1199 }
1200
1201 span_set->span_row_data_width = span_row_width;
1202 span_row = mega_div64_32(((le64_to_cpu(quad->logEnd) -
1203 le64_to_cpu(quad->logStart)) + le32_to_cpu(quad->diff)),
1204 le32_to_cpu(quad->diff));
1205
1206 if (element == 0) {
1207 span_set->log_start_lba = 0;
1208 span_set->log_end_lba =
1209 ((span_row << raid->stripeShift)
1210 * span_row_width) - 1;
1211
1212 span_set->span_row_start = 0;
1213 span_set->span_row_end = span_row - 1;
1214
1215 span_set->data_strip_start = 0;
1216 span_set->data_strip_end =
1217 (span_row * span_row_width) - 1;
1218
1219 span_set->data_row_start = 0;
1220 span_set->data_row_end =
1221 (span_row * le32_to_cpu(quad->diff)) - 1;
1222 } else {
1223 span_set_prev = &(ldSpanInfo[ld].
1224 span_set[element - 1]);
1225 span_set->log_start_lba =
1226 span_set_prev->log_end_lba + 1;
1227 span_set->log_end_lba =
1228 span_set->log_start_lba +
1229 ((span_row << raid->stripeShift)
1230 * span_row_width) - 1;
1231
1232 span_set->span_row_start =
1233 span_set_prev->span_row_end + 1;
1234 span_set->span_row_end =
1235 span_set->span_row_start + span_row - 1;
1236
1237 span_set->data_strip_start =
1238 span_set_prev->data_strip_end + 1;
1239 span_set->data_strip_end =
1240 span_set->data_strip_start +
1241 (span_row * span_row_width) - 1;
1242
1243 span_set->data_row_start =
1244 span_set_prev->data_row_end + 1;
1245 span_set->data_row_end =
1246 span_set->data_row_start +
1247 (span_row * le32_to_cpu(quad->diff)) - 1;
1248 }
1249 break;
1250 }
1251 if (span == raid->spanDepth)
1252 break;
1253 }
1254 }
1255}
1256
1257void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *drv_map,
1258 struct LD_LOAD_BALANCE_INFO *lbInfo)
1259{
1260 int ldCount;
1261 u16 ld;
1262 struct MR_LD_RAID *raid;
1263
1264 if (lb_pending_cmds > 128 || lb_pending_cmds < 1)
1265 lb_pending_cmds = LB_PENDING_CMDS_DEFAULT;
1266
1267 for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) {
1268 ld = MR_TargetIdToLdGet(ldCount, drv_map);
1269 if (ld >= MAX_LOGICAL_DRIVES_EXT) {
1270 lbInfo[ldCount].loadBalanceFlag = 0;
1271 continue;
1272 }
1273
1274 raid = MR_LdRaidGet(ld, drv_map);
1275 if ((raid->level != 1) ||
1276 (raid->ldState != MR_LD_STATE_OPTIMAL)) {
1277 lbInfo[ldCount].loadBalanceFlag = 0;
1278 continue;
1279 }
1280 lbInfo[ldCount].loadBalanceFlag = 1;
1281 }
1282}
1283
1284u8 megasas_get_best_arm_pd(struct megasas_instance *instance,
1285 struct LD_LOAD_BALANCE_INFO *lbInfo,
1286 struct IO_REQUEST_INFO *io_info,
1287 struct MR_DRV_RAID_MAP_ALL *drv_map)
1288{
1289 struct MR_LD_RAID *raid;
1290 u16 pd1_dev_handle;
1291 u16 pend0, pend1, ld;
1292 u64 diff0, diff1;
1293 u8 bestArm, pd0, pd1, span, arm;
1294 u32 arRef, span_row_size;
1295
1296 u64 block = io_info->ldStartBlock;
1297 u32 count = io_info->numBlocks;
1298
1299 span = ((io_info->span_arm & RAID_CTX_SPANARM_SPAN_MASK)
1300 >> RAID_CTX_SPANARM_SPAN_SHIFT);
1301 arm = (io_info->span_arm & RAID_CTX_SPANARM_ARM_MASK);
1302
1303 ld = MR_TargetIdToLdGet(io_info->ldTgtId, drv_map);
1304 raid = MR_LdRaidGet(ld, drv_map);
1305 span_row_size = instance->UnevenSpanSupport ?
1306 SPAN_ROW_SIZE(drv_map, ld, span) : raid->rowSize;
1307
1308 arRef = MR_LdSpanArrayGet(ld, span, drv_map);
1309 pd0 = MR_ArPdGet(arRef, arm, drv_map);
1310 pd1 = MR_ArPdGet(arRef, (arm + 1) >= span_row_size ?
1311 (arm + 1 - span_row_size) : arm + 1, drv_map);
1312
1313
1314
1315 pd1_dev_handle = MR_PdDevHandleGet(pd1, drv_map);
1316
1317 if (pd1_dev_handle == MR_DEVHANDLE_INVALID) {
1318 bestArm = arm;
1319 } else {
1320
1321 pend0 = atomic_read(&lbInfo->scsi_pending_cmds[pd0]);
1322 pend1 = atomic_read(&lbInfo->scsi_pending_cmds[pd1]);
1323
1324
1325 diff0 = ABS_DIFF(block, lbInfo->last_accessed_block[pd0]);
1326 diff1 = ABS_DIFF(block, lbInfo->last_accessed_block[pd1]);
1327 bestArm = (diff0 <= diff1 ? arm : arm ^ 1);
1328
1329
1330
1331
1332 if ((bestArm == arm && pend0 > pend1 + lb_pending_cmds) ||
1333 (bestArm != arm && pend1 > pend0 + lb_pending_cmds))
1334 bestArm ^= 1;
1335
1336
1337 io_info->span_arm =
1338 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | bestArm;
1339 io_info->pd_after_lb = (bestArm == arm) ? pd0 : pd1;
1340 }
1341
1342 lbInfo->last_accessed_block[io_info->pd_after_lb] = block + count - 1;
1343 return io_info->pd_after_lb;
1344}
1345
1346__le16 get_updated_dev_handle(struct megasas_instance *instance,
1347 struct LD_LOAD_BALANCE_INFO *lbInfo,
1348 struct IO_REQUEST_INFO *io_info,
1349 struct MR_DRV_RAID_MAP_ALL *drv_map)
1350{
1351 u8 arm_pd;
1352 __le16 devHandle;
1353
1354
1355 arm_pd = megasas_get_best_arm_pd(instance, lbInfo, io_info, drv_map);
1356 devHandle = MR_PdDevHandleGet(arm_pd, drv_map);
1357 io_info->pd_interface = MR_PdInterfaceTypeGet(arm_pd, drv_map);
1358 atomic_inc(&lbInfo->scsi_pending_cmds[arm_pd]);
1359
1360 return devHandle;
1361}
1362
