LXR linux/drivers/spi/spi-dw.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef DW_SPI_HEADER_H
   3#define DW_SPI_HEADER_H
   4
   5#include <linux/io.h>
   6#include <linux/scatterlist.h>
   7#include <linux/gpio.h>
   8
   9/* Register offsets */
  10#define DW_SPI_CTRL0                    0x00
  11#define DW_SPI_CTRL1                    0x04
  12#define DW_SPI_SSIENR                   0x08
  13#define DW_SPI_MWCR                     0x0c
  14#define DW_SPI_SER                      0x10
  15#define DW_SPI_BAUDR                    0x14
  16#define DW_SPI_TXFLTR                   0x18
  17#define DW_SPI_RXFLTR                   0x1c
  18#define DW_SPI_TXFLR                    0x20
  19#define DW_SPI_RXFLR                    0x24
  20#define DW_SPI_SR                       0x28
  21#define DW_SPI_IMR                      0x2c
  22#define DW_SPI_ISR                      0x30
  23#define DW_SPI_RISR                     0x34
  24#define DW_SPI_TXOICR                   0x38
  25#define DW_SPI_RXOICR                   0x3c
  26#define DW_SPI_RXUICR                   0x40
  27#define DW_SPI_MSTICR                   0x44
  28#define DW_SPI_ICR                      0x48
  29#define DW_SPI_DMACR                    0x4c
  30#define DW_SPI_DMATDLR                  0x50
  31#define DW_SPI_DMARDLR                  0x54
  32#define DW_SPI_IDR                      0x58
  33#define DW_SPI_VERSION                  0x5c
  34#define DW_SPI_DR                       0x60
  35#define DW_SPI_CS_OVERRIDE              0xf4
  36
  37/* Bit fields in CTRLR0 */
  38#define SPI_DFS_OFFSET                  0
  39
  40#define SPI_FRF_OFFSET                  4
  41#define SPI_FRF_SPI                     0x0
  42#define SPI_FRF_SSP                     0x1
  43#define SPI_FRF_MICROWIRE               0x2
  44#define SPI_FRF_RESV                    0x3
  45
  46#define SPI_MODE_OFFSET                 6
  47#define SPI_SCPH_OFFSET                 6
  48#define SPI_SCOL_OFFSET                 7
  49
  50#define SPI_TMOD_OFFSET                 8
  51#define SPI_TMOD_MASK                   (0x3 << SPI_TMOD_OFFSET)
  52#define SPI_TMOD_TR                     0x0             /* xmit & recv */
  53#define SPI_TMOD_TO                     0x1             /* xmit only */
  54#define SPI_TMOD_RO                     0x2             /* recv only */
  55#define SPI_TMOD_EPROMREAD              0x3             /* eeprom read mode */
  56
  57#define SPI_SLVOE_OFFSET                10
  58#define SPI_SRL_OFFSET                  11
  59#define SPI_CFS_OFFSET                  12
  60
  61/* Bit fields in SR, 7 bits */
  62#define SR_MASK                         0x7f            /* cover 7 bits */
  63#define SR_BUSY                         (1 << 0)
  64#define SR_TF_NOT_FULL                  (1 << 1)
  65#define SR_TF_EMPT                      (1 << 2)
  66#define SR_RF_NOT_EMPT                  (1 << 3)
  67#define SR_RF_FULL                      (1 << 4)
  68#define SR_TX_ERR                       (1 << 5)
  69#define SR_DCOL                         (1 << 6)
  70
  71/* Bit fields in ISR, IMR, RISR, 7 bits */
  72#define SPI_INT_TXEI                    (1 << 0)
  73#define SPI_INT_TXOI                    (1 << 1)
  74#define SPI_INT_RXUI                    (1 << 2)
  75#define SPI_INT_RXOI                    (1 << 3)
  76#define SPI_INT_RXFI                    (1 << 4)
  77#define SPI_INT_MSTI                    (1 << 5)
  78
  79/* Bit fields in DMACR */
  80#define SPI_DMA_RDMAE                   (1 << 0)
  81#define SPI_DMA_TDMAE                   (1 << 1)
  82
  83/* TX RX interrupt level threshold, max can be 256 */
  84#define SPI_INT_THRESHOLD               32
  85
  86enum dw_ssi_type {
  87        SSI_MOTO_SPI = 0,
  88        SSI_TI_SSP,
  89        SSI_NS_MICROWIRE,
  90};
  91
  92struct dw_spi;
  93struct dw_spi_dma_ops {
  94        int (*dma_init)(struct dw_spi *dws);
  95        void (*dma_exit)(struct dw_spi *dws);
  96        int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
  97        bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
  98                        struct spi_transfer *xfer);
  99        int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
 100        void (*dma_stop)(struct dw_spi *dws);
 101};
 102
 103struct dw_spi {
 104        struct spi_controller   *master;
 105        enum dw_ssi_type        type;
 106
 107        void __iomem            *regs;
 108        unsigned long           paddr;
 109        int                     irq;
 110        u32                     fifo_len;       /* depth of the FIFO buffer */
 111        u32                     max_freq;       /* max bus freq supported */
 112
 113        int                     cs_override;
 114        u32                     reg_io_width;   /* DR I/O width in bytes */
 115        u16                     bus_num;
 116        u16                     num_cs;         /* supported slave numbers */
 117        void (*set_cs)(struct spi_device *spi, bool enable);
 118
 119        /* Current message transfer state info */
 120        size_t                  len;
 121        void                    *tx;
 122        void                    *tx_end;
 123        void                    *rx;
 124        void                    *rx_end;
 125        int                     dma_mapped;
 126        u8                      n_bytes;        /* current is a 1/2 bytes op */
 127        u32                     dma_width;
 128        irqreturn_t             (*transfer_handler)(struct dw_spi *dws);
 129        u32                     current_freq;   /* frequency in hz */
 130
 131        /* DMA info */
 132        int                     dma_inited;
 133        struct dma_chan         *txchan;
 134        struct dma_chan         *rxchan;
 135        unsigned long           dma_chan_busy;
 136        dma_addr_t              dma_addr; /* phy address of the Data register */
 137        const struct dw_spi_dma_ops *dma_ops;
 138        void                    *dma_tx;
 139        void                    *dma_rx;
 140
 141        /* Bus interface info */
 142        void                    *priv;
 143#ifdef CONFIG_DEBUG_FS
 144        struct dentry *debugfs;
 145#endif
 146};
 147
 148static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
 149{
 150        return __raw_readl(dws->regs + offset);
 151}
 152
 153static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
 154{
 155        return __raw_readw(dws->regs + offset);
 156}
 157
 158static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
 159{
 160        __raw_writel(val, dws->regs + offset);
 161}
 162
 163static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
 164{
 165        __raw_writew(val, dws->regs + offset);
 166}
 167
 168static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
 169{
 170        switch (dws->reg_io_width) {
 171        case 2:
 172                return dw_readw(dws, offset);
 173        case 4:
 174        default:
 175                return dw_readl(dws, offset);
 176        }
 177}
 178
 179static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
 180{
 181        switch (dws->reg_io_width) {
 182        case 2:
 183                dw_writew(dws, offset, val);
 184                break;
 185        case 4:
 186        default:
 187                dw_writel(dws, offset, val);
 188                break;
 189        }
 190}
 191
 192static inline void spi_enable_chip(struct dw_spi *dws, int enable)
 193{
 194        dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
 195}
 196
 197static inline void spi_set_clk(struct dw_spi *dws, u16 div)
 198{
 199        dw_writel(dws, DW_SPI_BAUDR, div);
 200}
 201
 202/* Disable IRQ bits */
 203static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
 204{
 205        u32 new_mask;
 206
 207        new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
 208        dw_writel(dws, DW_SPI_IMR, new_mask);
 209}
 210
 211/* Enable IRQ bits */
 212static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
 213{
 214        u32 new_mask;
 215
 216        new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
 217        dw_writel(dws, DW_SPI_IMR, new_mask);
 218}
 219
 220/*
 221 * This does disable the SPI controller, interrupts, and re-enable the
 222 * controller back. Transmit and receive FIFO buffers are cleared when the
 223 * device is disabled.
 224 */
 225static inline void spi_reset_chip(struct dw_spi *dws)
 226{
 227        spi_enable_chip(dws, 0);
 228        spi_mask_intr(dws, 0xff);
 229        spi_enable_chip(dws, 1);
 230}
 231
 232static inline void spi_shutdown_chip(struct dw_spi *dws)
 233{
 234        spi_enable_chip(dws, 0);
 235        spi_set_clk(dws, 0);
 236}
 237
 238/*
 239 * Each SPI slave device to work with dw_api controller should
 240 * has such a structure claiming its working mode (poll or PIO/DMA),
 241 * which can be save in the "controller_data" member of the
 242 * struct spi_device.
 243 */
 244struct dw_spi_chip {
 245        u8 poll_mode;   /* 1 for controller polling mode */
 246        u8 type;        /* SPI/SSP/MicroWire */
 247        void (*cs_control)(u32 command);
 248};
 249
 250extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
 251extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
 252extern void dw_spi_remove_host(struct dw_spi *dws);
 253extern int dw_spi_suspend_host(struct dw_spi *dws);
 254extern int dw_spi_resume_host(struct dw_spi *dws);
 255
 256/* platform related setup */
 257extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
 258#endif /* DW_SPI_HEADER_H */
 259