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42#include <linux/kernel.h>
43#include <linux/module.h>
44#include <linux/spinlock.h>
45#include <linux/interrupt.h>
46#include <linux/platform_device.h>
47#include <linux/dma-mapping.h>
48#include <linux/delay.h>
49#include <linux/io.h>
50#include <linux/slab.h>
51#include <linux/usb.h>
52
53#include <linux/usb/hcd.h>
54#include <linux/usb/ch11.h>
55
56#include "core.h"
57#include "hcd.h"
58
59static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
60
61
62
63
64
65
66
67
68
69
70
71
72
73static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
74{
75 u32 intmsk;
76
77
78 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
79
80
81 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
82
83
84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
85
86 if (!hsotg->params.host_dma)
87 intmsk |= GINTSTS_RXFLVL;
88 if (!hsotg->params.external_id_pin_ctl)
89 intmsk |= GINTSTS_CONIDSTSCHNG;
90
91 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
92 GINTSTS_SESSREQINT;
93
94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
95 intmsk |= GINTSTS_LPMTRANRCVD;
96
97 dwc2_writel(hsotg, intmsk, GINTMSK);
98}
99
100
101
102
103
104static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
105{
106 u32 hcfg, val;
107
108 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
109 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
110 hsotg->params.ulpi_fs_ls) ||
111 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
112
113 val = HCFG_FSLSPCLKSEL_48_MHZ;
114 } else {
115
116 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
117 }
118
119 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
120 hcfg = dwc2_readl(hsotg, HCFG);
121 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
122 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
123 dwc2_writel(hsotg, hcfg, HCFG);
124}
125
126static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
127{
128 u32 usbcfg, ggpio, i2cctl;
129 int retval = 0;
130
131
132
133
134
135 if (select_phy) {
136 dev_dbg(hsotg->dev, "FS PHY selected\n");
137
138 usbcfg = dwc2_readl(hsotg, GUSBCFG);
139 if (!(usbcfg & GUSBCFG_PHYSEL)) {
140 usbcfg |= GUSBCFG_PHYSEL;
141 dwc2_writel(hsotg, usbcfg, GUSBCFG);
142
143
144 retval = dwc2_core_reset(hsotg, false);
145
146 if (retval) {
147 dev_err(hsotg->dev,
148 "%s: Reset failed, aborting", __func__);
149 return retval;
150 }
151 }
152
153 if (hsotg->params.activate_stm_fs_transceiver) {
154 ggpio = dwc2_readl(hsotg, GGPIO);
155 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
156 dev_dbg(hsotg->dev, "Activating transceiver\n");
157
158
159
160
161 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
162 dwc2_writel(hsotg, ggpio, GGPIO);
163 }
164 }
165 }
166
167
168
169
170
171
172 if (dwc2_is_host_mode(hsotg))
173 dwc2_init_fs_ls_pclk_sel(hsotg);
174
175 if (hsotg->params.i2c_enable) {
176 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
177
178
179 usbcfg = dwc2_readl(hsotg, GUSBCFG);
180 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
181 dwc2_writel(hsotg, usbcfg, GUSBCFG);
182
183
184 i2cctl = dwc2_readl(hsotg, GI2CCTL);
185 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
186 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
187 i2cctl &= ~GI2CCTL_I2CEN;
188 dwc2_writel(hsotg, i2cctl, GI2CCTL);
189 i2cctl |= GI2CCTL_I2CEN;
190 dwc2_writel(hsotg, i2cctl, GI2CCTL);
191 }
192
193 return retval;
194}
195
196static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
197{
198 u32 usbcfg, usbcfg_old;
199 int retval = 0;
200
201 if (!select_phy)
202 return 0;
203
204 usbcfg = dwc2_readl(hsotg, GUSBCFG);
205 usbcfg_old = usbcfg;
206
207
208
209
210
211
212 switch (hsotg->params.phy_type) {
213 case DWC2_PHY_TYPE_PARAM_ULPI:
214
215 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
216 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
217 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
218 if (hsotg->params.phy_ulpi_ddr)
219 usbcfg |= GUSBCFG_DDRSEL;
220
221
222 if (hsotg->params.oc_disable)
223 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
224 GUSBCFG_INDICATORPASSTHROUGH);
225 break;
226 case DWC2_PHY_TYPE_PARAM_UTMI:
227
228 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
229 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
230 if (hsotg->params.phy_utmi_width == 16)
231 usbcfg |= GUSBCFG_PHYIF16;
232 break;
233 default:
234 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
235 break;
236 }
237
238 if (usbcfg != usbcfg_old) {
239 dwc2_writel(hsotg, usbcfg, GUSBCFG);
240
241
242 retval = dwc2_core_reset(hsotg, false);
243 if (retval) {
244 dev_err(hsotg->dev,
245 "%s: Reset failed, aborting", __func__);
246 return retval;
247 }
248 }
249
250 return retval;
251}
252
253static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
254{
255 u32 usbcfg;
256 int retval = 0;
257
258 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
259 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
260 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
261
262 retval = dwc2_fs_phy_init(hsotg, select_phy);
263 if (retval)
264 return retval;
265 } else {
266
267 retval = dwc2_hs_phy_init(hsotg, select_phy);
268 if (retval)
269 return retval;
270 }
271
272 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
273 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
274 hsotg->params.ulpi_fs_ls) {
275 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
276 usbcfg = dwc2_readl(hsotg, GUSBCFG);
277 usbcfg |= GUSBCFG_ULPI_FS_LS;
278 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
279 dwc2_writel(hsotg, usbcfg, GUSBCFG);
280 } else {
281 usbcfg = dwc2_readl(hsotg, GUSBCFG);
282 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
283 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
284 dwc2_writel(hsotg, usbcfg, GUSBCFG);
285 }
286
287 return retval;
288}
289
290static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
291{
292 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
293
294 switch (hsotg->hw_params.arch) {
295 case GHWCFG2_EXT_DMA_ARCH:
296 dev_err(hsotg->dev, "External DMA Mode not supported\n");
297 return -EINVAL;
298
299 case GHWCFG2_INT_DMA_ARCH:
300 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
301 if (hsotg->params.ahbcfg != -1) {
302 ahbcfg &= GAHBCFG_CTRL_MASK;
303 ahbcfg |= hsotg->params.ahbcfg &
304 ~GAHBCFG_CTRL_MASK;
305 }
306 break;
307
308 case GHWCFG2_SLAVE_ONLY_ARCH:
309 default:
310 dev_dbg(hsotg->dev, "Slave Only Mode\n");
311 break;
312 }
313
314 if (hsotg->params.host_dma)
315 ahbcfg |= GAHBCFG_DMA_EN;
316 else
317 hsotg->params.dma_desc_enable = false;
318
319 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
320
321 return 0;
322}
323
324static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
325{
326 u32 usbcfg;
327
328 usbcfg = dwc2_readl(hsotg, GUSBCFG);
329 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
330
331 switch (hsotg->hw_params.op_mode) {
332 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
333 if (hsotg->params.otg_cap ==
334 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
335 usbcfg |= GUSBCFG_HNPCAP;
336 if (hsotg->params.otg_cap !=
337 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
338 usbcfg |= GUSBCFG_SRPCAP;
339 break;
340
341 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
342 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
343 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
344 if (hsotg->params.otg_cap !=
345 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
346 usbcfg |= GUSBCFG_SRPCAP;
347 break;
348
349 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
350 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
351 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
352 default:
353 break;
354 }
355
356 dwc2_writel(hsotg, usbcfg, GUSBCFG);
357}
358
359static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
360{
361 if (hsotg->vbus_supply)
362 return regulator_enable(hsotg->vbus_supply);
363
364 return 0;
365}
366
367static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
368{
369 if (hsotg->vbus_supply)
370 return regulator_disable(hsotg->vbus_supply);
371
372 return 0;
373}
374
375
376
377
378
379
380static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
381{
382 u32 intmsk;
383
384 dev_dbg(hsotg->dev, "%s()\n", __func__);
385
386
387 dwc2_writel(hsotg, 0, GINTMSK);
388 dwc2_writel(hsotg, 0, HAINTMSK);
389
390
391 dwc2_enable_common_interrupts(hsotg);
392
393
394 intmsk = dwc2_readl(hsotg, GINTMSK);
395 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
396 dwc2_writel(hsotg, intmsk, GINTMSK);
397}
398
399
400
401
402
403
404static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
405{
406 u32 intmsk = dwc2_readl(hsotg, GINTMSK);
407
408
409 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
410 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
411 dwc2_writel(hsotg, intmsk, GINTMSK);
412}
413
414
415
416
417
418
419
420
421static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
422{
423 struct dwc2_core_params *params = &hsotg->params;
424 struct dwc2_hw_params *hw = &hsotg->hw_params;
425 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
426
427 total_fifo_size = hw->total_fifo_size;
428 rxfsiz = params->host_rx_fifo_size;
429 nptxfsiz = params->host_nperio_tx_fifo_size;
430 ptxfsiz = params->host_perio_tx_fifo_size;
431
432
433
434
435
436
437
438 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
439
440
441
442
443
444
445 rxfsiz = 516 + hw->host_channels;
446
447
448
449
450
451
452 nptxfsiz = 256;
453
454
455
456
457
458
459 ptxfsiz = 768;
460
461 params->host_rx_fifo_size = rxfsiz;
462 params->host_nperio_tx_fifo_size = nptxfsiz;
463 params->host_perio_tx_fifo_size = ptxfsiz;
464 }
465
466
467
468
469
470
471
472
473
474
475
476 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
477 dev_err(hsotg->dev, "invalid fifo sizes\n");
478}
479
480static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
481{
482 struct dwc2_core_params *params = &hsotg->params;
483 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
484
485 if (!params->enable_dynamic_fifo)
486 return;
487
488 dwc2_calculate_dynamic_fifo(hsotg);
489
490
491 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
492 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
493 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
494 grxfsiz |= params->host_rx_fifo_size <<
495 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
496 dwc2_writel(hsotg, grxfsiz, GRXFSIZ);
497 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
498 dwc2_readl(hsotg, GRXFSIZ));
499
500
501 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
502 dwc2_readl(hsotg, GNPTXFSIZ));
503 nptxfsiz = params->host_nperio_tx_fifo_size <<
504 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
505 nptxfsiz |= params->host_rx_fifo_size <<
506 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
507 dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ);
508 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
509 dwc2_readl(hsotg, GNPTXFSIZ));
510
511
512 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
513 dwc2_readl(hsotg, HPTXFSIZ));
514 hptxfsiz = params->host_perio_tx_fifo_size <<
515 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
516 hptxfsiz |= (params->host_rx_fifo_size +
517 params->host_nperio_tx_fifo_size) <<
518 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
519 dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ);
520 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
521 dwc2_readl(hsotg, HPTXFSIZ));
522
523 if (hsotg->params.en_multiple_tx_fifo &&
524 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
525
526
527
528
529
530 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
531 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
532 dfifocfg |= (params->host_rx_fifo_size +
533 params->host_nperio_tx_fifo_size +
534 params->host_perio_tx_fifo_size) <<
535 GDFIFOCFG_EPINFOBASE_SHIFT &
536 GDFIFOCFG_EPINFOBASE_MASK;
537 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG);
538 }
539}
540
541
542
543
544
545
546
547
548
549
550
551u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
552{
553 u32 usbcfg;
554 u32 hprt0;
555 int clock = 60;
556
557 usbcfg = dwc2_readl(hsotg, GUSBCFG);
558 hprt0 = dwc2_readl(hsotg, HPRT0);
559
560 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
561 !(usbcfg & GUSBCFG_PHYIF16))
562 clock = 60;
563 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
564 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
565 clock = 48;
566 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
567 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
568 clock = 30;
569 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
570 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
571 clock = 60;
572 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
573 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
574 clock = 48;
575 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
576 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
577 clock = 48;
578 if ((usbcfg & GUSBCFG_PHYSEL) &&
579 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
580 clock = 48;
581
582 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
583
584 return 125 * clock - 1;
585
586
587 return 1000 * clock - 1;
588}
589
590
591
592
593
594
595
596
597
598void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
599{
600 u32 *data_buf = (u32 *)dest;
601 int word_count = (bytes + 3) / 4;
602 int i;
603
604
605
606
607
608
609
610 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
611
612 for (i = 0; i < word_count; i++, data_buf++)
613 *data_buf = dwc2_readl(hsotg, HCFIFO(0));
614}
615
616
617
618
619
620
621
622
623
624
625
626
627static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
628 struct dwc2_host_chan *chan)
629{
630#ifdef VERBOSE_DEBUG
631 int num_channels = hsotg->params.host_channels;
632 struct dwc2_qh *qh;
633 u32 hcchar;
634 u32 hcsplt;
635 u32 hctsiz;
636 u32 hc_dma;
637 int i;
638
639 if (!chan)
640 return;
641
642 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
643 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
644 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num));
645 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num));
646
647 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
648 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
649 hcchar, hcsplt);
650 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
651 hctsiz, hc_dma);
652 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
653 chan->dev_addr, chan->ep_num, chan->ep_is_in);
654 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
655 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
656 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
657 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
658 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
659 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
660 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
661 (unsigned long)chan->xfer_dma);
662 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
663 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
664 dev_dbg(hsotg->dev, " NP inactive sched:\n");
665 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
666 qh_list_entry)
667 dev_dbg(hsotg->dev, " %p\n", qh);
668 dev_dbg(hsotg->dev, " NP waiting sched:\n");
669 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
670 qh_list_entry)
671 dev_dbg(hsotg->dev, " %p\n", qh);
672 dev_dbg(hsotg->dev, " NP active sched:\n");
673 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
674 qh_list_entry)
675 dev_dbg(hsotg->dev, " %p\n", qh);
676 dev_dbg(hsotg->dev, " Channels:\n");
677 for (i = 0; i < num_channels; i++) {
678 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
679
680 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
681 }
682#endif
683}
684
685static int _dwc2_hcd_start(struct usb_hcd *hcd);
686
687static void dwc2_host_start(struct dwc2_hsotg *hsotg)
688{
689 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
690
691 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
692 _dwc2_hcd_start(hcd);
693}
694
695static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
696{
697 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
698
699 hcd->self.is_b_host = 0;
700}
701
702static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
703 int *hub_addr, int *hub_port)
704{
705 struct urb *urb = context;
706
707 if (urb->dev->tt)
708 *hub_addr = urb->dev->tt->hub->devnum;
709 else
710 *hub_addr = 0;
711 *hub_port = urb->dev->ttport;
712}
713
714
715
716
717
718
719
720static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
721 struct dwc2_host_chan *chan)
722{
723 u32 hcintmsk = HCINTMSK_CHHLTD;
724
725 switch (chan->ep_type) {
726 case USB_ENDPOINT_XFER_CONTROL:
727 case USB_ENDPOINT_XFER_BULK:
728 dev_vdbg(hsotg->dev, "control/bulk\n");
729 hcintmsk |= HCINTMSK_XFERCOMPL;
730 hcintmsk |= HCINTMSK_STALL;
731 hcintmsk |= HCINTMSK_XACTERR;
732 hcintmsk |= HCINTMSK_DATATGLERR;
733 if (chan->ep_is_in) {
734 hcintmsk |= HCINTMSK_BBLERR;
735 } else {
736 hcintmsk |= HCINTMSK_NAK;
737 hcintmsk |= HCINTMSK_NYET;
738 if (chan->do_ping)
739 hcintmsk |= HCINTMSK_ACK;
740 }
741
742 if (chan->do_split) {
743 hcintmsk |= HCINTMSK_NAK;
744 if (chan->complete_split)
745 hcintmsk |= HCINTMSK_NYET;
746 else
747 hcintmsk |= HCINTMSK_ACK;
748 }
749
750 if (chan->error_state)
751 hcintmsk |= HCINTMSK_ACK;
752 break;
753
754 case USB_ENDPOINT_XFER_INT:
755 if (dbg_perio())
756 dev_vdbg(hsotg->dev, "intr\n");
757 hcintmsk |= HCINTMSK_XFERCOMPL;
758 hcintmsk |= HCINTMSK_NAK;
759 hcintmsk |= HCINTMSK_STALL;
760 hcintmsk |= HCINTMSK_XACTERR;
761 hcintmsk |= HCINTMSK_DATATGLERR;
762 hcintmsk |= HCINTMSK_FRMOVRUN;
763
764 if (chan->ep_is_in)
765 hcintmsk |= HCINTMSK_BBLERR;
766 if (chan->error_state)
767 hcintmsk |= HCINTMSK_ACK;
768 if (chan->do_split) {
769 if (chan->complete_split)
770 hcintmsk |= HCINTMSK_NYET;
771 else
772 hcintmsk |= HCINTMSK_ACK;
773 }
774 break;
775
776 case USB_ENDPOINT_XFER_ISOC:
777 if (dbg_perio())
778 dev_vdbg(hsotg->dev, "isoc\n");
779 hcintmsk |= HCINTMSK_XFERCOMPL;
780 hcintmsk |= HCINTMSK_FRMOVRUN;
781 hcintmsk |= HCINTMSK_ACK;
782
783 if (chan->ep_is_in) {
784 hcintmsk |= HCINTMSK_XACTERR;
785 hcintmsk |= HCINTMSK_BBLERR;
786 }
787 break;
788 default:
789 dev_err(hsotg->dev, "## Unknown EP type ##\n");
790 break;
791 }
792
793 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
794 if (dbg_hc(chan))
795 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
796}
797
798static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
799 struct dwc2_host_chan *chan)
800{
801 u32 hcintmsk = HCINTMSK_CHHLTD;
802
803
804
805
806
807 if (!hsotg->params.dma_desc_enable) {
808 if (dbg_hc(chan))
809 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
810 hcintmsk |= HCINTMSK_AHBERR;
811 } else {
812 if (dbg_hc(chan))
813 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
814 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
815 hcintmsk |= HCINTMSK_XFERCOMPL;
816 }
817
818 if (chan->error_state && !chan->do_split &&
819 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
820 if (dbg_hc(chan))
821 dev_vdbg(hsotg->dev, "setting ACK\n");
822 hcintmsk |= HCINTMSK_ACK;
823 if (chan->ep_is_in) {
824 hcintmsk |= HCINTMSK_DATATGLERR;
825 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
826 hcintmsk |= HCINTMSK_NAK;
827 }
828 }
829
830 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
831 if (dbg_hc(chan))
832 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
833}
834
835static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
836 struct dwc2_host_chan *chan)
837{
838 u32 intmsk;
839
840 if (hsotg->params.host_dma) {
841 if (dbg_hc(chan))
842 dev_vdbg(hsotg->dev, "DMA enabled\n");
843 dwc2_hc_enable_dma_ints(hsotg, chan);
844 } else {
845 if (dbg_hc(chan))
846 dev_vdbg(hsotg->dev, "DMA disabled\n");
847 dwc2_hc_enable_slave_ints(hsotg, chan);
848 }
849
850
851 intmsk = dwc2_readl(hsotg, HAINTMSK);
852 intmsk |= 1 << chan->hc_num;
853 dwc2_writel(hsotg, intmsk, HAINTMSK);
854 if (dbg_hc(chan))
855 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
856
857
858 intmsk = dwc2_readl(hsotg, GINTMSK);
859 intmsk |= GINTSTS_HCHINT;
860 dwc2_writel(hsotg, intmsk, GINTMSK);
861 if (dbg_hc(chan))
862 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
863}
864
865
866
867
868
869
870
871
872
873
874
875
876static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
877{
878 u8 hc_num = chan->hc_num;
879 u32 hcintmsk;
880 u32 hcchar;
881 u32 hcsplt = 0;
882
883 if (dbg_hc(chan))
884 dev_vdbg(hsotg->dev, "%s()\n", __func__);
885
886
887 hcintmsk = 0xffffffff;
888 hcintmsk &= ~HCINTMSK_RESERVED14_31;
889 dwc2_writel(hsotg, hcintmsk, HCINT(hc_num));
890
891
892 dwc2_hc_enable_ints(hsotg, chan);
893
894
895
896
897
898 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
899 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
900 if (chan->ep_is_in)
901 hcchar |= HCCHAR_EPDIR;
902 if (chan->speed == USB_SPEED_LOW)
903 hcchar |= HCCHAR_LSPDDEV;
904 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
905 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
906 dwc2_writel(hsotg, hcchar, HCCHAR(hc_num));
907 if (dbg_hc(chan)) {
908 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
909 hc_num, hcchar);
910
911 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
912 __func__, hc_num);
913 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
914 chan->dev_addr);
915 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
916 chan->ep_num);
917 dev_vdbg(hsotg->dev, " Is In: %d\n",
918 chan->ep_is_in);
919 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
920 chan->speed == USB_SPEED_LOW);
921 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
922 chan->ep_type);
923 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
924 chan->max_packet);
925 }
926
927
928 if (chan->do_split) {
929 if (dbg_hc(chan))
930 dev_vdbg(hsotg->dev,
931 "Programming HC %d with split --> %s\n",
932 hc_num,
933 chan->complete_split ? "CSPLIT" : "SSPLIT");
934 if (chan->complete_split)
935 hcsplt |= HCSPLT_COMPSPLT;
936 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
937 HCSPLT_XACTPOS_MASK;
938 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
939 HCSPLT_HUBADDR_MASK;
940 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
941 HCSPLT_PRTADDR_MASK;
942 if (dbg_hc(chan)) {
943 dev_vdbg(hsotg->dev, " comp split %d\n",
944 chan->complete_split);
945 dev_vdbg(hsotg->dev, " xact pos %d\n",
946 chan->xact_pos);
947 dev_vdbg(hsotg->dev, " hub addr %d\n",
948 chan->hub_addr);
949 dev_vdbg(hsotg->dev, " hub port %d\n",
950 chan->hub_port);
951 dev_vdbg(hsotg->dev, " is_in %d\n",
952 chan->ep_is_in);
953 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
954 chan->max_packet);
955 dev_vdbg(hsotg->dev, " xferlen %d\n",
956 chan->xfer_len);
957 }
958 }
959
960 dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num));
961}
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
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988
989
990
991void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
992 enum dwc2_halt_status halt_status)
993{
994 u32 nptxsts, hptxsts, hcchar;
995
996 if (dbg_hc(chan))
997 dev_vdbg(hsotg->dev, "%s()\n", __func__);
998
999
1000
1001
1002
1003
1004
1005 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
1006 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
1007 if (!chan->do_split &&
1008 (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
1009 chan->ep_type == USB_ENDPOINT_XFER_INT)) {
1010 dev_err(hsotg->dev, "%s() Channel can't be halted\n",
1011 __func__);
1012 return;
1013 }
1014 }
1015
1016 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1017 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1018
1019 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1020 halt_status == DWC2_HC_XFER_AHB_ERR) {
1021
1022
1023
1024
1025
1026
1027 u32 hcintmsk = HCINTMSK_CHHLTD;
1028
1029 dev_vdbg(hsotg->dev, "dequeue/error\n");
1030 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
1031
1032
1033
1034
1035
1036
1037 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num));
1038
1039
1040
1041
1042
1043
1044 chan->halt_status = halt_status;
1045
1046 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1047 if (!(hcchar & HCCHAR_CHENA)) {
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059 return;
1060 }
1061 }
1062 if (chan->halt_pending) {
1063
1064
1065
1066
1067
1068 dev_vdbg(hsotg->dev,
1069 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1070 __func__, chan->hc_num);
1071 return;
1072 }
1073
1074 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1075
1076
1077
1078 if (!hsotg->params.dma_desc_enable) {
1079 if (dbg_hc(chan))
1080 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1081 hcchar |= HCCHAR_CHENA;
1082 } else {
1083 if (dbg_hc(chan))
1084 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1085 }
1086 hcchar |= HCCHAR_CHDIS;
1087
1088 if (!hsotg->params.host_dma) {
1089 if (dbg_hc(chan))
1090 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1091 hcchar |= HCCHAR_CHENA;
1092
1093
1094 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1095 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1096 dev_vdbg(hsotg->dev, "control/bulk\n");
1097 nptxsts = dwc2_readl(hsotg, GNPTXSTS);
1098 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1099 dev_vdbg(hsotg->dev, "Disabling channel\n");
1100 hcchar &= ~HCCHAR_CHENA;
1101 }
1102 } else {
1103 if (dbg_perio())
1104 dev_vdbg(hsotg->dev, "isoc/intr\n");
1105 hptxsts = dwc2_readl(hsotg, HPTXSTS);
1106 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1107 hsotg->queuing_high_bandwidth) {
1108 if (dbg_perio())
1109 dev_vdbg(hsotg->dev, "Disabling channel\n");
1110 hcchar &= ~HCCHAR_CHENA;
1111 }
1112 }
1113 } else {
1114 if (dbg_hc(chan))
1115 dev_vdbg(hsotg->dev, "DMA enabled\n");
1116 }
1117
1118 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1119 chan->halt_status = halt_status;
1120
1121 if (hcchar & HCCHAR_CHENA) {
1122 if (dbg_hc(chan))
1123 dev_vdbg(hsotg->dev, "Channel enabled\n");
1124 chan->halt_pending = 1;
1125 chan->halt_on_queue = 0;
1126 } else {
1127 if (dbg_hc(chan))
1128 dev_vdbg(hsotg->dev, "Channel disabled\n");
1129 chan->halt_on_queue = 1;
1130 }
1131
1132 if (dbg_hc(chan)) {
1133 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1134 chan->hc_num);
1135 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1136 hcchar);
1137 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1138 chan->halt_pending);
1139 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1140 chan->halt_on_queue);
1141 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1142 chan->halt_status);
1143 }
1144}
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1156{
1157 u32 hcintmsk;
1158
1159 chan->xfer_started = 0;
1160
1161 list_del_init(&chan->split_order_list_entry);
1162
1163
1164
1165
1166
1167 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num));
1168 hcintmsk = 0xffffffff;
1169 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1170 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num));
1171}
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1184 struct dwc2_host_chan *chan, u32 *hcchar)
1185{
1186 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1187 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1188 int host_speed;
1189 int xfer_ns;
1190 int xfer_us;
1191 int bytes_in_fifo;
1192 u16 fifo_space;
1193 u16 frame_number;
1194 u16 wire_frame;
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220 host_speed = (chan->speed != USB_SPEED_HIGH &&
1221 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1222
1223
1224 fifo_space = (dwc2_readl(hsotg, HPTXSTS) &
1225 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1226 bytes_in_fifo = sizeof(u32) *
1227 (hsotg->params.host_perio_tx_fifo_size -
1228 fifo_space);
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1239 chan->xfer_len + bytes_in_fifo);
1240 xfer_us = NS_TO_US(xfer_ns);
1241
1242
1243 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1244
1245
1246 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1247
1248
1249
1250
1251
1252
1253
1254
1255 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1256 dwc2_sch_vdbg(hsotg,
1257 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1258 chan->qh, wire_frame, frame_number,
1259 dwc2_frame_num_dec(frame_number,
1260 wire_frame));
1261 wire_frame = frame_number;
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271 chan->qh->next_active_frame =
1272 dwc2_frame_num_dec(frame_number, 1);
1273 }
1274
1275 if (wire_frame & 1)
1276 *hcchar |= HCCHAR_ODDFRM;
1277 else
1278 *hcchar &= ~HCCHAR_ODDFRM;
1279 }
1280}
1281
1282static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1283{
1284
1285 if (chan->speed == USB_SPEED_HIGH) {
1286 if (chan->ep_is_in) {
1287 if (chan->multi_count == 1)
1288 chan->data_pid_start = DWC2_HC_PID_DATA0;
1289 else if (chan->multi_count == 2)
1290 chan->data_pid_start = DWC2_HC_PID_DATA1;
1291 else
1292 chan->data_pid_start = DWC2_HC_PID_DATA2;
1293 } else {
1294 if (chan->multi_count == 1)
1295 chan->data_pid_start = DWC2_HC_PID_DATA0;
1296 else
1297 chan->data_pid_start = DWC2_HC_PID_MDATA;
1298 }
1299 } else {
1300 chan->data_pid_start = DWC2_HC_PID_DATA0;
1301 }
1302}
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1319 struct dwc2_host_chan *chan)
1320{
1321 u32 i;
1322 u32 remaining_count;
1323 u32 byte_count;
1324 u32 dword_count;
1325 u32 *data_buf = (u32 *)chan->xfer_buf;
1326
1327 if (dbg_hc(chan))
1328 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1329
1330 remaining_count = chan->xfer_len - chan->xfer_count;
1331 if (remaining_count > chan->max_packet)
1332 byte_count = chan->max_packet;
1333 else
1334 byte_count = remaining_count;
1335
1336 dword_count = (byte_count + 3) / 4;
1337
1338 if (((unsigned long)data_buf & 0x3) == 0) {
1339
1340 for (i = 0; i < dword_count; i++, data_buf++)
1341 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num));
1342 } else {
1343
1344 for (i = 0; i < dword_count; i++, data_buf++) {
1345 u32 data = data_buf[0] | data_buf[1] << 8 |
1346 data_buf[2] << 16 | data_buf[3] << 24;
1347 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num));
1348 }
1349 }
1350
1351 chan->xfer_count += byte_count;
1352 chan->xfer_buf += byte_count;
1353}
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1365 struct dwc2_host_chan *chan)
1366{
1367 u32 hcchar;
1368 u32 hctsiz;
1369
1370 if (dbg_hc(chan))
1371 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1372 chan->hc_num);
1373
1374 hctsiz = TSIZ_DOPNG;
1375 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1376 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1377
1378 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1379 hcchar |= HCCHAR_CHENA;
1380 hcchar &= ~HCCHAR_CHDIS;
1381 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1382}
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
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1409
1410
1411
1412
1413
1414
1415
1416
1417static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1418 struct dwc2_host_chan *chan)
1419{
1420 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1421 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1422 u32 hcchar;
1423 u32 hctsiz = 0;
1424 u16 num_packets;
1425 u32 ec_mc;
1426
1427 if (dbg_hc(chan))
1428 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1429
1430 if (chan->do_ping) {
1431 if (!hsotg->params.host_dma) {
1432 if (dbg_hc(chan))
1433 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1434 dwc2_hc_do_ping(hsotg, chan);
1435 chan->xfer_started = 1;
1436 return;
1437 }
1438
1439 if (dbg_hc(chan))
1440 dev_vdbg(hsotg->dev, "ping, DMA\n");
1441
1442 hctsiz |= TSIZ_DOPNG;
1443 }
1444
1445 if (chan->do_split) {
1446 if (dbg_hc(chan))
1447 dev_vdbg(hsotg->dev, "split\n");
1448 num_packets = 1;
1449
1450 if (chan->complete_split && !chan->ep_is_in)
1451
1452
1453
1454
1455 chan->xfer_len = 0;
1456 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1457 chan->xfer_len = chan->max_packet;
1458 else if (!chan->ep_is_in && chan->xfer_len > 188)
1459 chan->xfer_len = 188;
1460
1461 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1462 TSIZ_XFERSIZE_MASK;
1463
1464
1465 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1466 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1467 ec_mc = 3;
1468 else
1469 ec_mc = 1;
1470 } else {
1471 if (dbg_hc(chan))
1472 dev_vdbg(hsotg->dev, "no split\n");
1473
1474
1475
1476
1477 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1478 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1479
1480
1481
1482
1483
1484
1485
1486 u32 max_periodic_len =
1487 chan->multi_count * chan->max_packet;
1488
1489 if (chan->xfer_len > max_periodic_len)
1490 chan->xfer_len = max_periodic_len;
1491 } else if (chan->xfer_len > max_hc_xfer_size) {
1492
1493
1494
1495
1496 chan->xfer_len =
1497 max_hc_xfer_size - chan->max_packet + 1;
1498 }
1499
1500 if (chan->xfer_len > 0) {
1501 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1502 chan->max_packet;
1503 if (num_packets > max_hc_pkt_count) {
1504 num_packets = max_hc_pkt_count;
1505 chan->xfer_len = num_packets * chan->max_packet;
1506 }
1507 } else {
1508
1509 num_packets = 1;
1510 }
1511
1512 if (chan->ep_is_in)
1513
1514
1515
1516
1517 chan->xfer_len = num_packets * chan->max_packet;
1518
1519 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1520 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1521
1522
1523
1524
1525 chan->multi_count = num_packets;
1526
1527 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1528 dwc2_set_pid_isoc(chan);
1529
1530 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1531 TSIZ_XFERSIZE_MASK;
1532
1533
1534 ec_mc = chan->multi_count;
1535 }
1536
1537 chan->start_pkt_count = num_packets;
1538 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1539 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1540 TSIZ_SC_MC_PID_MASK;
1541 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1542 if (dbg_hc(chan)) {
1543 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1544 hctsiz, chan->hc_num);
1545
1546 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1547 chan->hc_num);
1548 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1549 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1550 TSIZ_XFERSIZE_SHIFT);
1551 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1552 (hctsiz & TSIZ_PKTCNT_MASK) >>
1553 TSIZ_PKTCNT_SHIFT);
1554 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1555 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1556 TSIZ_SC_MC_PID_SHIFT);
1557 }
1558
1559 if (hsotg->params.host_dma) {
1560 dma_addr_t dma_addr;
1561
1562 if (chan->align_buf) {
1563 if (dbg_hc(chan))
1564 dev_vdbg(hsotg->dev, "align_buf\n");
1565 dma_addr = chan->align_buf;
1566 } else {
1567 dma_addr = chan->xfer_dma;
1568 }
1569 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));
1570
1571 if (dbg_hc(chan))
1572 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1573 (unsigned long)dma_addr, chan->hc_num);
1574 }
1575
1576
1577 if (chan->do_split) {
1578 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
1579
1580 hcsplt |= HCSPLT_SPLTENA;
1581 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num));
1582 }
1583
1584 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1585 hcchar &= ~HCCHAR_MULTICNT_MASK;
1586 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1587 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1588
1589 if (hcchar & HCCHAR_CHDIS)
1590 dev_warn(hsotg->dev,
1591 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1592 __func__, chan->hc_num, hcchar);
1593
1594
1595 hcchar |= HCCHAR_CHENA;
1596 hcchar &= ~HCCHAR_CHDIS;
1597
1598 if (dbg_hc(chan))
1599 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1600 (hcchar & HCCHAR_MULTICNT_MASK) >>
1601 HCCHAR_MULTICNT_SHIFT);
1602
1603 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1604 if (dbg_hc(chan))
1605 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1606 chan->hc_num);
1607
1608 chan->xfer_started = 1;
1609 chan->requests++;
1610
1611 if (!hsotg->params.host_dma &&
1612 !chan->ep_is_in && chan->xfer_len > 0)
1613
1614 dwc2_hc_write_packet(hsotg, chan);
1615}
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1632 struct dwc2_host_chan *chan)
1633{
1634 u32 hcchar;
1635 u32 hctsiz = 0;
1636
1637 if (chan->do_ping)
1638 hctsiz |= TSIZ_DOPNG;
1639
1640 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1641 dwc2_set_pid_isoc(chan);
1642
1643
1644 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1645 TSIZ_SC_MC_PID_MASK;
1646
1647
1648 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1649
1650
1651 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1652
1653 if (dbg_hc(chan)) {
1654 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1655 chan->hc_num);
1656 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1657 chan->data_pid_start);
1658 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1659 }
1660
1661 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1662
1663 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1664 chan->desc_list_sz, DMA_TO_DEVICE);
1665
1666 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
1667
1668 if (dbg_hc(chan))
1669 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1670 &chan->desc_list_addr, chan->hc_num);
1671
1672 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1673 hcchar &= ~HCCHAR_MULTICNT_MASK;
1674 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1675 HCCHAR_MULTICNT_MASK;
1676
1677 if (hcchar & HCCHAR_CHDIS)
1678 dev_warn(hsotg->dev,
1679 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1680 __func__, chan->hc_num, hcchar);
1681
1682
1683 hcchar |= HCCHAR_CHENA;
1684 hcchar &= ~HCCHAR_CHDIS;
1685
1686 if (dbg_hc(chan))
1687 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1688 (hcchar & HCCHAR_MULTICNT_MASK) >>
1689 HCCHAR_MULTICNT_SHIFT);
1690
1691 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1692 if (dbg_hc(chan))
1693 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1694 chan->hc_num);
1695
1696 chan->xfer_started = 1;
1697 chan->requests++;
1698}
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1721 struct dwc2_host_chan *chan)
1722{
1723 if (dbg_hc(chan))
1724 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1725 chan->hc_num);
1726
1727 if (chan->do_split)
1728
1729 return 0;
1730
1731 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1732
1733 return 0;
1734
1735 if (chan->ep_is_in) {
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1749
1750 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1751 hcchar |= HCCHAR_CHENA;
1752 hcchar &= ~HCCHAR_CHDIS;
1753 if (dbg_hc(chan))
1754 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1755 hcchar);
1756 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1757 chan->requests++;
1758 return 1;
1759 }
1760
1761
1762
1763 if (chan->xfer_count < chan->xfer_len) {
1764 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1765 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1766 u32 hcchar = dwc2_readl(hsotg,
1767 HCCHAR(chan->hc_num));
1768
1769 dwc2_hc_set_even_odd_frame(hsotg, chan,
1770 &hcchar);
1771 }
1772
1773
1774 dwc2_hc_write_packet(hsotg, chan);
1775 chan->requests++;
1776 return 1;
1777 }
1778
1779 return 0;
1780}
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1795 struct list_head *qh_list)
1796{
1797 struct dwc2_qh *qh, *qh_tmp;
1798 struct dwc2_qtd *qtd, *qtd_tmp;
1799
1800 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1801 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1802 qtd_list_entry) {
1803 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1804 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1805 }
1806 }
1807}
1808
1809static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1810 struct list_head *qh_list)
1811{
1812 struct dwc2_qtd *qtd, *qtd_tmp;
1813 struct dwc2_qh *qh, *qh_tmp;
1814 unsigned long flags;
1815
1816 if (!qh_list->next)
1817
1818 return;
1819
1820 spin_lock_irqsave(&hsotg->lock, flags);
1821
1822
1823 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1824
1825 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1826 dwc2_hcd_qh_unlink(hsotg, qh);
1827
1828
1829 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1830 qtd_list_entry)
1831 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1832
1833 if (qh->channel && qh->channel->qh == qh)
1834 qh->channel->qh = NULL;
1835
1836 spin_unlock_irqrestore(&hsotg->lock, flags);
1837 dwc2_hcd_qh_free(hsotg, qh);
1838 spin_lock_irqsave(&hsotg->lock, flags);
1839 }
1840
1841 spin_unlock_irqrestore(&hsotg->lock, flags);
1842}
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1853{
1854 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1855 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1856 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1857 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1858 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1859 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1860 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1861}
1862
1863
1864
1865
1866
1867
1868void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1869{
1870 u32 hprt0;
1871
1872 if (hsotg->op_state == OTG_STATE_B_HOST) {
1873
1874
1875
1876
1877
1878 hprt0 = dwc2_read_hprt0(hsotg);
1879 hprt0 |= HPRT0_RST;
1880 dwc2_writel(hsotg, hprt0, HPRT0);
1881 }
1882
1883 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1884 msecs_to_jiffies(50));
1885}
1886
1887
1888static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1889{
1890 int num_channels = hsotg->params.host_channels;
1891 struct dwc2_host_chan *channel;
1892 u32 hcchar;
1893 int i;
1894
1895 if (!hsotg->params.host_dma) {
1896
1897 for (i = 0; i < num_channels; i++) {
1898 channel = hsotg->hc_ptr_array[i];
1899 if (!list_empty(&channel->hc_list_entry))
1900 continue;
1901 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1902 if (hcchar & HCCHAR_CHENA) {
1903 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1904 hcchar |= HCCHAR_CHDIS;
1905 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1906 }
1907 }
1908 }
1909
1910 for (i = 0; i < num_channels; i++) {
1911 channel = hsotg->hc_ptr_array[i];
1912 if (!list_empty(&channel->hc_list_entry))
1913 continue;
1914 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1915 if (hcchar & HCCHAR_CHENA) {
1916
1917 hcchar |= HCCHAR_CHDIS;
1918 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1919 }
1920
1921 dwc2_hc_cleanup(hsotg, channel);
1922 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1923
1924
1925
1926
1927
1928 channel->qh = NULL;
1929 }
1930
1931 if (hsotg->params.uframe_sched) {
1932 hsotg->available_host_channels =
1933 hsotg->params.host_channels;
1934 } else {
1935 hsotg->non_periodic_channels = 0;
1936 hsotg->periodic_channels = 0;
1937 }
1938}
1939
1940
1941
1942
1943
1944
1945
1946
1947void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1948{
1949 if (hsotg->lx_state != DWC2_L0)
1950 usb_hcd_resume_root_hub(hsotg->priv);
1951
1952 hsotg->flags.b.port_connect_status_change = 1;
1953 hsotg->flags.b.port_connect_status = 1;
1954}
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1965{
1966 u32 intr;
1967 u32 hprt0;
1968
1969
1970 hsotg->flags.b.port_connect_status_change = 1;
1971 hsotg->flags.b.port_connect_status = 0;
1972
1973
1974
1975
1976
1977
1978 intr = dwc2_readl(hsotg, GINTMSK);
1979 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1980 dwc2_writel(hsotg, intr, GINTMSK);
1981 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1982 dwc2_writel(hsotg, intr, GINTSTS);
1983
1984
1985
1986
1987
1988
1989 if (dwc2_is_device_mode(hsotg)) {
1990 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1991 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1992 dwc2_writel(hsotg, 0, HPRT0);
1993 }
1994
1995 dwc2_disable_host_interrupts(hsotg);
1996 }
1997
1998
1999 dwc2_kill_all_urbs(hsotg);
2000
2001 if (dwc2_is_host_mode(hsotg))
2002
2003 dwc2_hcd_cleanup_channels(hsotg);
2004
2005 dwc2_host_disconnect(hsotg);
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019 if (!force) {
2020 hprt0 = dwc2_readl(hsotg, HPRT0);
2021 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
2022 dwc2_hcd_connect(hsotg);
2023 }
2024}
2025
2026
2027
2028
2029
2030
2031static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
2032{
2033 if (hsotg->bus_suspended) {
2034 hsotg->flags.b.port_suspend_change = 1;
2035 usb_hcd_resume_root_hub(hsotg->priv);
2036 }
2037
2038 if (hsotg->lx_state == DWC2_L1)
2039 hsotg->flags.b.port_l1_change = 1;
2040}
2041
2042
2043
2044
2045
2046
2047
2048
2049void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
2050{
2051 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
2052
2053
2054
2055
2056
2057
2058
2059
2060 dwc2_disable_host_interrupts(hsotg);
2061
2062
2063 dev_dbg(hsotg->dev, "PortPower off\n");
2064 dwc2_writel(hsotg, 0, HPRT0);
2065}
2066
2067
2068static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2069 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
2070 struct dwc2_qtd *qtd)
2071{
2072 u32 intr_mask;
2073 int retval;
2074 int dev_speed;
2075
2076 if (!hsotg->flags.b.port_connect_status) {
2077
2078 dev_err(hsotg->dev, "Not connected\n");
2079 return -ENODEV;
2080 }
2081
2082 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
2083
2084
2085 if ((dev_speed == USB_SPEED_LOW) &&
2086 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2087 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2088 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
2089 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2090
2091 if (prtspd == HPRT0_SPD_FULL_SPEED)
2092 return -ENODEV;
2093 }
2094
2095 if (!qtd)
2096 return -EINVAL;
2097
2098 dwc2_hcd_qtd_init(qtd, urb);
2099 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
2100 if (retval) {
2101 dev_err(hsotg->dev,
2102 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2103 retval);
2104 return retval;
2105 }
2106
2107 intr_mask = dwc2_readl(hsotg, GINTMSK);
2108 if (!(intr_mask & GINTSTS_SOF)) {
2109 enum dwc2_transaction_type tr_type;
2110
2111 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2112 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2113
2114
2115
2116
2117 return 0;
2118
2119 tr_type = dwc2_hcd_select_transactions(hsotg);
2120 if (tr_type != DWC2_TRANSACTION_NONE)
2121 dwc2_hcd_queue_transactions(hsotg, tr_type);
2122 }
2123
2124 return 0;
2125}
2126
2127
2128static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2129 struct dwc2_hcd_urb *urb)
2130{
2131 struct dwc2_qh *qh;
2132 struct dwc2_qtd *urb_qtd;
2133
2134 urb_qtd = urb->qtd;
2135 if (!urb_qtd) {
2136 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2137 return -EINVAL;
2138 }
2139
2140 qh = urb_qtd->qh;
2141 if (!qh) {
2142 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2143 return -EINVAL;
2144 }
2145
2146 urb->priv = NULL;
2147
2148 if (urb_qtd->in_process && qh->channel) {
2149 dwc2_dump_channel_info(hsotg, qh->channel);
2150
2151
2152 if (hsotg->flags.b.port_connect_status)
2153
2154
2155
2156
2157
2158
2159
2160 dwc2_hc_halt(hsotg, qh->channel,
2161 DWC2_HC_XFER_URB_DEQUEUE);
2162 }
2163
2164
2165
2166
2167
2168 if (!hsotg->params.dma_desc_enable) {
2169 u8 in_process = urb_qtd->in_process;
2170
2171 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2172 if (in_process) {
2173 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2174 qh->channel = NULL;
2175 } else if (list_empty(&qh->qtd_list)) {
2176 dwc2_hcd_qh_unlink(hsotg, qh);
2177 }
2178 } else {
2179 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2180 }
2181
2182 return 0;
2183}
2184
2185
2186static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2187 struct usb_host_endpoint *ep, int retry)
2188{
2189 struct dwc2_qtd *qtd, *qtd_tmp;
2190 struct dwc2_qh *qh;
2191 unsigned long flags;
2192 int rc;
2193
2194 spin_lock_irqsave(&hsotg->lock, flags);
2195
2196 qh = ep->hcpriv;
2197 if (!qh) {
2198 rc = -EINVAL;
2199 goto err;
2200 }
2201
2202 while (!list_empty(&qh->qtd_list) && retry--) {
2203 if (retry == 0) {
2204 dev_err(hsotg->dev,
2205 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2206 rc = -EBUSY;
2207 goto err;
2208 }
2209
2210 spin_unlock_irqrestore(&hsotg->lock, flags);
2211 msleep(20);
2212 spin_lock_irqsave(&hsotg->lock, flags);
2213 qh = ep->hcpriv;
2214 if (!qh) {
2215 rc = -EINVAL;
2216 goto err;
2217 }
2218 }
2219
2220 dwc2_hcd_qh_unlink(hsotg, qh);
2221
2222
2223 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2224 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2225
2226 ep->hcpriv = NULL;
2227
2228 if (qh->channel && qh->channel->qh == qh)
2229 qh->channel->qh = NULL;
2230
2231 spin_unlock_irqrestore(&hsotg->lock, flags);
2232
2233 dwc2_hcd_qh_free(hsotg, qh);
2234
2235 return 0;
2236
2237err:
2238 ep->hcpriv = NULL;
2239 spin_unlock_irqrestore(&hsotg->lock, flags);
2240
2241 return rc;
2242}
2243
2244
2245static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2246 struct usb_host_endpoint *ep)
2247{
2248 struct dwc2_qh *qh = ep->hcpriv;
2249
2250 if (!qh)
2251 return -EINVAL;
2252
2253 qh->data_toggle = DWC2_HC_PID_DATA0;
2254
2255 return 0;
2256}
2257
2258
2259
2260
2261
2262
2263
2264
2265int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2266{
2267 u32 usbcfg, otgctl;
2268 int retval;
2269
2270 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2271
2272 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2273
2274
2275 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2276 if (hsotg->params.phy_ulpi_ext_vbus)
2277 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2278
2279
2280 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2281 if (hsotg->params.ts_dline)
2282 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2283
2284 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2285
2286
2287
2288
2289
2290
2291
2292
2293 if (!initial_setup) {
2294 retval = dwc2_core_reset(hsotg, false);
2295 if (retval) {
2296 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2297 __func__);
2298 return retval;
2299 }
2300 }
2301
2302
2303
2304
2305 retval = dwc2_phy_init(hsotg, initial_setup);
2306 if (retval)
2307 return retval;
2308
2309
2310 retval = dwc2_gahbcfg_init(hsotg);
2311 if (retval)
2312 return retval;
2313
2314
2315 dwc2_gusbcfg_init(hsotg);
2316
2317
2318 otgctl = dwc2_readl(hsotg, GOTGCTL);
2319 otgctl &= ~GOTGCTL_OTGVER;
2320 dwc2_writel(hsotg, otgctl, GOTGCTL);
2321
2322
2323 hsotg->srp_success = 0;
2324
2325
2326 dwc2_enable_common_interrupts(hsotg);
2327
2328
2329
2330
2331
2332 if (dwc2_is_host_mode(hsotg)) {
2333 dev_dbg(hsotg->dev, "Host Mode\n");
2334 hsotg->op_state = OTG_STATE_A_HOST;
2335 } else {
2336 dev_dbg(hsotg->dev, "Device Mode\n");
2337 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2338 }
2339
2340 return 0;
2341}
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2354{
2355 u32 hcfg, hfir, otgctl, usbcfg;
2356
2357 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2368 usbcfg |= GUSBCFG_TOUTCAL(7);
2369 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2370
2371
2372 dwc2_writel(hsotg, 0, PCGCTL);
2373
2374
2375 dwc2_init_fs_ls_pclk_sel(hsotg);
2376 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2377 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2378 hcfg = dwc2_readl(hsotg, HCFG);
2379 hcfg |= HCFG_FSLSSUPP;
2380 dwc2_writel(hsotg, hcfg, HCFG);
2381 }
2382
2383
2384
2385
2386
2387
2388 if (hsotg->params.reload_ctl) {
2389 hfir = dwc2_readl(hsotg, HFIR);
2390 hfir |= HFIR_RLDCTRL;
2391 dwc2_writel(hsotg, hfir, HFIR);
2392 }
2393
2394 if (hsotg->params.dma_desc_enable) {
2395 u32 op_mode = hsotg->hw_params.op_mode;
2396
2397 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2398 !hsotg->hw_params.dma_desc_enable ||
2399 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2400 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2401 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2402 dev_err(hsotg->dev,
2403 "Hardware does not support descriptor DMA mode -\n");
2404 dev_err(hsotg->dev,
2405 "falling back to buffer DMA mode.\n");
2406 hsotg->params.dma_desc_enable = false;
2407 } else {
2408 hcfg = dwc2_readl(hsotg, HCFG);
2409 hcfg |= HCFG_DESCDMA;
2410 dwc2_writel(hsotg, hcfg, HCFG);
2411 }
2412 }
2413
2414
2415 dwc2_config_fifos(hsotg);
2416
2417
2418
2419 otgctl = dwc2_readl(hsotg, GOTGCTL);
2420 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2421 dwc2_writel(hsotg, otgctl, GOTGCTL);
2422
2423
2424 dwc2_flush_tx_fifo(hsotg, 0x10 );
2425 dwc2_flush_rx_fifo(hsotg);
2426
2427
2428 otgctl = dwc2_readl(hsotg, GOTGCTL);
2429 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2430 dwc2_writel(hsotg, otgctl, GOTGCTL);
2431
2432 if (!hsotg->params.dma_desc_enable) {
2433 int num_channels, i;
2434 u32 hcchar;
2435
2436
2437 num_channels = hsotg->params.host_channels;
2438 for (i = 0; i < num_channels; i++) {
2439 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2440 hcchar &= ~HCCHAR_CHENA;
2441 hcchar |= HCCHAR_CHDIS;
2442 hcchar &= ~HCCHAR_EPDIR;
2443 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2444 }
2445
2446
2447 for (i = 0; i < num_channels; i++) {
2448 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2449 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2450 hcchar &= ~HCCHAR_EPDIR;
2451 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2452 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2453 __func__, i);
2454
2455 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2456 HCCHAR_CHENA, 1000)) {
2457 dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n",
2458 i);
2459 }
2460 }
2461 }
2462
2463
2464 dwc2_enable_acg(hsotg);
2465
2466
2467 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2468 if (hsotg->op_state == OTG_STATE_A_HOST) {
2469 u32 hprt0 = dwc2_read_hprt0(hsotg);
2470
2471 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2472 !!(hprt0 & HPRT0_PWR));
2473 if (!(hprt0 & HPRT0_PWR)) {
2474 hprt0 |= HPRT0_PWR;
2475 dwc2_writel(hsotg, hprt0, HPRT0);
2476 }
2477 }
2478
2479 dwc2_enable_host_interrupts(hsotg);
2480}
2481
2482
2483
2484
2485
2486
2487static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2488{
2489 struct dwc2_host_chan *chan, *chan_tmp;
2490 int num_channels;
2491 int i;
2492
2493 hsotg->flags.d32 = 0;
2494 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2495
2496 if (hsotg->params.uframe_sched) {
2497 hsotg->available_host_channels =
2498 hsotg->params.host_channels;
2499 } else {
2500 hsotg->non_periodic_channels = 0;
2501 hsotg->periodic_channels = 0;
2502 }
2503
2504
2505
2506
2507
2508 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2509 hc_list_entry)
2510 list_del_init(&chan->hc_list_entry);
2511
2512 num_channels = hsotg->params.host_channels;
2513 for (i = 0; i < num_channels; i++) {
2514 chan = hsotg->hc_ptr_array[i];
2515 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2516 dwc2_hc_cleanup(hsotg, chan);
2517 }
2518
2519
2520 dwc2_core_host_init(hsotg);
2521}
2522
2523static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2524 struct dwc2_host_chan *chan,
2525 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2526{
2527 int hub_addr, hub_port;
2528
2529 chan->do_split = 1;
2530 chan->xact_pos = qtd->isoc_split_pos;
2531 chan->complete_split = qtd->complete_split;
2532 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2533 chan->hub_addr = (u8)hub_addr;
2534 chan->hub_port = (u8)hub_port;
2535}
2536
2537static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2538 struct dwc2_host_chan *chan,
2539 struct dwc2_qtd *qtd)
2540{
2541 struct dwc2_hcd_urb *urb = qtd->urb;
2542 struct dwc2_hcd_iso_packet_desc *frame_desc;
2543
2544 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2545 case USB_ENDPOINT_XFER_CONTROL:
2546 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2547
2548 switch (qtd->control_phase) {
2549 case DWC2_CONTROL_SETUP:
2550 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2551 chan->do_ping = 0;
2552 chan->ep_is_in = 0;
2553 chan->data_pid_start = DWC2_HC_PID_SETUP;
2554 if (hsotg->params.host_dma)
2555 chan->xfer_dma = urb->setup_dma;
2556 else
2557 chan->xfer_buf = urb->setup_packet;
2558 chan->xfer_len = 8;
2559 break;
2560
2561 case DWC2_CONTROL_DATA:
2562 dev_vdbg(hsotg->dev, " Control data transaction\n");
2563 chan->data_pid_start = qtd->data_toggle;
2564 break;
2565
2566 case DWC2_CONTROL_STATUS:
2567
2568
2569
2570
2571 dev_vdbg(hsotg->dev, " Control status transaction\n");
2572 if (urb->length == 0)
2573 chan->ep_is_in = 1;
2574 else
2575 chan->ep_is_in =
2576 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2577 if (chan->ep_is_in)
2578 chan->do_ping = 0;
2579 chan->data_pid_start = DWC2_HC_PID_DATA1;
2580 chan->xfer_len = 0;
2581 if (hsotg->params.host_dma)
2582 chan->xfer_dma = hsotg->status_buf_dma;
2583 else
2584 chan->xfer_buf = hsotg->status_buf;
2585 break;
2586 }
2587 break;
2588
2589 case USB_ENDPOINT_XFER_BULK:
2590 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2591 break;
2592
2593 case USB_ENDPOINT_XFER_INT:
2594 chan->ep_type = USB_ENDPOINT_XFER_INT;
2595 break;
2596
2597 case USB_ENDPOINT_XFER_ISOC:
2598 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2599 if (hsotg->params.dma_desc_enable)
2600 break;
2601
2602 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2603 frame_desc->status = 0;
2604
2605 if (hsotg->params.host_dma) {
2606 chan->xfer_dma = urb->dma;
2607 chan->xfer_dma += frame_desc->offset +
2608 qtd->isoc_split_offset;
2609 } else {
2610 chan->xfer_buf = urb->buf;
2611 chan->xfer_buf += frame_desc->offset +
2612 qtd->isoc_split_offset;
2613 }
2614
2615 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2616
2617 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2618 if (chan->xfer_len <= 188)
2619 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2620 else
2621 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2622 }
2623 break;
2624 }
2625}
2626
2627static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
2628 struct dwc2_qh *qh,
2629 struct dwc2_host_chan *chan)
2630{
2631 if (!hsotg->unaligned_cache ||
2632 chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE)
2633 return -ENOMEM;
2634
2635 if (!qh->dw_align_buf) {
2636 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
2637 GFP_ATOMIC | GFP_DMA);
2638 if (!qh->dw_align_buf)
2639 return -ENOMEM;
2640 }
2641
2642 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
2643 DWC2_KMEM_UNALIGNED_BUF_SIZE,
2644 DMA_FROM_DEVICE);
2645
2646 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
2647 dev_err(hsotg->dev, "can't map align_buf\n");
2648 chan->align_buf = 0;
2649 return -EINVAL;
2650 }
2651
2652 chan->align_buf = qh->dw_align_buf_dma;
2653 return 0;
2654}
2655
2656#define DWC2_USB_DMA_ALIGN 4
2657
2658static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2659{
2660 void *stored_xfer_buffer;
2661 size_t length;
2662
2663 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2664 return;
2665
2666
2667 memcpy(&stored_xfer_buffer, urb->transfer_buffer +
2668 urb->transfer_buffer_length, sizeof(urb->transfer_buffer));
2669
2670 if (usb_urb_dir_in(urb)) {
2671 if (usb_pipeisoc(urb->pipe))
2672 length = urb->transfer_buffer_length;
2673 else
2674 length = urb->actual_length;
2675
2676 memcpy(stored_xfer_buffer, urb->transfer_buffer, length);
2677 }
2678 kfree(urb->transfer_buffer);
2679 urb->transfer_buffer = stored_xfer_buffer;
2680
2681 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2682}
2683
2684static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2685{
2686 void *kmalloc_ptr;
2687 size_t kmalloc_size;
2688
2689 if (urb->num_sgs || urb->sg ||
2690 urb->transfer_buffer_length == 0 ||
2691 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2692 return 0;
2693
2694
2695
2696
2697
2698
2699 kmalloc_size = urb->transfer_buffer_length +
2700 sizeof(urb->transfer_buffer);
2701
2702 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2703 if (!kmalloc_ptr)
2704 return -ENOMEM;
2705
2706
2707
2708
2709
2710 memcpy(kmalloc_ptr + urb->transfer_buffer_length,
2711 &urb->transfer_buffer, sizeof(urb->transfer_buffer));
2712
2713 if (usb_urb_dir_out(urb))
2714 memcpy(kmalloc_ptr, urb->transfer_buffer,
2715 urb->transfer_buffer_length);
2716 urb->transfer_buffer = kmalloc_ptr;
2717
2718 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2719
2720 return 0;
2721}
2722
2723static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2724 gfp_t mem_flags)
2725{
2726 int ret;
2727
2728
2729 WARN_ON_ONCE(urb->setup_dma &&
2730 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2731
2732 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2733 if (ret)
2734 return ret;
2735
2736 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2737 if (ret)
2738 dwc2_free_dma_aligned_buffer(urb);
2739
2740 return ret;
2741}
2742
2743static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2744{
2745 usb_hcd_unmap_urb_for_dma(hcd, urb);
2746 dwc2_free_dma_aligned_buffer(urb);
2747}
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2759{
2760 struct dwc2_host_chan *chan;
2761 struct dwc2_hcd_urb *urb;
2762 struct dwc2_qtd *qtd;
2763
2764 if (dbg_qh(qh))
2765 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2766
2767 if (list_empty(&qh->qtd_list)) {
2768 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2769 return -ENOMEM;
2770 }
2771
2772 if (list_empty(&hsotg->free_hc_list)) {
2773 dev_dbg(hsotg->dev, "No free channel to assign\n");
2774 return -ENOMEM;
2775 }
2776
2777 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2778 hc_list_entry);
2779
2780
2781 list_del_init(&chan->hc_list_entry);
2782
2783 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2784 urb = qtd->urb;
2785 qh->channel = chan;
2786 qtd->in_process = 1;
2787
2788
2789
2790
2791
2792 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2793 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2794 chan->speed = qh->dev_speed;
2795 chan->max_packet = dwc2_max_packet(qh->maxp);
2796
2797 chan->xfer_started = 0;
2798 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2799 chan->error_state = (qtd->error_count > 0);
2800 chan->halt_on_queue = 0;
2801 chan->halt_pending = 0;
2802 chan->requests = 0;
2803
2804
2805
2806
2807
2808
2809
2810
2811 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2812 if (chan->ep_is_in)
2813 chan->do_ping = 0;
2814 else
2815 chan->do_ping = qh->ping_state;
2816
2817 chan->data_pid_start = qh->data_toggle;
2818 chan->multi_count = 1;
2819
2820 if (urb->actual_length > urb->length &&
2821 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2822 urb->actual_length = urb->length;
2823
2824 if (hsotg->params.host_dma)
2825 chan->xfer_dma = urb->dma + urb->actual_length;
2826 else
2827 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2828
2829 chan->xfer_len = urb->length - urb->actual_length;
2830 chan->xfer_count = 0;
2831
2832
2833 if (qh->do_split)
2834 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2835 else
2836 chan->do_split = 0;
2837
2838
2839 dwc2_hc_init_xfer(hsotg, chan, qtd);
2840
2841
2842 if (hsotg->params.host_dma && qh->do_split &&
2843 chan->ep_is_in && (chan->xfer_dma & 0x3)) {
2844 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
2845 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) {
2846 dev_err(hsotg->dev,
2847 "Failed to allocate memory to handle non-aligned buffer\n");
2848
2849 chan->align_buf = 0;
2850 chan->multi_count = 0;
2851 list_add_tail(&chan->hc_list_entry,
2852 &hsotg->free_hc_list);
2853 qtd->in_process = 0;
2854 qh->channel = NULL;
2855 return -ENOMEM;
2856 }
2857 } else {
2858
2859
2860
2861
2862 WARN_ON_ONCE(hsotg->params.host_dma &&
2863 (chan->xfer_dma & 0x3));
2864 chan->align_buf = 0;
2865 }
2866
2867 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2868 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2869
2870
2871
2872
2873 chan->multi_count = dwc2_hb_mult(qh->maxp);
2874
2875 if (hsotg->params.dma_desc_enable) {
2876 chan->desc_list_addr = qh->desc_list_dma;
2877 chan->desc_list_sz = qh->desc_list_sz;
2878 }
2879
2880 dwc2_hc_init(hsotg, chan);
2881 chan->qh = qh;
2882
2883 return 0;
2884}
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895enum dwc2_transaction_type dwc2_hcd_select_transactions(
2896 struct dwc2_hsotg *hsotg)
2897{
2898 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2899 struct list_head *qh_ptr;
2900 struct dwc2_qh *qh;
2901 int num_channels;
2902
2903#ifdef DWC2_DEBUG_SOF
2904 dev_vdbg(hsotg->dev, " Select Transactions\n");
2905#endif
2906
2907
2908 qh_ptr = hsotg->periodic_sched_ready.next;
2909 while (qh_ptr != &hsotg->periodic_sched_ready) {
2910 if (list_empty(&hsotg->free_hc_list))
2911 break;
2912 if (hsotg->params.uframe_sched) {
2913 if (hsotg->available_host_channels <= 1)
2914 break;
2915 hsotg->available_host_channels--;
2916 }
2917 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2918 if (dwc2_assign_and_init_hc(hsotg, qh))
2919 break;
2920
2921
2922
2923
2924
2925 qh_ptr = qh_ptr->next;
2926 list_move_tail(&qh->qh_list_entry,
2927 &hsotg->periodic_sched_assigned);
2928 ret_val = DWC2_TRANSACTION_PERIODIC;
2929 }
2930
2931
2932
2933
2934
2935
2936 num_channels = hsotg->params.host_channels;
2937 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2938 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2939 if (!hsotg->params.uframe_sched &&
2940 hsotg->non_periodic_channels >= num_channels -
2941 hsotg->periodic_channels)
2942 break;
2943 if (list_empty(&hsotg->free_hc_list))
2944 break;
2945 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2946 if (hsotg->params.uframe_sched) {
2947 if (hsotg->available_host_channels < 1)
2948 break;
2949 hsotg->available_host_channels--;
2950 }
2951
2952 if (dwc2_assign_and_init_hc(hsotg, qh))
2953 break;
2954
2955
2956
2957
2958
2959 qh_ptr = qh_ptr->next;
2960 list_move_tail(&qh->qh_list_entry,
2961 &hsotg->non_periodic_sched_active);
2962
2963 if (ret_val == DWC2_TRANSACTION_NONE)
2964 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2965 else
2966 ret_val = DWC2_TRANSACTION_ALL;
2967
2968 if (!hsotg->params.uframe_sched)
2969 hsotg->non_periodic_channels++;
2970 }
2971
2972 return ret_val;
2973}
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2997 struct dwc2_host_chan *chan,
2998 u16 fifo_dwords_avail)
2999{
3000 int retval = 0;
3001
3002 if (chan->do_split)
3003
3004 list_move_tail(&chan->split_order_list_entry,
3005 &hsotg->split_order);
3006
3007 if (hsotg->params.host_dma) {
3008 if (hsotg->params.dma_desc_enable) {
3009 if (!chan->xfer_started ||
3010 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
3011 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
3012 chan->qh->ping_state = 0;
3013 }
3014 } else if (!chan->xfer_started) {
3015 dwc2_hc_start_transfer(hsotg, chan);
3016 chan->qh->ping_state = 0;
3017 }
3018 } else if (chan->halt_pending) {
3019
3020 } else if (chan->halt_on_queue) {
3021 dwc2_hc_halt(hsotg, chan, chan->halt_status);
3022 } else if (chan->do_ping) {
3023 if (!chan->xfer_started)
3024 dwc2_hc_start_transfer(hsotg, chan);
3025 } else if (!chan->ep_is_in ||
3026 chan->data_pid_start == DWC2_HC_PID_SETUP) {
3027 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
3028 if (!chan->xfer_started) {
3029 dwc2_hc_start_transfer(hsotg, chan);
3030 retval = 1;
3031 } else {
3032 retval = dwc2_hc_continue_transfer(hsotg, chan);
3033 }
3034 } else {
3035 retval = -1;
3036 }
3037 } else {
3038 if (!chan->xfer_started) {
3039 dwc2_hc_start_transfer(hsotg, chan);
3040 retval = 1;
3041 } else {
3042 retval = dwc2_hc_continue_transfer(hsotg, chan);
3043 }
3044 }
3045
3046 return retval;
3047}
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
3059{
3060 struct list_head *qh_ptr;
3061 struct dwc2_qh *qh;
3062 u32 tx_status;
3063 u32 fspcavail;
3064 u32 gintmsk;
3065 int status;
3066 bool no_queue_space = false;
3067 bool no_fifo_space = false;
3068 u32 qspcavail;
3069
3070
3071 if (list_empty(&hsotg->periodic_sched_assigned))
3072 goto exit;
3073
3074 if (dbg_perio())
3075 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
3076
3077 tx_status = dwc2_readl(hsotg, HPTXSTS);
3078 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3079 TXSTS_QSPCAVAIL_SHIFT;
3080 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3081 TXSTS_FSPCAVAIL_SHIFT;
3082
3083 if (dbg_perio()) {
3084 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
3085 qspcavail);
3086 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
3087 fspcavail);
3088 }
3089
3090 qh_ptr = hsotg->periodic_sched_assigned.next;
3091 while (qh_ptr != &hsotg->periodic_sched_assigned) {
3092 tx_status = dwc2_readl(hsotg, HPTXSTS);
3093 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3094 TXSTS_QSPCAVAIL_SHIFT;
3095 if (qspcavail == 0) {
3096 no_queue_space = true;
3097 break;
3098 }
3099
3100 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
3101 if (!qh->channel) {
3102 qh_ptr = qh_ptr->next;
3103 continue;
3104 }
3105
3106
3107 if (qh->tt_buffer_dirty) {
3108 qh_ptr = qh_ptr->next;
3109 continue;
3110 }
3111
3112
3113
3114
3115
3116
3117 if (!hsotg->params.host_dma &&
3118 qh->channel->multi_count > 1)
3119 hsotg->queuing_high_bandwidth = 1;
3120
3121 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3122 TXSTS_FSPCAVAIL_SHIFT;
3123 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3124 if (status < 0) {
3125 no_fifo_space = true;
3126 break;
3127 }
3128
3129
3130
3131
3132
3133
3134
3135
3136 if (hsotg->params.host_dma || status == 0 ||
3137 qh->channel->requests == qh->channel->multi_count) {
3138 qh_ptr = qh_ptr->next;
3139
3140
3141
3142
3143 list_move_tail(&qh->qh_list_entry,
3144 &hsotg->periodic_sched_queued);
3145
3146
3147 hsotg->queuing_high_bandwidth = 0;
3148 }
3149 }
3150
3151exit:
3152 if (no_queue_space || no_fifo_space ||
3153 (!hsotg->params.host_dma &&
3154 !list_empty(&hsotg->periodic_sched_assigned))) {
3155
3156
3157
3158
3159
3160
3161
3162 gintmsk = dwc2_readl(hsotg, GINTMSK);
3163 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3164 gintmsk |= GINTSTS_PTXFEMP;
3165 dwc2_writel(hsotg, gintmsk, GINTMSK);
3166 }
3167 } else {
3168
3169
3170
3171
3172
3173
3174
3175 gintmsk = dwc2_readl(hsotg, GINTMSK);
3176 if (gintmsk & GINTSTS_PTXFEMP) {
3177 gintmsk &= ~GINTSTS_PTXFEMP;
3178 dwc2_writel(hsotg, gintmsk, GINTMSK);
3179 }
3180 }
3181}
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3193{
3194 struct list_head *orig_qh_ptr;
3195 struct dwc2_qh *qh;
3196 u32 tx_status;
3197 u32 qspcavail;
3198 u32 fspcavail;
3199 u32 gintmsk;
3200 int status;
3201 int no_queue_space = 0;
3202 int no_fifo_space = 0;
3203 int more_to_do = 0;
3204
3205 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3206
3207 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3208 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3209 TXSTS_QSPCAVAIL_SHIFT;
3210 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3211 TXSTS_FSPCAVAIL_SHIFT;
3212 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3213 qspcavail);
3214 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3215 fspcavail);
3216
3217
3218
3219
3220
3221 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3222 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3223 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3224
3225
3226
3227
3228
3229 do {
3230 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3231 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3232 TXSTS_QSPCAVAIL_SHIFT;
3233 if (!hsotg->params.host_dma && qspcavail == 0) {
3234 no_queue_space = 1;
3235 break;
3236 }
3237
3238 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3239 qh_list_entry);
3240 if (!qh->channel)
3241 goto next;
3242
3243
3244 if (qh->tt_buffer_dirty)
3245 goto next;
3246
3247 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3248 TXSTS_FSPCAVAIL_SHIFT;
3249 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3250
3251 if (status > 0) {
3252 more_to_do = 1;
3253 } else if (status < 0) {
3254 no_fifo_space = 1;
3255 break;
3256 }
3257next:
3258
3259 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3260 if (hsotg->non_periodic_qh_ptr ==
3261 &hsotg->non_periodic_sched_active)
3262 hsotg->non_periodic_qh_ptr =
3263 hsotg->non_periodic_qh_ptr->next;
3264 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3265
3266 if (!hsotg->params.host_dma) {
3267 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3268 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3269 TXSTS_QSPCAVAIL_SHIFT;
3270 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3271 TXSTS_FSPCAVAIL_SHIFT;
3272 dev_vdbg(hsotg->dev,
3273 " NP Tx Req Queue Space Avail (after queue): %d\n",
3274 qspcavail);
3275 dev_vdbg(hsotg->dev,
3276 " NP Tx FIFO Space Avail (after queue): %d\n",
3277 fspcavail);
3278
3279 if (more_to_do || no_queue_space || no_fifo_space) {
3280
3281
3282
3283
3284
3285
3286
3287 gintmsk = dwc2_readl(hsotg, GINTMSK);
3288 gintmsk |= GINTSTS_NPTXFEMP;
3289 dwc2_writel(hsotg, gintmsk, GINTMSK);
3290 } else {
3291
3292
3293
3294
3295
3296
3297
3298 gintmsk = dwc2_readl(hsotg, GINTMSK);
3299 gintmsk &= ~GINTSTS_NPTXFEMP;
3300 dwc2_writel(hsotg, gintmsk, GINTMSK);
3301 }
3302 }
3303}
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3317 enum dwc2_transaction_type tr_type)
3318{
3319#ifdef DWC2_DEBUG_SOF
3320 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3321#endif
3322
3323 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3324 tr_type == DWC2_TRANSACTION_ALL)
3325 dwc2_process_periodic_channels(hsotg);
3326
3327
3328 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3329 tr_type == DWC2_TRANSACTION_ALL) {
3330 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3331 dwc2_process_non_periodic_channels(hsotg);
3332 } else {
3333
3334
3335
3336
3337 u32 gintmsk = dwc2_readl(hsotg, GINTMSK);
3338
3339 gintmsk &= ~GINTSTS_NPTXFEMP;
3340 dwc2_writel(hsotg, gintmsk, GINTMSK);
3341 }
3342 }
3343}
3344
3345static void dwc2_conn_id_status_change(struct work_struct *work)
3346{
3347 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3348 wf_otg);
3349 u32 count = 0;
3350 u32 gotgctl;
3351 unsigned long flags;
3352
3353 dev_dbg(hsotg->dev, "%s()\n", __func__);
3354
3355 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3356 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3357 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3358 !!(gotgctl & GOTGCTL_CONID_B));
3359
3360
3361 if (gotgctl & GOTGCTL_CONID_B) {
3362 dwc2_vbus_supply_exit(hsotg);
3363
3364 dev_dbg(hsotg->dev, "connId B\n");
3365 if (hsotg->bus_suspended) {
3366 dev_info(hsotg->dev,
3367 "Do port resume before switching to device mode\n");
3368 dwc2_port_resume(hsotg);
3369 }
3370 while (!dwc2_is_device_mode(hsotg)) {
3371 dev_info(hsotg->dev,
3372 "Waiting for Peripheral Mode, Mode=%s\n",
3373 dwc2_is_host_mode(hsotg) ? "Host" :
3374 "Peripheral");
3375 msleep(20);
3376
3377
3378
3379
3380
3381 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3382 if (!(gotgctl & GOTGCTL_CONID_B))
3383 goto host;
3384 if (++count > 250)
3385 break;
3386 }
3387 if (count > 250)
3388 dev_err(hsotg->dev,
3389 "Connection id status change timed out\n");
3390 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3391 dwc2_core_init(hsotg, false);
3392 dwc2_enable_global_interrupts(hsotg);
3393 spin_lock_irqsave(&hsotg->lock, flags);
3394 dwc2_hsotg_core_init_disconnected(hsotg, false);
3395 spin_unlock_irqrestore(&hsotg->lock, flags);
3396
3397 dwc2_enable_acg(hsotg);
3398 dwc2_hsotg_core_connect(hsotg);
3399 } else {
3400host:
3401
3402 dev_dbg(hsotg->dev, "connId A\n");
3403 while (!dwc2_is_host_mode(hsotg)) {
3404 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3405 dwc2_is_host_mode(hsotg) ?
3406 "Host" : "Peripheral");
3407 msleep(20);
3408 if (++count > 250)
3409 break;
3410 }
3411 if (count > 250)
3412 dev_err(hsotg->dev,
3413 "Connection id status change timed out\n");
3414
3415 spin_lock_irqsave(&hsotg->lock, flags);
3416 dwc2_hsotg_disconnect(hsotg);
3417 spin_unlock_irqrestore(&hsotg->lock, flags);
3418
3419 hsotg->op_state = OTG_STATE_A_HOST;
3420
3421 dwc2_core_init(hsotg, false);
3422 dwc2_enable_global_interrupts(hsotg);
3423 dwc2_hcd_start(hsotg);
3424 }
3425}
3426
3427static void dwc2_wakeup_detected(struct timer_list *t)
3428{
3429 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3430 u32 hprt0;
3431
3432 dev_dbg(hsotg->dev, "%s()\n", __func__);
3433
3434
3435
3436
3437
3438 hprt0 = dwc2_read_hprt0(hsotg);
3439 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3440 hprt0 &= ~HPRT0_RES;
3441 dwc2_writel(hsotg, hprt0, HPRT0);
3442 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3443 dwc2_readl(hsotg, HPRT0));
3444
3445 dwc2_hcd_rem_wakeup(hsotg);
3446 hsotg->bus_suspended = false;
3447
3448
3449 hsotg->lx_state = DWC2_L0;
3450}
3451
3452static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3453{
3454 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3455
3456 return hcd->self.b_hnp_enable;
3457}
3458
3459
3460static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3461{
3462 unsigned long flags;
3463 u32 hprt0;
3464 u32 pcgctl;
3465 u32 gotgctl;
3466
3467 dev_dbg(hsotg->dev, "%s()\n", __func__);
3468
3469 spin_lock_irqsave(&hsotg->lock, flags);
3470
3471 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3472 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3473 gotgctl |= GOTGCTL_HSTSETHNPEN;
3474 dwc2_writel(hsotg, gotgctl, GOTGCTL);
3475 hsotg->op_state = OTG_STATE_A_SUSPEND;
3476 }
3477
3478 hprt0 = dwc2_read_hprt0(hsotg);
3479 hprt0 |= HPRT0_SUSP;
3480 dwc2_writel(hsotg, hprt0, HPRT0);
3481
3482 hsotg->bus_suspended = true;
3483
3484
3485
3486
3487
3488 if (!hsotg->params.power_down) {
3489
3490 pcgctl = dwc2_readl(hsotg, PCGCTL);
3491 pcgctl |= PCGCTL_STOPPCLK;
3492 dwc2_writel(hsotg, pcgctl, PCGCTL);
3493 udelay(10);
3494 }
3495
3496
3497 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3498 pcgctl = dwc2_readl(hsotg, PCGCTL);
3499 pcgctl &= ~PCGCTL_STOPPCLK;
3500 dwc2_writel(hsotg, pcgctl, PCGCTL);
3501
3502 spin_unlock_irqrestore(&hsotg->lock, flags);
3503
3504 msleep(200);
3505 } else {
3506 spin_unlock_irqrestore(&hsotg->lock, flags);
3507 }
3508}
3509
3510
3511static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3512{
3513 unsigned long flags;
3514 u32 hprt0;
3515 u32 pcgctl;
3516
3517 spin_lock_irqsave(&hsotg->lock, flags);
3518
3519
3520
3521
3522
3523 if (!hsotg->params.power_down) {
3524 pcgctl = dwc2_readl(hsotg, PCGCTL);
3525 pcgctl &= ~PCGCTL_STOPPCLK;
3526 dwc2_writel(hsotg, pcgctl, PCGCTL);
3527 spin_unlock_irqrestore(&hsotg->lock, flags);
3528 msleep(20);
3529 spin_lock_irqsave(&hsotg->lock, flags);
3530 }
3531
3532 hprt0 = dwc2_read_hprt0(hsotg);
3533 hprt0 |= HPRT0_RES;
3534 hprt0 &= ~HPRT0_SUSP;
3535 dwc2_writel(hsotg, hprt0, HPRT0);
3536 spin_unlock_irqrestore(&hsotg->lock, flags);
3537
3538 msleep(USB_RESUME_TIMEOUT);
3539
3540 spin_lock_irqsave(&hsotg->lock, flags);
3541 hprt0 = dwc2_read_hprt0(hsotg);
3542 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3543 dwc2_writel(hsotg, hprt0, HPRT0);
3544 hsotg->bus_suspended = false;
3545 spin_unlock_irqrestore(&hsotg->lock, flags);
3546}
3547
3548
3549static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3550 u16 wvalue, u16 windex, char *buf, u16 wlength)
3551{
3552 struct usb_hub_descriptor *hub_desc;
3553 int retval = 0;
3554 u32 hprt0;
3555 u32 port_status;
3556 u32 speed;
3557 u32 pcgctl;
3558 u32 pwr;
3559
3560 switch (typereq) {
3561 case ClearHubFeature:
3562 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3563
3564 switch (wvalue) {
3565 case C_HUB_LOCAL_POWER:
3566 case C_HUB_OVER_CURRENT:
3567
3568 break;
3569
3570 default:
3571 retval = -EINVAL;
3572 dev_err(hsotg->dev,
3573 "ClearHubFeature request %1xh unknown\n",
3574 wvalue);
3575 }
3576 break;
3577
3578 case ClearPortFeature:
3579 if (wvalue != USB_PORT_FEAT_L1)
3580 if (!windex || windex > 1)
3581 goto error;
3582 switch (wvalue) {
3583 case USB_PORT_FEAT_ENABLE:
3584 dev_dbg(hsotg->dev,
3585 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3586 hprt0 = dwc2_read_hprt0(hsotg);
3587 hprt0 |= HPRT0_ENA;
3588 dwc2_writel(hsotg, hprt0, HPRT0);
3589 break;
3590
3591 case USB_PORT_FEAT_SUSPEND:
3592 dev_dbg(hsotg->dev,
3593 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3594
3595 if (hsotg->bus_suspended) {
3596 if (hsotg->hibernated)
3597 dwc2_exit_hibernation(hsotg, 0, 0, 1);
3598 else
3599 dwc2_port_resume(hsotg);
3600 }
3601 break;
3602
3603 case USB_PORT_FEAT_POWER:
3604 dev_dbg(hsotg->dev,
3605 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3606 hprt0 = dwc2_read_hprt0(hsotg);
3607 pwr = hprt0 & HPRT0_PWR;
3608 hprt0 &= ~HPRT0_PWR;
3609 dwc2_writel(hsotg, hprt0, HPRT0);
3610 if (pwr)
3611 dwc2_vbus_supply_exit(hsotg);
3612 break;
3613
3614 case USB_PORT_FEAT_INDICATOR:
3615 dev_dbg(hsotg->dev,
3616 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3617
3618 break;
3619
3620 case USB_PORT_FEAT_C_CONNECTION:
3621
3622
3623
3624 dev_dbg(hsotg->dev,
3625 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3626 hsotg->flags.b.port_connect_status_change = 0;
3627 break;
3628
3629 case USB_PORT_FEAT_C_RESET:
3630
3631 dev_dbg(hsotg->dev,
3632 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3633 hsotg->flags.b.port_reset_change = 0;
3634 break;
3635
3636 case USB_PORT_FEAT_C_ENABLE:
3637
3638
3639
3640
3641 dev_dbg(hsotg->dev,
3642 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3643 hsotg->flags.b.port_enable_change = 0;
3644 break;
3645
3646 case USB_PORT_FEAT_C_SUSPEND:
3647
3648
3649
3650
3651
3652 dev_dbg(hsotg->dev,
3653 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3654 hsotg->flags.b.port_suspend_change = 0;
3655 break;
3656
3657 case USB_PORT_FEAT_C_PORT_L1:
3658 dev_dbg(hsotg->dev,
3659 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3660 hsotg->flags.b.port_l1_change = 0;
3661 break;
3662
3663 case USB_PORT_FEAT_C_OVER_CURRENT:
3664 dev_dbg(hsotg->dev,
3665 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3666 hsotg->flags.b.port_over_current_change = 0;
3667 break;
3668
3669 default:
3670 retval = -EINVAL;
3671 dev_err(hsotg->dev,
3672 "ClearPortFeature request %1xh unknown or unsupported\n",
3673 wvalue);
3674 }
3675 break;
3676
3677 case GetHubDescriptor:
3678 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3679 hub_desc = (struct usb_hub_descriptor *)buf;
3680 hub_desc->bDescLength = 9;
3681 hub_desc->bDescriptorType = USB_DT_HUB;
3682 hub_desc->bNbrPorts = 1;
3683 hub_desc->wHubCharacteristics =
3684 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3685 HUB_CHAR_INDV_PORT_OCPM);
3686 hub_desc->bPwrOn2PwrGood = 1;
3687 hub_desc->bHubContrCurrent = 0;
3688 hub_desc->u.hs.DeviceRemovable[0] = 0;
3689 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3690 break;
3691
3692 case GetHubStatus:
3693 dev_dbg(hsotg->dev, "GetHubStatus\n");
3694 memset(buf, 0, 4);
3695 break;
3696
3697 case GetPortStatus:
3698 dev_vdbg(hsotg->dev,
3699 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3700 hsotg->flags.d32);
3701 if (!windex || windex > 1)
3702 goto error;
3703
3704 port_status = 0;
3705 if (hsotg->flags.b.port_connect_status_change)
3706 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3707 if (hsotg->flags.b.port_enable_change)
3708 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3709 if (hsotg->flags.b.port_suspend_change)
3710 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3711 if (hsotg->flags.b.port_l1_change)
3712 port_status |= USB_PORT_STAT_C_L1 << 16;
3713 if (hsotg->flags.b.port_reset_change)
3714 port_status |= USB_PORT_STAT_C_RESET << 16;
3715 if (hsotg->flags.b.port_over_current_change) {
3716 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3717 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3718 }
3719
3720 if (!hsotg->flags.b.port_connect_status) {
3721
3722
3723
3724
3725
3726
3727
3728 *(__le32 *)buf = cpu_to_le32(port_status);
3729 break;
3730 }
3731
3732 hprt0 = dwc2_readl(hsotg, HPRT0);
3733 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3734
3735 if (hprt0 & HPRT0_CONNSTS)
3736 port_status |= USB_PORT_STAT_CONNECTION;
3737 if (hprt0 & HPRT0_ENA)
3738 port_status |= USB_PORT_STAT_ENABLE;
3739 if (hprt0 & HPRT0_SUSP)
3740 port_status |= USB_PORT_STAT_SUSPEND;
3741 if (hprt0 & HPRT0_OVRCURRACT)
3742 port_status |= USB_PORT_STAT_OVERCURRENT;
3743 if (hprt0 & HPRT0_RST)
3744 port_status |= USB_PORT_STAT_RESET;
3745 if (hprt0 & HPRT0_PWR)
3746 port_status |= USB_PORT_STAT_POWER;
3747
3748 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3749 if (speed == HPRT0_SPD_HIGH_SPEED)
3750 port_status |= USB_PORT_STAT_HIGH_SPEED;
3751 else if (speed == HPRT0_SPD_LOW_SPEED)
3752 port_status |= USB_PORT_STAT_LOW_SPEED;
3753
3754 if (hprt0 & HPRT0_TSTCTL_MASK)
3755 port_status |= USB_PORT_STAT_TEST;
3756
3757
3758 if (hsotg->params.dma_desc_fs_enable) {
3759
3760
3761
3762
3763 if (hsotg->new_connection &&
3764 ((port_status &
3765 (USB_PORT_STAT_CONNECTION |
3766 USB_PORT_STAT_HIGH_SPEED |
3767 USB_PORT_STAT_LOW_SPEED)) ==
3768 USB_PORT_STAT_CONNECTION)) {
3769 u32 hcfg;
3770
3771 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3772 hsotg->params.dma_desc_enable = true;
3773 hcfg = dwc2_readl(hsotg, HCFG);
3774 hcfg |= HCFG_DESCDMA;
3775 dwc2_writel(hsotg, hcfg, HCFG);
3776 hsotg->new_connection = false;
3777 }
3778 }
3779
3780 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3781 *(__le32 *)buf = cpu_to_le32(port_status);
3782 break;
3783
3784 case SetHubFeature:
3785 dev_dbg(hsotg->dev, "SetHubFeature\n");
3786
3787 break;
3788
3789 case SetPortFeature:
3790 dev_dbg(hsotg->dev, "SetPortFeature\n");
3791 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3792 goto error;
3793
3794 if (!hsotg->flags.b.port_connect_status) {
3795
3796
3797
3798
3799
3800
3801
3802 break;
3803 }
3804
3805 switch (wvalue) {
3806 case USB_PORT_FEAT_SUSPEND:
3807 dev_dbg(hsotg->dev,
3808 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3809 if (windex != hsotg->otg_port)
3810 goto error;
3811 if (hsotg->params.power_down == 2)
3812 dwc2_enter_hibernation(hsotg, 1);
3813 else
3814 dwc2_port_suspend(hsotg, windex);
3815 break;
3816
3817 case USB_PORT_FEAT_POWER:
3818 dev_dbg(hsotg->dev,
3819 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3820 hprt0 = dwc2_read_hprt0(hsotg);
3821 pwr = hprt0 & HPRT0_PWR;
3822 hprt0 |= HPRT0_PWR;
3823 dwc2_writel(hsotg, hprt0, HPRT0);
3824 if (!pwr)
3825 dwc2_vbus_supply_init(hsotg);
3826 break;
3827
3828 case USB_PORT_FEAT_RESET:
3829 if (hsotg->params.power_down == 2 &&
3830 hsotg->hibernated)
3831 dwc2_exit_hibernation(hsotg, 0, 1, 1);
3832 hprt0 = dwc2_read_hprt0(hsotg);
3833 dev_dbg(hsotg->dev,
3834 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3835 pcgctl = dwc2_readl(hsotg, PCGCTL);
3836 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3837 dwc2_writel(hsotg, pcgctl, PCGCTL);
3838
3839 dwc2_writel(hsotg, 0, PCGCTL);
3840
3841 hprt0 = dwc2_read_hprt0(hsotg);
3842 pwr = hprt0 & HPRT0_PWR;
3843
3844 hprt0 &= ~HPRT0_SUSP;
3845
3846
3847
3848
3849
3850
3851 if (!dwc2_hcd_is_b_host(hsotg)) {
3852 hprt0 |= HPRT0_PWR | HPRT0_RST;
3853 dev_dbg(hsotg->dev,
3854 "In host mode, hprt0=%08x\n", hprt0);
3855 dwc2_writel(hsotg, hprt0, HPRT0);
3856 if (!pwr)
3857 dwc2_vbus_supply_init(hsotg);
3858 }
3859
3860
3861 msleep(50);
3862 hprt0 &= ~HPRT0_RST;
3863 dwc2_writel(hsotg, hprt0, HPRT0);
3864 hsotg->lx_state = DWC2_L0;
3865 break;
3866
3867 case USB_PORT_FEAT_INDICATOR:
3868 dev_dbg(hsotg->dev,
3869 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3870
3871 break;
3872
3873 case USB_PORT_FEAT_TEST:
3874 hprt0 = dwc2_read_hprt0(hsotg);
3875 dev_dbg(hsotg->dev,
3876 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3877 hprt0 &= ~HPRT0_TSTCTL_MASK;
3878 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3879 dwc2_writel(hsotg, hprt0, HPRT0);
3880 break;
3881
3882 default:
3883 retval = -EINVAL;
3884 dev_err(hsotg->dev,
3885 "SetPortFeature %1xh unknown or unsupported\n",
3886 wvalue);
3887 break;
3888 }
3889 break;
3890
3891 default:
3892error:
3893 retval = -EINVAL;
3894 dev_dbg(hsotg->dev,
3895 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3896 typereq, windex, wvalue);
3897 break;
3898 }
3899
3900 return retval;
3901}
3902
3903static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3904{
3905 int retval;
3906
3907 if (port != 1)
3908 return -EINVAL;
3909
3910 retval = (hsotg->flags.b.port_connect_status_change ||
3911 hsotg->flags.b.port_reset_change ||
3912 hsotg->flags.b.port_enable_change ||
3913 hsotg->flags.b.port_suspend_change ||
3914 hsotg->flags.b.port_over_current_change);
3915
3916 if (retval) {
3917 dev_dbg(hsotg->dev,
3918 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3919 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3920 hsotg->flags.b.port_connect_status_change);
3921 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3922 hsotg->flags.b.port_reset_change);
3923 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3924 hsotg->flags.b.port_enable_change);
3925 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3926 hsotg->flags.b.port_suspend_change);
3927 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3928 hsotg->flags.b.port_over_current_change);
3929 }
3930
3931 return retval;
3932}
3933
3934int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3935{
3936 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3937
3938#ifdef DWC2_DEBUG_SOF
3939 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3940 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3941#endif
3942 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3943}
3944
3945int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3946{
3947 u32 hprt = dwc2_readl(hsotg, HPRT0);
3948 u32 hfir = dwc2_readl(hsotg, HFIR);
3949 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3950 unsigned int us_per_frame;
3951 unsigned int frame_number;
3952 unsigned int remaining;
3953 unsigned int interval;
3954 unsigned int phy_clks;
3955
3956
3957 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3958
3959
3960 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3961 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3962 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3963
3964
3965
3966
3967
3968 phy_clks = (interval - remaining) +
3969 DIV_ROUND_UP(interval * us, us_per_frame);
3970
3971 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3972}
3973
3974int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3975{
3976 return hsotg->op_state == OTG_STATE_B_HOST;
3977}
3978
3979static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3980 int iso_desc_count,
3981 gfp_t mem_flags)
3982{
3983 struct dwc2_hcd_urb *urb;
3984 u32 size = sizeof(*urb) + iso_desc_count *
3985 sizeof(struct dwc2_hcd_iso_packet_desc);
3986
3987 urb = kzalloc(size, mem_flags);
3988 if (urb)
3989 urb->packet_count = iso_desc_count;
3990 return urb;
3991}
3992
3993static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3994 struct dwc2_hcd_urb *urb, u8 dev_addr,
3995 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3996{
3997 if (dbg_perio() ||
3998 ep_type == USB_ENDPOINT_XFER_BULK ||
3999 ep_type == USB_ENDPOINT_XFER_CONTROL)
4000 dev_vdbg(hsotg->dev,
4001 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
4002 dev_addr, ep_num, ep_dir, ep_type, mps);
4003 urb->pipe_info.dev_addr = dev_addr;
4004 urb->pipe_info.ep_num = ep_num;
4005 urb->pipe_info.pipe_type = ep_type;
4006 urb->pipe_info.pipe_dir = ep_dir;
4007 urb->pipe_info.mps = mps;
4008}
4009
4010
4011
4012
4013
4014void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
4015{
4016#ifdef DEBUG
4017 struct dwc2_host_chan *chan;
4018 struct dwc2_hcd_urb *urb;
4019 struct dwc2_qtd *qtd;
4020 int num_channels;
4021 u32 np_tx_status;
4022 u32 p_tx_status;
4023 int i;
4024
4025 num_channels = hsotg->params.host_channels;
4026 dev_dbg(hsotg->dev, "\n");
4027 dev_dbg(hsotg->dev,
4028 "************************************************************\n");
4029 dev_dbg(hsotg->dev, "HCD State:\n");
4030 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
4031
4032 for (i = 0; i < num_channels; i++) {
4033 chan = hsotg->hc_ptr_array[i];
4034 dev_dbg(hsotg->dev, " Channel %d:\n", i);
4035 dev_dbg(hsotg->dev,
4036 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
4037 chan->dev_addr, chan->ep_num, chan->ep_is_in);
4038 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
4039 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
4040 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
4041 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
4042 chan->data_pid_start);
4043 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
4044 dev_dbg(hsotg->dev, " xfer_started: %d\n",
4045 chan->xfer_started);
4046 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
4047 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
4048 (unsigned long)chan->xfer_dma);
4049 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
4050 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
4051 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
4052 chan->halt_on_queue);
4053 dev_dbg(hsotg->dev, " halt_pending: %d\n",
4054 chan->halt_pending);
4055 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
4056 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
4057 dev_dbg(hsotg->dev, " complete_split: %d\n",
4058 chan->complete_split);
4059 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
4060 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
4061 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
4062 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
4063 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
4064
4065 if (chan->xfer_started) {
4066 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
4067
4068 hfnum = dwc2_readl(hsotg, HFNUM);
4069 hcchar = dwc2_readl(hsotg, HCCHAR(i));
4070 hctsiz = dwc2_readl(hsotg, HCTSIZ(i));
4071 hcint = dwc2_readl(hsotg, HCINT(i));
4072 hcintmsk = dwc2_readl(hsotg, HCINTMSK(i));
4073 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
4074 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
4075 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
4076 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
4077 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
4078 }
4079
4080 if (!(chan->xfer_started && chan->qh))
4081 continue;
4082
4083 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
4084 if (!qtd->in_process)
4085 break;
4086 urb = qtd->urb;
4087 dev_dbg(hsotg->dev, " URB Info:\n");
4088 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
4089 qtd, urb);
4090 if (urb) {
4091 dev_dbg(hsotg->dev,
4092 " Dev: %d, EP: %d %s\n",
4093 dwc2_hcd_get_dev_addr(&urb->pipe_info),
4094 dwc2_hcd_get_ep_num(&urb->pipe_info),
4095 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
4096 "IN" : "OUT");
4097 dev_dbg(hsotg->dev,
4098 " Max packet size: %d\n",
4099 dwc2_hcd_get_mps(&urb->pipe_info));
4100 dev_dbg(hsotg->dev,
4101 " transfer_buffer: %p\n",
4102 urb->buf);
4103 dev_dbg(hsotg->dev,
4104 " transfer_dma: %08lx\n",
4105 (unsigned long)urb->dma);
4106 dev_dbg(hsotg->dev,
4107 " transfer_buffer_length: %d\n",
4108 urb->length);
4109 dev_dbg(hsotg->dev, " actual_length: %d\n",
4110 urb->actual_length);
4111 }
4112 }
4113 }
4114
4115 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
4116 hsotg->non_periodic_channels);
4117 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
4118 hsotg->periodic_channels);
4119 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
4120 np_tx_status = dwc2_readl(hsotg, GNPTXSTS);
4121 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
4122 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4123 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
4124 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4125 p_tx_status = dwc2_readl(hsotg, HPTXSTS);
4126 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
4127 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4128 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
4129 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4130 dwc2_dump_global_registers(hsotg);
4131 dwc2_dump_host_registers(hsotg);
4132 dev_dbg(hsotg->dev,
4133 "************************************************************\n");
4134 dev_dbg(hsotg->dev, "\n");
4135#endif
4136}
4137
4138struct wrapper_priv_data {
4139 struct dwc2_hsotg *hsotg;
4140};
4141
4142
4143static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4144{
4145 struct wrapper_priv_data *p;
4146
4147 p = (struct wrapper_priv_data *)&hcd->hcd_priv;
4148 return p->hsotg;
4149}
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4172 gfp_t mem_flags, int *ttport)
4173{
4174 struct urb *urb = context;
4175 struct dwc2_tt *dwc_tt = NULL;
4176
4177 if (urb->dev->tt) {
4178 *ttport = urb->dev->ttport;
4179
4180 dwc_tt = urb->dev->tt->hcpriv;
4181 if (!dwc_tt) {
4182 size_t bitmap_size;
4183
4184
4185
4186
4187
4188 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4189 sizeof(dwc_tt->periodic_bitmaps[0]);
4190 if (urb->dev->tt->multi)
4191 bitmap_size *= urb->dev->tt->hub->maxchild;
4192
4193 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4194 mem_flags);
4195 if (!dwc_tt)
4196 return NULL;
4197
4198 dwc_tt->usb_tt = urb->dev->tt;
4199 dwc_tt->usb_tt->hcpriv = dwc_tt;
4200 }
4201
4202 dwc_tt->refcount++;
4203 }
4204
4205 return dwc_tt;
4206}
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4220{
4221
4222 if (!dwc_tt)
4223 return;
4224
4225 WARN_ON(dwc_tt->refcount < 1);
4226
4227 dwc_tt->refcount--;
4228 if (!dwc_tt->refcount) {
4229 dwc_tt->usb_tt->hcpriv = NULL;
4230 kfree(dwc_tt);
4231 }
4232}
4233
4234int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4235{
4236 struct urb *urb = context;
4237
4238 return urb->dev->speed;
4239}
4240
4241static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4242 struct urb *urb)
4243{
4244 struct usb_bus *bus = hcd_to_bus(hcd);
4245
4246 if (urb->interval)
4247 bus->bandwidth_allocated += bw / urb->interval;
4248 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4249 bus->bandwidth_isoc_reqs++;
4250 else
4251 bus->bandwidth_int_reqs++;
4252}
4253
4254static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4255 struct urb *urb)
4256{
4257 struct usb_bus *bus = hcd_to_bus(hcd);
4258
4259 if (urb->interval)
4260 bus->bandwidth_allocated -= bw / urb->interval;
4261 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4262 bus->bandwidth_isoc_reqs--;
4263 else
4264 bus->bandwidth_int_reqs--;
4265}
4266
4267
4268
4269
4270
4271
4272
4273void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4274 int status)
4275{
4276 struct urb *urb;
4277 int i;
4278
4279 if (!qtd) {
4280 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4281 return;
4282 }
4283
4284 if (!qtd->urb) {
4285 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4286 return;
4287 }
4288
4289 urb = qtd->urb->priv;
4290 if (!urb) {
4291 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4292 return;
4293 }
4294
4295 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4296
4297 if (dbg_urb(urb))
4298 dev_vdbg(hsotg->dev,
4299 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4300 __func__, urb, usb_pipedevice(urb->pipe),
4301 usb_pipeendpoint(urb->pipe),
4302 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4303 urb->actual_length);
4304
4305 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4306 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4307 for (i = 0; i < urb->number_of_packets; ++i) {
4308 urb->iso_frame_desc[i].actual_length =
4309 dwc2_hcd_urb_get_iso_desc_actual_length(
4310 qtd->urb, i);
4311 urb->iso_frame_desc[i].status =
4312 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4313 }
4314 }
4315
4316 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4317 for (i = 0; i < urb->number_of_packets; i++)
4318 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4319 i, urb->iso_frame_desc[i].status);
4320 }
4321
4322 urb->status = status;
4323 if (!status) {
4324 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4325 urb->actual_length < urb->transfer_buffer_length)
4326 urb->status = -EREMOTEIO;
4327 }
4328
4329 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4330 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4331 struct usb_host_endpoint *ep = urb->ep;
4332
4333 if (ep)
4334 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4335 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4336 urb);
4337 }
4338
4339 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4340 urb->hcpriv = NULL;
4341 kfree(qtd->urb);
4342 qtd->urb = NULL;
4343
4344 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4345}
4346
4347
4348
4349
4350static void dwc2_hcd_start_func(struct work_struct *work)
4351{
4352 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4353 start_work.work);
4354
4355 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4356 dwc2_host_start(hsotg);
4357}
4358
4359
4360
4361
4362static void dwc2_hcd_reset_func(struct work_struct *work)
4363{
4364 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4365 reset_work.work);
4366 unsigned long flags;
4367 u32 hprt0;
4368
4369 dev_dbg(hsotg->dev, "USB RESET function called\n");
4370
4371 spin_lock_irqsave(&hsotg->lock, flags);
4372
4373 hprt0 = dwc2_read_hprt0(hsotg);
4374 hprt0 &= ~HPRT0_RST;
4375 dwc2_writel(hsotg, hprt0, HPRT0);
4376 hsotg->flags.b.port_reset_change = 1;
4377
4378 spin_unlock_irqrestore(&hsotg->lock, flags);
4379}
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392static int _dwc2_hcd_start(struct usb_hcd *hcd)
4393{
4394 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4395 struct usb_bus *bus = hcd_to_bus(hcd);
4396 unsigned long flags;
4397 u32 hprt0;
4398 int ret;
4399
4400 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4401
4402 spin_lock_irqsave(&hsotg->lock, flags);
4403 hsotg->lx_state = DWC2_L0;
4404 hcd->state = HC_STATE_RUNNING;
4405 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4406
4407 if (dwc2_is_device_mode(hsotg)) {
4408 spin_unlock_irqrestore(&hsotg->lock, flags);
4409 return 0;
4410 }
4411
4412 dwc2_hcd_reinit(hsotg);
4413
4414 hprt0 = dwc2_read_hprt0(hsotg);
4415
4416 if (hprt0 & HPRT0_PWR) {
4417
4418 spin_unlock_irqrestore(&hsotg->lock, flags);
4419 ret = dwc2_vbus_supply_init(hsotg);
4420 if (ret)
4421 return ret;
4422 spin_lock_irqsave(&hsotg->lock, flags);
4423 }
4424
4425
4426 if (bus->root_hub) {
4427 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4428
4429 usb_hcd_resume_root_hub(hcd);
4430 }
4431
4432 spin_unlock_irqrestore(&hsotg->lock, flags);
4433
4434 return 0;
4435}
4436
4437
4438
4439
4440
4441static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4442{
4443 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4444 unsigned long flags;
4445 u32 hprt0;
4446
4447
4448 dwc2_disable_host_interrupts(hsotg);
4449
4450
4451 synchronize_irq(hcd->irq);
4452
4453 spin_lock_irqsave(&hsotg->lock, flags);
4454 hprt0 = dwc2_read_hprt0(hsotg);
4455
4456 dwc2_hcd_disconnect(hsotg, true);
4457 dwc2_hcd_stop(hsotg);
4458 hsotg->lx_state = DWC2_L3;
4459 hcd->state = HC_STATE_HALT;
4460 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4461 spin_unlock_irqrestore(&hsotg->lock, flags);
4462
4463
4464 if (hprt0 & HPRT0_PWR)
4465 dwc2_vbus_supply_exit(hsotg);
4466
4467 usleep_range(1000, 3000);
4468}
4469
4470static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4471{
4472 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4473 unsigned long flags;
4474 int ret = 0;
4475 u32 hprt0;
4476
4477 spin_lock_irqsave(&hsotg->lock, flags);
4478
4479 if (dwc2_is_device_mode(hsotg))
4480 goto unlock;
4481
4482 if (hsotg->lx_state != DWC2_L0)
4483 goto unlock;
4484
4485 if (!HCD_HW_ACCESSIBLE(hcd))
4486 goto unlock;
4487
4488 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4489 goto unlock;
4490
4491 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
4492 goto skip_power_saving;
4493
4494
4495
4496
4497
4498 if (!hsotg->bus_suspended) {
4499 hprt0 = dwc2_read_hprt0(hsotg);
4500 hprt0 |= HPRT0_SUSP;
4501 hprt0 &= ~HPRT0_PWR;
4502 dwc2_writel(hsotg, hprt0, HPRT0);
4503 spin_unlock_irqrestore(&hsotg->lock, flags);
4504 dwc2_vbus_supply_exit(hsotg);
4505 spin_lock_irqsave(&hsotg->lock, flags);
4506 }
4507
4508
4509 ret = dwc2_enter_partial_power_down(hsotg);
4510 if (ret) {
4511 if (ret != -ENOTSUPP)
4512 dev_err(hsotg->dev,
4513 "enter partial_power_down failed\n");
4514 goto skip_power_saving;
4515 }
4516
4517
4518 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4519 spin_unlock_irqrestore(&hsotg->lock, flags);
4520 usb_phy_set_suspend(hsotg->uphy, true);
4521 spin_lock_irqsave(&hsotg->lock, flags);
4522 }
4523
4524
4525 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4526
4527skip_power_saving:
4528 hsotg->lx_state = DWC2_L2;
4529unlock:
4530 spin_unlock_irqrestore(&hsotg->lock, flags);
4531
4532 return ret;
4533}
4534
4535static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4536{
4537 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4538 unsigned long flags;
4539 int ret = 0;
4540
4541 spin_lock_irqsave(&hsotg->lock, flags);
4542
4543 if (dwc2_is_device_mode(hsotg))
4544 goto unlock;
4545
4546 if (hsotg->lx_state != DWC2_L2)
4547 goto unlock;
4548
4549 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) {
4550 hsotg->lx_state = DWC2_L0;
4551 goto unlock;
4552 }
4553
4554
4555
4556
4557
4558 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4559
4560
4561
4562
4563
4564
4565 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4566 spin_unlock_irqrestore(&hsotg->lock, flags);
4567 usb_phy_set_suspend(hsotg->uphy, false);
4568 spin_lock_irqsave(&hsotg->lock, flags);
4569 }
4570
4571
4572 ret = dwc2_exit_partial_power_down(hsotg, true);
4573 if (ret && (ret != -ENOTSUPP))
4574 dev_err(hsotg->dev, "exit partial_power_down failed\n");
4575
4576 hsotg->lx_state = DWC2_L0;
4577
4578 spin_unlock_irqrestore(&hsotg->lock, flags);
4579
4580 if (hsotg->bus_suspended) {
4581 spin_lock_irqsave(&hsotg->lock, flags);
4582 hsotg->flags.b.port_suspend_change = 1;
4583 spin_unlock_irqrestore(&hsotg->lock, flags);
4584 dwc2_port_resume(hsotg);
4585 } else {
4586 dwc2_vbus_supply_init(hsotg);
4587
4588
4589 usleep_range(3000, 5000);
4590
4591
4592
4593
4594
4595 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
4596 HPRT0_ENACHG, HPRT0);
4597
4598 usleep_range(5000, 7000);
4599 }
4600
4601 return ret;
4602unlock:
4603 spin_unlock_irqrestore(&hsotg->lock, flags);
4604
4605 return ret;
4606}
4607
4608
4609static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4610{
4611 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4612
4613 return dwc2_hcd_get_frame_number(hsotg);
4614}
4615
4616static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4617 char *fn_name)
4618{
4619#ifdef VERBOSE_DEBUG
4620 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4621 char *pipetype = NULL;
4622 char *speed = NULL;
4623
4624 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4625 dev_vdbg(hsotg->dev, " Device address: %d\n",
4626 usb_pipedevice(urb->pipe));
4627 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4628 usb_pipeendpoint(urb->pipe),
4629 usb_pipein(urb->pipe) ? "IN" : "OUT");
4630
4631 switch (usb_pipetype(urb->pipe)) {
4632 case PIPE_CONTROL:
4633 pipetype = "CONTROL";
4634 break;
4635 case PIPE_BULK:
4636 pipetype = "BULK";
4637 break;
4638 case PIPE_INTERRUPT:
4639 pipetype = "INTERRUPT";
4640 break;
4641 case PIPE_ISOCHRONOUS:
4642 pipetype = "ISOCHRONOUS";
4643 break;
4644 }
4645
4646 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4647 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4648 "IN" : "OUT");
4649
4650 switch (urb->dev->speed) {
4651 case USB_SPEED_HIGH:
4652 speed = "HIGH";
4653 break;
4654 case USB_SPEED_FULL:
4655 speed = "FULL";
4656 break;
4657 case USB_SPEED_LOW:
4658 speed = "LOW";
4659 break;
4660 default:
4661 speed = "UNKNOWN";
4662 break;
4663 }
4664
4665 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4666 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
4667 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4668 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4669 urb->transfer_buffer_length);
4670 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4671 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4672 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4673 urb->setup_packet, (unsigned long)urb->setup_dma);
4674 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4675
4676 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4677 int i;
4678
4679 for (i = 0; i < urb->number_of_packets; i++) {
4680 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4681 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4682 urb->iso_frame_desc[i].offset,
4683 urb->iso_frame_desc[i].length);
4684 }
4685 }
4686#endif
4687}
4688
4689
4690
4691
4692
4693
4694static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4695 gfp_t mem_flags)
4696{
4697 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4698 struct usb_host_endpoint *ep = urb->ep;
4699 struct dwc2_hcd_urb *dwc2_urb;
4700 int i;
4701 int retval;
4702 int alloc_bandwidth = 0;
4703 u8 ep_type = 0;
4704 u32 tflags = 0;
4705 void *buf;
4706 unsigned long flags;
4707 struct dwc2_qh *qh;
4708 bool qh_allocated = false;
4709 struct dwc2_qtd *qtd;
4710
4711 if (dbg_urb(urb)) {
4712 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4713 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4714 }
4715
4716 if (!ep)
4717 return -EINVAL;
4718
4719 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4720 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4721 spin_lock_irqsave(&hsotg->lock, flags);
4722 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4723 alloc_bandwidth = 1;
4724 spin_unlock_irqrestore(&hsotg->lock, flags);
4725 }
4726
4727 switch (usb_pipetype(urb->pipe)) {
4728 case PIPE_CONTROL:
4729 ep_type = USB_ENDPOINT_XFER_CONTROL;
4730 break;
4731 case PIPE_ISOCHRONOUS:
4732 ep_type = USB_ENDPOINT_XFER_ISOC;
4733 break;
4734 case PIPE_BULK:
4735 ep_type = USB_ENDPOINT_XFER_BULK;
4736 break;
4737 case PIPE_INTERRUPT:
4738 ep_type = USB_ENDPOINT_XFER_INT;
4739 break;
4740 }
4741
4742 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4743 mem_flags);
4744 if (!dwc2_urb)
4745 return -ENOMEM;
4746
4747 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4748 usb_pipeendpoint(urb->pipe), ep_type,
4749 usb_pipein(urb->pipe),
4750 usb_maxpacket(urb->dev, urb->pipe,
4751 !(usb_pipein(urb->pipe))));
4752
4753 buf = urb->transfer_buffer;
4754
4755 if (hcd->self.uses_dma) {
4756 if (!buf && (urb->transfer_dma & 3)) {
4757 dev_err(hsotg->dev,
4758 "%s: unaligned transfer with no transfer_buffer",
4759 __func__);
4760 retval = -EINVAL;
4761 goto fail0;
4762 }
4763 }
4764
4765 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4766 tflags |= URB_GIVEBACK_ASAP;
4767 if (urb->transfer_flags & URB_ZERO_PACKET)
4768 tflags |= URB_SEND_ZERO_PACKET;
4769
4770 dwc2_urb->priv = urb;
4771 dwc2_urb->buf = buf;
4772 dwc2_urb->dma = urb->transfer_dma;
4773 dwc2_urb->length = urb->transfer_buffer_length;
4774 dwc2_urb->setup_packet = urb->setup_packet;
4775 dwc2_urb->setup_dma = urb->setup_dma;
4776 dwc2_urb->flags = tflags;
4777 dwc2_urb->interval = urb->interval;
4778 dwc2_urb->status = -EINPROGRESS;
4779
4780 for (i = 0; i < urb->number_of_packets; ++i)
4781 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4782 urb->iso_frame_desc[i].offset,
4783 urb->iso_frame_desc[i].length);
4784
4785 urb->hcpriv = dwc2_urb;
4786 qh = (struct dwc2_qh *)ep->hcpriv;
4787
4788 if (!qh) {
4789 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4790 if (!qh) {
4791 retval = -ENOMEM;
4792 goto fail0;
4793 }
4794 ep->hcpriv = qh;
4795 qh_allocated = true;
4796 }
4797
4798 qtd = kzalloc(sizeof(*qtd), mem_flags);
4799 if (!qtd) {
4800 retval = -ENOMEM;
4801 goto fail1;
4802 }
4803
4804 spin_lock_irqsave(&hsotg->lock, flags);
4805 retval = usb_hcd_link_urb_to_ep(hcd, urb);
4806 if (retval)
4807 goto fail2;
4808
4809 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4810 if (retval)
4811 goto fail3;
4812
4813 if (alloc_bandwidth) {
4814 dwc2_allocate_bus_bandwidth(hcd,
4815 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4816 urb);
4817 }
4818
4819 spin_unlock_irqrestore(&hsotg->lock, flags);
4820
4821 return 0;
4822
4823fail3:
4824 dwc2_urb->priv = NULL;
4825 usb_hcd_unlink_urb_from_ep(hcd, urb);
4826 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4827 qh->channel->qh = NULL;
4828fail2:
4829 spin_unlock_irqrestore(&hsotg->lock, flags);
4830 urb->hcpriv = NULL;
4831 kfree(qtd);
4832 qtd = NULL;
4833fail1:
4834 if (qh_allocated) {
4835 struct dwc2_qtd *qtd2, *qtd2_tmp;
4836
4837 ep->hcpriv = NULL;
4838 dwc2_hcd_qh_unlink(hsotg, qh);
4839
4840 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4841 qtd_list_entry)
4842 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4843 dwc2_hcd_qh_free(hsotg, qh);
4844 }
4845fail0:
4846 kfree(dwc2_urb);
4847
4848 return retval;
4849}
4850
4851
4852
4853
4854static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4855 int status)
4856{
4857 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4858 int rc;
4859 unsigned long flags;
4860
4861 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4862 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4863
4864 spin_lock_irqsave(&hsotg->lock, flags);
4865
4866 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4867 if (rc)
4868 goto out;
4869
4870 if (!urb->hcpriv) {
4871 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4872 goto out;
4873 }
4874
4875 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4876
4877 usb_hcd_unlink_urb_from_ep(hcd, urb);
4878
4879 kfree(urb->hcpriv);
4880 urb->hcpriv = NULL;
4881
4882
4883 spin_unlock(&hsotg->lock);
4884 usb_hcd_giveback_urb(hcd, urb, status);
4885 spin_lock(&hsotg->lock);
4886
4887 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4888 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4889out:
4890 spin_unlock_irqrestore(&hsotg->lock, flags);
4891
4892 return rc;
4893}
4894
4895
4896
4897
4898
4899
4900static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4901 struct usb_host_endpoint *ep)
4902{
4903 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4904
4905 dev_dbg(hsotg->dev,
4906 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4907 ep->desc.bEndpointAddress, ep->hcpriv);
4908 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4909}
4910
4911
4912
4913
4914
4915
4916static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4917 struct usb_host_endpoint *ep)
4918{
4919 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4920 unsigned long flags;
4921
4922 dev_dbg(hsotg->dev,
4923 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4924 ep->desc.bEndpointAddress);
4925
4926 spin_lock_irqsave(&hsotg->lock, flags);
4927 dwc2_hcd_endpoint_reset(hsotg, ep);
4928 spin_unlock_irqrestore(&hsotg->lock, flags);
4929}
4930
4931
4932
4933
4934
4935
4936
4937
4938static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4939{
4940 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4941
4942 return dwc2_handle_hcd_intr(hsotg);
4943}
4944
4945
4946
4947
4948
4949
4950
4951static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4952{
4953 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4954
4955 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4956 return buf[0] != 0;
4957}
4958
4959
4960static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4961 u16 windex, char *buf, u16 wlength)
4962{
4963 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4964 wvalue, windex, buf, wlength);
4965 return retval;
4966}
4967
4968
4969static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4970 struct usb_host_endpoint *ep)
4971{
4972 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4973 struct dwc2_qh *qh;
4974 unsigned long flags;
4975
4976 qh = ep->hcpriv;
4977 if (!qh)
4978 return;
4979
4980 spin_lock_irqsave(&hsotg->lock, flags);
4981 qh->tt_buffer_dirty = 0;
4982
4983 if (hsotg->flags.b.port_connect_status)
4984 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4985
4986 spin_unlock_irqrestore(&hsotg->lock, flags);
4987}
4988
4989
4990
4991
4992
4993static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4994{
4995 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4996
4997 if (hsotg->params.speed == speed)
4998 return;
4999
5000 hsotg->params.speed = speed;
5001 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
5002}
5003
5004static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
5005{
5006 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5007
5008 if (!hsotg->params.change_speed_quirk)
5009 return;
5010
5011
5012
5013
5014 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
5015 udev->parent->speed < USB_SPEED_HIGH) {
5016 dev_info(hsotg->dev, "Set speed to default high-speed\n");
5017 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5018 }
5019}
5020
5021static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
5022{
5023 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5024
5025 if (!hsotg->params.change_speed_quirk)
5026 return 0;
5027
5028 if (udev->speed == USB_SPEED_HIGH) {
5029 dev_info(hsotg->dev, "Set speed to high-speed\n");
5030 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5031 } else if ((udev->speed == USB_SPEED_FULL ||
5032 udev->speed == USB_SPEED_LOW)) {
5033
5034
5035
5036
5037 dev_info(hsotg->dev, "Set speed to full-speed\n");
5038 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
5039 }
5040
5041 return 0;
5042}
5043
5044static struct hc_driver dwc2_hc_driver = {
5045 .description = "dwc2_hsotg",
5046 .product_desc = "DWC OTG Controller",
5047 .hcd_priv_size = sizeof(struct wrapper_priv_data),
5048
5049 .irq = _dwc2_hcd_irq,
5050 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
5051
5052 .start = _dwc2_hcd_start,
5053 .stop = _dwc2_hcd_stop,
5054 .urb_enqueue = _dwc2_hcd_urb_enqueue,
5055 .urb_dequeue = _dwc2_hcd_urb_dequeue,
5056 .endpoint_disable = _dwc2_hcd_endpoint_disable,
5057 .endpoint_reset = _dwc2_hcd_endpoint_reset,
5058 .get_frame_number = _dwc2_hcd_get_frame_number,
5059
5060 .hub_status_data = _dwc2_hcd_hub_status_data,
5061 .hub_control = _dwc2_hcd_hub_control,
5062 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
5063
5064 .bus_suspend = _dwc2_hcd_suspend,
5065 .bus_resume = _dwc2_hcd_resume,
5066
5067 .map_urb_for_dma = dwc2_map_urb_for_dma,
5068 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
5069};
5070
5071
5072
5073
5074
5075static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
5076{
5077 u32 ahbcfg;
5078 u32 dctl;
5079 int i;
5080
5081 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
5082
5083
5084 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
5085 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
5086 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
5087 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
5088 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
5089 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
5090 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
5091
5092
5093 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
5094 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
5095
5096 if (chan) {
5097 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
5098 i, chan);
5099 hsotg->hc_ptr_array[i] = NULL;
5100 kfree(chan);
5101 }
5102 }
5103
5104 if (hsotg->params.host_dma) {
5105 if (hsotg->status_buf) {
5106 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
5107 hsotg->status_buf,
5108 hsotg->status_buf_dma);
5109 hsotg->status_buf = NULL;
5110 }
5111 } else {
5112 kfree(hsotg->status_buf);
5113 hsotg->status_buf = NULL;
5114 }
5115
5116 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
5117
5118
5119 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5120 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
5121 dwc2_writel(hsotg, 0, GINTMSK);
5122
5123 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5124 dctl = dwc2_readl(hsotg, DCTL);
5125 dctl |= DCTL_SFTDISCON;
5126 dwc2_writel(hsotg, dctl, DCTL);
5127 }
5128
5129 if (hsotg->wq_otg) {
5130 if (!cancel_work_sync(&hsotg->wf_otg))
5131 flush_workqueue(hsotg->wq_otg);
5132 destroy_workqueue(hsotg->wq_otg);
5133 }
5134
5135 del_timer(&hsotg->wkp_timer);
5136}
5137
5138static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5139{
5140
5141 dwc2_disable_host_interrupts(hsotg);
5142
5143 dwc2_hcd_free(hsotg);
5144}
5145
5146
5147
5148
5149
5150
5151
5152int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5153{
5154 struct platform_device *pdev = to_platform_device(hsotg->dev);
5155 struct resource *res;
5156 struct usb_hcd *hcd;
5157 struct dwc2_host_chan *channel;
5158 u32 hcfg;
5159 int i, num_channels;
5160 int retval;
5161
5162 if (usb_disabled())
5163 return -ENODEV;
5164
5165 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5166
5167 retval = -ENOMEM;
5168
5169 hcfg = dwc2_readl(hsotg, HCFG);
5170 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5171
5172#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5173 hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE,
5174 sizeof(*hsotg->frame_num_array),
5175 GFP_KERNEL);
5176 if (!hsotg->frame_num_array)
5177 goto error1;
5178 hsotg->last_frame_num_array =
5179 kcalloc(FRAME_NUM_ARRAY_SIZE,
5180 sizeof(*hsotg->last_frame_num_array), GFP_KERNEL);
5181 if (!hsotg->last_frame_num_array)
5182 goto error1;
5183#endif
5184 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5185
5186
5187 if (hsotg->params.host_dma &&
5188 !hsotg->dev->dma_mask) {
5189 dev_warn(hsotg->dev,
5190 "dma_mask not set, disabling DMA\n");
5191 hsotg->params.host_dma = false;
5192 hsotg->params.dma_desc_enable = false;
5193 }
5194
5195
5196 if (hsotg->params.host_dma) {
5197 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5198 dev_warn(hsotg->dev, "can't set DMA mask\n");
5199 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5200 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5201 }
5202
5203 if (hsotg->params.change_speed_quirk) {
5204 dwc2_hc_driver.free_dev = dwc2_free_dev;
5205 dwc2_hc_driver.reset_device = dwc2_reset_device;
5206 }
5207
5208 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5209 if (!hcd)
5210 goto error1;
5211
5212 if (!hsotg->params.host_dma)
5213 hcd->self.uses_dma = 0;
5214
5215 hcd->has_tt = 1;
5216
5217 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5218 hcd->rsrc_start = res->start;
5219 hcd->rsrc_len = resource_size(res);
5220
5221 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5222 hsotg->priv = hcd;
5223
5224
5225
5226
5227
5228 dwc2_disable_global_interrupts(hsotg);
5229
5230
5231 retval = dwc2_core_init(hsotg, true);
5232 if (retval)
5233 goto error2;
5234
5235
5236 retval = -ENOMEM;
5237 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5238 if (!hsotg->wq_otg) {
5239 dev_err(hsotg->dev, "Failed to create workqueue\n");
5240 goto error2;
5241 }
5242 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5243
5244 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5245
5246
5247 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5248 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5249 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5250
5251
5252 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5253 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5254 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5255 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5256
5257 INIT_LIST_HEAD(&hsotg->split_order);
5258
5259
5260
5261
5262
5263 INIT_LIST_HEAD(&hsotg->free_hc_list);
5264 num_channels = hsotg->params.host_channels;
5265 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5266
5267 for (i = 0; i < num_channels; i++) {
5268 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5269 if (!channel)
5270 goto error3;
5271 channel->hc_num = i;
5272 INIT_LIST_HEAD(&channel->split_order_list_entry);
5273 hsotg->hc_ptr_array[i] = channel;
5274 }
5275
5276
5277 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5278
5279
5280 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5281
5282
5283
5284
5285
5286
5287
5288 if (hsotg->params.host_dma)
5289 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5290 DWC2_HCD_STATUS_BUF_SIZE,
5291 &hsotg->status_buf_dma, GFP_KERNEL);
5292 else
5293 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5294 GFP_KERNEL);
5295
5296 if (!hsotg->status_buf)
5297 goto error3;
5298
5299
5300
5301
5302
5303
5304 if (hsotg->params.dma_desc_enable ||
5305 hsotg->params.dma_desc_fs_enable) {
5306 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5307 sizeof(struct dwc2_dma_desc) *
5308 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5309 NULL);
5310 if (!hsotg->desc_gen_cache) {
5311 dev_err(hsotg->dev,
5312 "unable to create dwc2 generic desc cache\n");
5313
5314
5315
5316
5317
5318 hsotg->params.dma_desc_enable = false;
5319 hsotg->params.dma_desc_fs_enable = false;
5320 }
5321
5322 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5323 sizeof(struct dwc2_dma_desc) *
5324 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5325 if (!hsotg->desc_hsisoc_cache) {
5326 dev_err(hsotg->dev,
5327 "unable to create dwc2 hs isoc desc cache\n");
5328
5329 kmem_cache_destroy(hsotg->desc_gen_cache);
5330
5331
5332
5333
5334
5335 hsotg->params.dma_desc_enable = false;
5336 hsotg->params.dma_desc_fs_enable = false;
5337 }
5338 }
5339
5340 if (hsotg->params.host_dma) {
5341
5342
5343
5344
5345 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
5346 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4,
5347 SLAB_CACHE_DMA, NULL);
5348 if (!hsotg->unaligned_cache)
5349 dev_err(hsotg->dev,
5350 "unable to create dwc2 unaligned cache\n");
5351 }
5352
5353 hsotg->otg_port = 1;
5354 hsotg->frame_list = NULL;
5355 hsotg->frame_list_dma = 0;
5356 hsotg->periodic_qh_count = 0;
5357
5358
5359 hsotg->lx_state = DWC2_L3;
5360
5361 hcd->self.otg_port = hsotg->otg_port;
5362
5363
5364 hcd->self.sg_tablesize = 0;
5365
5366 if (!IS_ERR_OR_NULL(hsotg->uphy))
5367 otg_set_host(hsotg->uphy->otg, &hcd->self);
5368
5369
5370
5371
5372
5373
5374 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5375 if (retval < 0)
5376 goto error4;
5377
5378 device_wakeup_enable(hcd->self.controller);
5379
5380 dwc2_hcd_dump_state(hsotg);
5381
5382 dwc2_enable_global_interrupts(hsotg);
5383
5384 return 0;
5385
5386error4:
5387 kmem_cache_destroy(hsotg->unaligned_cache);
5388 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5389 kmem_cache_destroy(hsotg->desc_gen_cache);
5390error3:
5391 dwc2_hcd_release(hsotg);
5392error2:
5393 usb_put_hcd(hcd);
5394error1:
5395
5396#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5397 kfree(hsotg->last_frame_num_array);
5398 kfree(hsotg->frame_num_array);
5399#endif
5400
5401 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5402 return retval;
5403}
5404
5405
5406
5407
5408
5409void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5410{
5411 struct usb_hcd *hcd;
5412
5413 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5414
5415 hcd = dwc2_hsotg_to_hcd(hsotg);
5416 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5417
5418 if (!hcd) {
5419 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5420 __func__);
5421 return;
5422 }
5423
5424 if (!IS_ERR_OR_NULL(hsotg->uphy))
5425 otg_set_host(hsotg->uphy->otg, NULL);
5426
5427 usb_remove_hcd(hcd);
5428 hsotg->priv = NULL;
5429
5430 kmem_cache_destroy(hsotg->unaligned_cache);
5431 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5432 kmem_cache_destroy(hsotg->desc_gen_cache);
5433
5434 dwc2_hcd_release(hsotg);
5435 usb_put_hcd(hcd);
5436
5437#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5438 kfree(hsotg->last_frame_num_array);
5439 kfree(hsotg->frame_num_array);
5440#endif
5441}
5442
5443
5444
5445
5446
5447
5448
5449
5450int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5451{
5452 struct dwc2_hregs_backup *hr;
5453 int i;
5454
5455 dev_dbg(hsotg->dev, "%s\n", __func__);
5456
5457
5458 hr = &hsotg->hr_backup;
5459 hr->hcfg = dwc2_readl(hsotg, HCFG);
5460 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK);
5461 for (i = 0; i < hsotg->params.host_channels; ++i)
5462 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i));
5463
5464 hr->hprt0 = dwc2_read_hprt0(hsotg);
5465 hr->hfir = dwc2_readl(hsotg, HFIR);
5466 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
5467 hr->valid = true;
5468
5469 return 0;
5470}
5471
5472
5473
5474
5475
5476
5477
5478
5479int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5480{
5481 struct dwc2_hregs_backup *hr;
5482 int i;
5483
5484 dev_dbg(hsotg->dev, "%s\n", __func__);
5485
5486
5487 hr = &hsotg->hr_backup;
5488 if (!hr->valid) {
5489 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5490 __func__);
5491 return -EINVAL;
5492 }
5493 hr->valid = false;
5494
5495 dwc2_writel(hsotg, hr->hcfg, HCFG);
5496 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK);
5497
5498 for (i = 0; i < hsotg->params.host_channels; ++i)
5499 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i));
5500
5501 dwc2_writel(hsotg, hr->hprt0, HPRT0);
5502 dwc2_writel(hsotg, hr->hfir, HFIR);
5503 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ);
5504 hsotg->frame_number = 0;
5505
5506 return 0;
5507}
5508
5509
5510
5511
5512
5513
5514int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5515{
5516 unsigned long flags;
5517 int ret = 0;
5518 u32 hprt0;
5519 u32 pcgcctl;
5520 u32 gusbcfg;
5521 u32 gpwrdn;
5522
5523 dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
5524 ret = dwc2_backup_global_registers(hsotg);
5525 if (ret) {
5526 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5527 __func__);
5528 return ret;
5529 }
5530 ret = dwc2_backup_host_registers(hsotg);
5531 if (ret) {
5532 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5533 __func__);
5534 return ret;
5535 }
5536
5537
5538 hprt0 = dwc2_readl(hsotg, HPRT0);
5539 hprt0 |= HPRT0_SUSP;
5540 hprt0 &= ~HPRT0_ENA;
5541 dwc2_writel(hsotg, hprt0, HPRT0);
5542
5543
5544 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000))
5545 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5546
5547
5548
5549
5550
5551 spin_lock_irqsave(&hsotg->lock, flags);
5552 hsotg->lx_state = DWC2_L2;
5553
5554 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
5555 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5556
5557
5558 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5559 pcgcctl |= PCGCTL_STOPPCLK;
5560 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5561 udelay(10);
5562
5563 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5564 gpwrdn |= GPWRDN_PMUACTV;
5565 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5566 udelay(10);
5567 } else {
5568
5569 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5570 gpwrdn |= GPWRDN_PMUACTV;
5571 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5572 udelay(10);
5573
5574 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5575 pcgcctl |= PCGCTL_STOPPCLK;
5576 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5577 udelay(10);
5578 }
5579
5580
5581 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5582 gpwrdn |= GPWRDN_PMUINTSEL;
5583 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5584 udelay(10);
5585
5586
5587 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5588 gpwrdn |= GPWRDN_DISCONN_DET_MSK;
5589 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5590 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5591 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5592 udelay(10);
5593
5594
5595 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5596 gpwrdn |= GPWRDN_PWRDNCLMP;
5597 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5598 udelay(10);
5599
5600
5601 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5602 gpwrdn |= GPWRDN_PWRDNSWTCH;
5603 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5604
5605 hsotg->hibernated = 1;
5606 hsotg->bus_suspended = 1;
5607 dev_dbg(hsotg->dev, "Host hibernation completed\n");
5608 spin_unlock_irqrestore(&hsotg->lock, flags);
5609 return ret;
5610}
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5625 int reset)
5626{
5627 u32 gpwrdn;
5628 u32 hprt0;
5629 int ret = 0;
5630 struct dwc2_gregs_backup *gr;
5631 struct dwc2_hregs_backup *hr;
5632
5633 gr = &hsotg->gr_backup;
5634 hr = &hsotg->hr_backup;
5635
5636 dev_dbg(hsotg->dev,
5637 "%s: called with rem_wakeup = %d reset = %d\n",
5638 __func__, rem_wakeup, reset);
5639
5640 dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
5641 hsotg->hibernated = 0;
5642
5643
5644
5645
5646
5647
5648 mdelay(100);
5649
5650
5651 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5652
5653
5654 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5655 gpwrdn &= ~GPWRDN_RESTORE;
5656 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5657 udelay(10);
5658
5659
5660 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5661 dwc2_writel(hsotg, hr->hcfg, HCFG);
5662
5663
5664 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5665 gpwrdn &= ~GPWRDN_PMUACTV;
5666 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5667 udelay(10);
5668
5669 hprt0 = hr->hprt0;
5670 hprt0 |= HPRT0_PWR;
5671 hprt0 &= ~HPRT0_ENA;
5672 hprt0 &= ~HPRT0_SUSP;
5673 dwc2_writel(hsotg, hprt0, HPRT0);
5674
5675 hprt0 = hr->hprt0;
5676 hprt0 |= HPRT0_PWR;
5677 hprt0 &= ~HPRT0_ENA;
5678 hprt0 &= ~HPRT0_SUSP;
5679
5680 if (reset) {
5681 hprt0 |= HPRT0_RST;
5682 dwc2_writel(hsotg, hprt0, HPRT0);
5683
5684
5685 mdelay(60);
5686 hprt0 &= ~HPRT0_RST;
5687 dwc2_writel(hsotg, hprt0, HPRT0);
5688 } else {
5689 hprt0 |= HPRT0_RES;
5690 dwc2_writel(hsotg, hprt0, HPRT0);
5691
5692
5693 mdelay(100);
5694 hprt0 &= ~HPRT0_RES;
5695 dwc2_writel(hsotg, hprt0, HPRT0);
5696 }
5697
5698 hprt0 = dwc2_readl(hsotg, HPRT0);
5699 hprt0 |= HPRT0_CONNDET;
5700 hprt0 |= HPRT0_ENACHG;
5701 hprt0 &= ~HPRT0_ENA;
5702 dwc2_writel(hsotg, hprt0, HPRT0);
5703
5704 hprt0 = dwc2_readl(hsotg, HPRT0);
5705
5706
5707 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5708
5709
5710 ret = dwc2_restore_global_registers(hsotg);
5711 if (ret) {
5712 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5713 __func__);
5714 return ret;
5715 }
5716
5717
5718 ret = dwc2_restore_host_registers(hsotg);
5719 if (ret) {
5720 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5721 __func__);
5722 return ret;
5723 }
5724
5725 dwc2_hcd_rem_wakeup(hsotg);
5726
5727 hsotg->hibernated = 0;
5728 hsotg->bus_suspended = 0;
5729 hsotg->lx_state = DWC2_L0;
5730 dev_dbg(hsotg->dev, "Host hibernation restore complete\n");
5731 return ret;
5732}
5733