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14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/kernel.h>
17#include <linux/gpio/consumer.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/i2c.h>
21#include <linux/input.h>
22#include <linux/regmap.h>
23#include <linux/slab.h>
24#include <linux/platform_device.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32#include "cs4265.h"
33
34struct cs4265_private {
35 struct regmap *regmap;
36 struct gpio_desc *reset_gpio;
37 u8 format;
38 u32 sysclk;
39};
40
41static const struct reg_default cs4265_reg_defaults[] = {
42 { CS4265_PWRCTL, 0x0F },
43 { CS4265_DAC_CTL, 0x08 },
44 { CS4265_ADC_CTL, 0x00 },
45 { CS4265_MCLK_FREQ, 0x00 },
46 { CS4265_SIG_SEL, 0x40 },
47 { CS4265_CHB_PGA_CTL, 0x00 },
48 { CS4265_CHA_PGA_CTL, 0x00 },
49 { CS4265_ADC_CTL2, 0x19 },
50 { CS4265_DAC_CHA_VOL, 0x00 },
51 { CS4265_DAC_CHB_VOL, 0x00 },
52 { CS4265_DAC_CTL2, 0xC0 },
53 { CS4265_SPDIF_CTL1, 0x00 },
54 { CS4265_SPDIF_CTL2, 0x00 },
55 { CS4265_INT_MASK, 0x00 },
56 { CS4265_STATUS_MODE_MSB, 0x00 },
57 { CS4265_STATUS_MODE_LSB, 0x00 },
58};
59
60static bool cs4265_readable_register(struct device *dev, unsigned int reg)
61{
62 switch (reg) {
63 case CS4265_CHIP_ID ... CS4265_SPDIF_CTL2:
64 return true;
65 default:
66 return false;
67 }
68}
69
70static bool cs4265_volatile_register(struct device *dev, unsigned int reg)
71{
72 switch (reg) {
73 case CS4265_INT_STATUS:
74 return true;
75 default:
76 return false;
77 }
78}
79
80static DECLARE_TLV_DB_SCALE(pga_tlv, -1200, 50, 0);
81
82static DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 0);
83
84static const char * const digital_input_mux_text[] = {
85 "SDIN1", "SDIN2"
86};
87
88static SOC_ENUM_SINGLE_DECL(digital_input_mux_enum, CS4265_SIG_SEL, 7,
89 digital_input_mux_text);
90
91static const struct snd_kcontrol_new digital_input_mux =
92 SOC_DAPM_ENUM("Digital Input Mux", digital_input_mux_enum);
93
94static const char * const mic_linein_text[] = {
95 "MIC", "LINEIN"
96};
97
98static SOC_ENUM_SINGLE_DECL(mic_linein_enum, CS4265_ADC_CTL2, 0,
99 mic_linein_text);
100
101static const char * const cam_mode_text[] = {
102 "One Byte", "Two Byte"
103};
104
105static SOC_ENUM_SINGLE_DECL(cam_mode_enum, CS4265_SPDIF_CTL1, 5,
106 cam_mode_text);
107
108static const char * const cam_mono_stereo_text[] = {
109 "Stereo", "Mono"
110};
111
112static SOC_ENUM_SINGLE_DECL(spdif_mono_stereo_enum, CS4265_SPDIF_CTL2, 2,
113 cam_mono_stereo_text);
114
115static const char * const mono_select_text[] = {
116 "Channel A", "Channel B"
117};
118
119static SOC_ENUM_SINGLE_DECL(spdif_mono_select_enum, CS4265_SPDIF_CTL2, 0,
120 mono_select_text);
121
122static const struct snd_kcontrol_new mic_linein_mux =
123 SOC_DAPM_ENUM("ADC Input Capture Mux", mic_linein_enum);
124
125static const struct snd_kcontrol_new loopback_ctl =
126 SOC_DAPM_SINGLE("Switch", CS4265_SIG_SEL, 1, 1, 0);
127
128static const struct snd_kcontrol_new spdif_switch =
129 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 0, 0);
130
131static const struct snd_kcontrol_new dac_switch =
132 SOC_DAPM_SINGLE("Switch", CS4265_PWRCTL, 1, 1, 0);
133
134static const struct snd_kcontrol_new cs4265_snd_controls[] = {
135
136 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS4265_CHA_PGA_CTL,
137 CS4265_CHB_PGA_CTL, 0, 0x28, 0x30, pga_tlv),
138 SOC_DOUBLE_R_TLV("DAC Volume", CS4265_DAC_CHA_VOL,
139 CS4265_DAC_CHB_VOL, 0, 0xFF, 1, dac_tlv),
140 SOC_SINGLE("De-emp 44.1kHz Switch", CS4265_DAC_CTL, 1,
141 1, 0),
142 SOC_SINGLE("DAC INV Switch", CS4265_DAC_CTL2, 5,
143 1, 0),
144 SOC_SINGLE("DAC Zero Cross Switch", CS4265_DAC_CTL2, 6,
145 1, 0),
146 SOC_SINGLE("DAC Soft Ramp Switch", CS4265_DAC_CTL2, 7,
147 1, 0),
148 SOC_SINGLE("ADC HPF Switch", CS4265_ADC_CTL, 1,
149 1, 0),
150 SOC_SINGLE("ADC Zero Cross Switch", CS4265_ADC_CTL2, 3,
151 1, 1),
152 SOC_SINGLE("ADC Soft Ramp Switch", CS4265_ADC_CTL2, 7,
153 1, 0),
154 SOC_SINGLE("E to F Buffer Disable Switch", CS4265_SPDIF_CTL1,
155 6, 1, 0),
156 SOC_ENUM("C Data Access", cam_mode_enum),
157 SOC_SINGLE("SPDIF Switch", CS4265_SPDIF_CTL2, 5, 1, 1),
158 SOC_SINGLE("Validity Bit Control Switch", CS4265_SPDIF_CTL2,
159 3, 1, 0),
160 SOC_ENUM("SPDIF Mono/Stereo", spdif_mono_stereo_enum),
161 SOC_SINGLE("MMTLR Data Switch", CS4265_SPDIF_CTL2, 0, 1, 0),
162 SOC_ENUM("Mono Channel Select", spdif_mono_select_enum),
163 SND_SOC_BYTES("C Data Buffer", CS4265_C_DATA_BUFF, 24),
164};
165
166static const struct snd_soc_dapm_widget cs4265_dapm_widgets[] = {
167
168 SND_SOC_DAPM_INPUT("LINEINL"),
169 SND_SOC_DAPM_INPUT("LINEINR"),
170 SND_SOC_DAPM_INPUT("MICL"),
171 SND_SOC_DAPM_INPUT("MICR"),
172
173 SND_SOC_DAPM_AIF_OUT("DOUT", NULL, 0,
174 SND_SOC_NOPM, 0, 0),
175 SND_SOC_DAPM_AIF_OUT("SPDIFOUT", NULL, 0,
176 SND_SOC_NOPM, 0, 0),
177
178 SND_SOC_DAPM_MUX("ADC Mux", SND_SOC_NOPM, 0, 0, &mic_linein_mux),
179
180 SND_SOC_DAPM_ADC("ADC", NULL, CS4265_PWRCTL, 2, 1),
181 SND_SOC_DAPM_PGA("Pre-amp MIC", CS4265_PWRCTL, 3,
182 1, NULL, 0),
183
184 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM,
185 0, 0, &digital_input_mux),
186
187 SND_SOC_DAPM_MIXER("SDIN1 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
188 SND_SOC_DAPM_MIXER("SDIN2 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
189 SND_SOC_DAPM_MIXER("SPDIF Transmitter", SND_SOC_NOPM, 0, 0, NULL, 0),
190
191 SND_SOC_DAPM_SWITCH("Loopback", SND_SOC_NOPM, 0, 0,
192 &loopback_ctl),
193 SND_SOC_DAPM_SWITCH("SPDIF", SND_SOC_NOPM, 0, 0,
194 &spdif_switch),
195 SND_SOC_DAPM_SWITCH("DAC", CS4265_PWRCTL, 1, 1,
196 &dac_switch),
197
198 SND_SOC_DAPM_AIF_IN("DIN1", NULL, 0,
199 SND_SOC_NOPM, 0, 0),
200 SND_SOC_DAPM_AIF_IN("DIN2", NULL, 0,
201 SND_SOC_NOPM, 0, 0),
202 SND_SOC_DAPM_AIF_IN("TXIN", NULL, 0,
203 CS4265_SPDIF_CTL2, 5, 1),
204
205 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
206 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
207
208};
209
210static const struct snd_soc_dapm_route cs4265_audio_map[] = {
211
212 {"DIN1", NULL, "DAI1 Playback"},
213 {"DIN2", NULL, "DAI2 Playback"},
214 {"SDIN1 Input Mixer", NULL, "DIN1"},
215 {"SDIN2 Input Mixer", NULL, "DIN2"},
216 {"Input Mux", "SDIN1", "SDIN1 Input Mixer"},
217 {"Input Mux", "SDIN2", "SDIN2 Input Mixer"},
218 {"DAC", "Switch", "Input Mux"},
219 {"SPDIF", "Switch", "Input Mux"},
220 {"LINEOUTL", NULL, "DAC"},
221 {"LINEOUTR", NULL, "DAC"},
222 {"SPDIFOUT", NULL, "SPDIF"},
223
224 {"Pre-amp MIC", NULL, "MICL"},
225 {"Pre-amp MIC", NULL, "MICR"},
226 {"ADC Mux", "MIC", "Pre-amp MIC"},
227 {"ADC Mux", "LINEIN", "LINEINL"},
228 {"ADC Mux", "LINEIN", "LINEINR"},
229 {"ADC", NULL, "ADC Mux"},
230 {"DOUT", NULL, "ADC"},
231 {"DAI1 Capture", NULL, "DOUT"},
232 {"DAI2 Capture", NULL, "DOUT"},
233
234
235 {"Loopback", "Switch", "ADC"},
236 {"DAC", NULL, "Loopback"},
237};
238
239struct cs4265_clk_para {
240 u32 mclk;
241 u32 rate;
242 u8 fm_mode;
243 u8 mclkdiv;
244};
245
246static const struct cs4265_clk_para clk_map_table[] = {
247
248 {8192000, 32000, 0, 0},
249 {12288000, 32000, 0, 1},
250 {16384000, 32000, 0, 2},
251 {24576000, 32000, 0, 3},
252 {32768000, 32000, 0, 4},
253
254
255 {11289600, 44100, 0, 0},
256 {16934400, 44100, 0, 1},
257 {22579200, 44100, 0, 2},
258 {33868000, 44100, 0, 3},
259 {45158400, 44100, 0, 4},
260
261
262 {12288000, 48000, 0, 0},
263 {18432000, 48000, 0, 1},
264 {24576000, 48000, 0, 2},
265 {36864000, 48000, 0, 3},
266 {49152000, 48000, 0, 4},
267
268
269 {8192000, 64000, 1, 0},
270 {12288000, 64000, 1, 1},
271 {16934400, 64000, 1, 2},
272 {24576000, 64000, 1, 3},
273 {32768000, 64000, 1, 4},
274
275
276 {11289600, 88200, 1, 0},
277 {16934400, 88200, 1, 1},
278 {22579200, 88200, 1, 2},
279 {33868000, 88200, 1, 3},
280 {45158400, 88200, 1, 4},
281
282
283 {12288000, 96000, 1, 0},
284 {18432000, 96000, 1, 1},
285 {24576000, 96000, 1, 2},
286 {36864000, 96000, 1, 3},
287 {49152000, 96000, 1, 4},
288
289
290 {8192000, 128000, 2, 0},
291 {12288000, 128000, 2, 1},
292 {16934400, 128000, 2, 2},
293 {24576000, 128000, 2, 3},
294 {32768000, 128000, 2, 4},
295
296
297 {11289600, 176400, 2, 0},
298 {16934400, 176400, 2, 1},
299 {22579200, 176400, 2, 2},
300 {33868000, 176400, 2, 3},
301 {49152000, 176400, 2, 4},
302
303
304 {12288000, 192000, 2, 0},
305 {18432000, 192000, 2, 1},
306 {24576000, 192000, 2, 2},
307 {36864000, 192000, 2, 3},
308 {49152000, 192000, 2, 4},
309};
310
311static int cs4265_get_clk_index(int mclk, int rate)
312{
313 int i;
314
315 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
316 if (clk_map_table[i].rate == rate &&
317 clk_map_table[i].mclk == mclk)
318 return i;
319 }
320 return -EINVAL;
321}
322
323static int cs4265_set_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
324 unsigned int freq, int dir)
325{
326 struct snd_soc_component *component = codec_dai->component;
327 struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
328 int i;
329
330 if (clk_id != 0) {
331 dev_err(component->dev, "Invalid clk_id %d\n", clk_id);
332 return -EINVAL;
333 }
334 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
335 if (clk_map_table[i].mclk == freq) {
336 cs4265->sysclk = freq;
337 return 0;
338 }
339 }
340 cs4265->sysclk = 0;
341 dev_err(component->dev, "Invalid freq parameter %d\n", freq);
342 return -EINVAL;
343}
344
345static int cs4265_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
346{
347 struct snd_soc_component *component = codec_dai->component;
348 struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
349 u8 iface = 0;
350
351 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
352 case SND_SOC_DAIFMT_CBM_CFM:
353 snd_soc_component_update_bits(component, CS4265_ADC_CTL,
354 CS4265_ADC_MASTER,
355 CS4265_ADC_MASTER);
356 break;
357 case SND_SOC_DAIFMT_CBS_CFS:
358 snd_soc_component_update_bits(component, CS4265_ADC_CTL,
359 CS4265_ADC_MASTER,
360 0);
361 break;
362 default:
363 return -EINVAL;
364 }
365
366
367 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
368 case SND_SOC_DAIFMT_I2S:
369 iface |= SND_SOC_DAIFMT_I2S;
370 break;
371 case SND_SOC_DAIFMT_RIGHT_J:
372 iface |= SND_SOC_DAIFMT_RIGHT_J;
373 break;
374 case SND_SOC_DAIFMT_LEFT_J:
375 iface |= SND_SOC_DAIFMT_LEFT_J;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 cs4265->format = iface;
382 return 0;
383}
384
385static int cs4265_digital_mute(struct snd_soc_dai *dai, int mute)
386{
387 struct snd_soc_component *component = dai->component;
388
389 if (mute) {
390 snd_soc_component_update_bits(component, CS4265_DAC_CTL,
391 CS4265_DAC_CTL_MUTE,
392 CS4265_DAC_CTL_MUTE);
393 snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
394 CS4265_SPDIF_CTL2_MUTE,
395 CS4265_SPDIF_CTL2_MUTE);
396 } else {
397 snd_soc_component_update_bits(component, CS4265_DAC_CTL,
398 CS4265_DAC_CTL_MUTE,
399 0);
400 snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
401 CS4265_SPDIF_CTL2_MUTE,
402 0);
403 }
404 return 0;
405}
406
407static int cs4265_pcm_hw_params(struct snd_pcm_substream *substream,
408 struct snd_pcm_hw_params *params,
409 struct snd_soc_dai *dai)
410{
411 struct snd_soc_component *component = dai->component;
412 struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
413 int index;
414
415 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
416 ((cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK)
417 == SND_SOC_DAIFMT_RIGHT_J))
418 return -EINVAL;
419
420 index = cs4265_get_clk_index(cs4265->sysclk, params_rate(params));
421 if (index >= 0) {
422 snd_soc_component_update_bits(component, CS4265_ADC_CTL,
423 CS4265_ADC_FM, clk_map_table[index].fm_mode << 6);
424 snd_soc_component_update_bits(component, CS4265_MCLK_FREQ,
425 CS4265_MCLK_FREQ_MASK,
426 clk_map_table[index].mclkdiv << 4);
427
428 } else {
429 dev_err(component->dev, "can't get correct mclk\n");
430 return -EINVAL;
431 }
432
433 switch (cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK) {
434 case SND_SOC_DAIFMT_I2S:
435 snd_soc_component_update_bits(component, CS4265_DAC_CTL,
436 CS4265_DAC_CTL_DIF, (1 << 4));
437 snd_soc_component_update_bits(component, CS4265_ADC_CTL,
438 CS4265_ADC_DIF, (1 << 4));
439 snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
440 CS4265_SPDIF_CTL2_DIF, (1 << 6));
441 break;
442 case SND_SOC_DAIFMT_RIGHT_J:
443 if (params_width(params) == 16) {
444 snd_soc_component_update_bits(component, CS4265_DAC_CTL,
445 CS4265_DAC_CTL_DIF, (2 << 4));
446 snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
447 CS4265_SPDIF_CTL2_DIF, (2 << 6));
448 } else {
449 snd_soc_component_update_bits(component, CS4265_DAC_CTL,
450 CS4265_DAC_CTL_DIF, (3 << 4));
451 snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
452 CS4265_SPDIF_CTL2_DIF, (3 << 6));
453 }
454 break;
455 case SND_SOC_DAIFMT_LEFT_J:
456 snd_soc_component_update_bits(component, CS4265_DAC_CTL,
457 CS4265_DAC_CTL_DIF, 0);
458 snd_soc_component_update_bits(component, CS4265_ADC_CTL,
459 CS4265_ADC_DIF, 0);
460 snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
461 CS4265_SPDIF_CTL2_DIF, 0);
462
463 break;
464 default:
465 return -EINVAL;
466 }
467 return 0;
468}
469
470static int cs4265_set_bias_level(struct snd_soc_component *component,
471 enum snd_soc_bias_level level)
472{
473 switch (level) {
474 case SND_SOC_BIAS_ON:
475 break;
476 case SND_SOC_BIAS_PREPARE:
477 snd_soc_component_update_bits(component, CS4265_PWRCTL,
478 CS4265_PWRCTL_PDN, 0);
479 break;
480 case SND_SOC_BIAS_STANDBY:
481 snd_soc_component_update_bits(component, CS4265_PWRCTL,
482 CS4265_PWRCTL_PDN,
483 CS4265_PWRCTL_PDN);
484 break;
485 case SND_SOC_BIAS_OFF:
486 snd_soc_component_update_bits(component, CS4265_PWRCTL,
487 CS4265_PWRCTL_PDN,
488 CS4265_PWRCTL_PDN);
489 break;
490 }
491 return 0;
492}
493
494#define CS4265_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
495 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
496 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
497 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
498
499#define CS4265_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
500 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE | \
501 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
502
503static const struct snd_soc_dai_ops cs4265_ops = {
504 .hw_params = cs4265_pcm_hw_params,
505 .digital_mute = cs4265_digital_mute,
506 .set_fmt = cs4265_set_fmt,
507 .set_sysclk = cs4265_set_sysclk,
508};
509
510static struct snd_soc_dai_driver cs4265_dai[] = {
511 {
512 .name = "cs4265-dai1",
513 .playback = {
514 .stream_name = "DAI1 Playback",
515 .channels_min = 1,
516 .channels_max = 2,
517 .rates = CS4265_RATES,
518 .formats = CS4265_FORMATS,
519 },
520 .capture = {
521 .stream_name = "DAI1 Capture",
522 .channels_min = 1,
523 .channels_max = 2,
524 .rates = CS4265_RATES,
525 .formats = CS4265_FORMATS,
526 },
527 .ops = &cs4265_ops,
528 },
529 {
530 .name = "cs4265-dai2",
531 .playback = {
532 .stream_name = "DAI2 Playback",
533 .channels_min = 1,
534 .channels_max = 2,
535 .rates = CS4265_RATES,
536 .formats = CS4265_FORMATS,
537 },
538 .capture = {
539 .stream_name = "DAI2 Capture",
540 .channels_min = 1,
541 .channels_max = 2,
542 .rates = CS4265_RATES,
543 .formats = CS4265_FORMATS,
544 },
545 .ops = &cs4265_ops,
546 },
547};
548
549static const struct snd_soc_component_driver soc_component_cs4265 = {
550 .set_bias_level = cs4265_set_bias_level,
551 .controls = cs4265_snd_controls,
552 .num_controls = ARRAY_SIZE(cs4265_snd_controls),
553 .dapm_widgets = cs4265_dapm_widgets,
554 .num_dapm_widgets = ARRAY_SIZE(cs4265_dapm_widgets),
555 .dapm_routes = cs4265_audio_map,
556 .num_dapm_routes = ARRAY_SIZE(cs4265_audio_map),
557 .idle_bias_on = 1,
558 .use_pmdown_time = 1,
559 .endianness = 1,
560 .non_legacy_dai_naming = 1,
561};
562
563static const struct regmap_config cs4265_regmap = {
564 .reg_bits = 8,
565 .val_bits = 8,
566
567 .max_register = CS4265_MAX_REGISTER,
568 .reg_defaults = cs4265_reg_defaults,
569 .num_reg_defaults = ARRAY_SIZE(cs4265_reg_defaults),
570 .readable_reg = cs4265_readable_register,
571 .volatile_reg = cs4265_volatile_register,
572 .cache_type = REGCACHE_RBTREE,
573};
574
575static int cs4265_i2c_probe(struct i2c_client *i2c_client,
576 const struct i2c_device_id *id)
577{
578 struct cs4265_private *cs4265;
579 int ret = 0;
580 unsigned int devid = 0;
581 unsigned int reg;
582
583 cs4265 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs4265_private),
584 GFP_KERNEL);
585 if (cs4265 == NULL)
586 return -ENOMEM;
587
588 cs4265->regmap = devm_regmap_init_i2c(i2c_client, &cs4265_regmap);
589 if (IS_ERR(cs4265->regmap)) {
590 ret = PTR_ERR(cs4265->regmap);
591 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
592 return ret;
593 }
594
595 cs4265->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
596 "reset", GPIOD_OUT_LOW);
597 if (IS_ERR(cs4265->reset_gpio))
598 return PTR_ERR(cs4265->reset_gpio);
599
600 if (cs4265->reset_gpio) {
601 mdelay(1);
602 gpiod_set_value_cansleep(cs4265->reset_gpio, 1);
603 }
604
605 i2c_set_clientdata(i2c_client, cs4265);
606
607 ret = regmap_read(cs4265->regmap, CS4265_CHIP_ID, ®);
608 devid = reg & CS4265_CHIP_ID_MASK;
609 if (devid != CS4265_CHIP_ID_VAL) {
610 ret = -ENODEV;
611 dev_err(&i2c_client->dev,
612 "CS4265 Device ID (%X). Expected %X\n",
613 devid, CS4265_CHIP_ID);
614 return ret;
615 }
616 dev_info(&i2c_client->dev,
617 "CS4265 Version %x\n",
618 reg & CS4265_REV_ID_MASK);
619
620 regmap_write(cs4265->regmap, CS4265_PWRCTL, 0x0F);
621
622 ret = devm_snd_soc_register_component(&i2c_client->dev,
623 &soc_component_cs4265, cs4265_dai,
624 ARRAY_SIZE(cs4265_dai));
625 return ret;
626}
627
628static const struct of_device_id cs4265_of_match[] = {
629 { .compatible = "cirrus,cs4265", },
630 { }
631};
632MODULE_DEVICE_TABLE(of, cs4265_of_match);
633
634static const struct i2c_device_id cs4265_id[] = {
635 { "cs4265", 0 },
636 { }
637};
638MODULE_DEVICE_TABLE(i2c, cs4265_id);
639
640static struct i2c_driver cs4265_i2c_driver = {
641 .driver = {
642 .name = "cs4265",
643 .of_match_table = cs4265_of_match,
644 },
645 .id_table = cs4265_id,
646 .probe = cs4265_i2c_probe,
647};
648
649module_i2c_driver(cs4265_i2c_driver);
650
651MODULE_DESCRIPTION("ASoC CS4265 driver");
652MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>");
653MODULE_LICENSE("GPL");
654
