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18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/pm_runtime.h>
26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/of_device.h>
29#include <linux/platform_data/davinci_asp.h>
30#include <linux/math64.h>
31
32#include <sound/asoundef.h>
33#include <sound/core.h>
34#include <sound/pcm.h>
35#include <sound/pcm_params.h>
36#include <sound/initval.h>
37#include <sound/soc.h>
38#include <sound/dmaengine_pcm.h>
39
40#include "edma-pcm.h"
41#include "../omap/sdma-pcm.h"
42#include "davinci-mcasp.h"
43
44#define MCASP_MAX_AFIFO_DEPTH 64
45
46static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
53 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
55 DAVINCI_MCASP_PDIR_REG,
56 DAVINCI_MCASP_RXMASK_REG,
57 DAVINCI_MCASP_TXMASK_REG,
58 DAVINCI_MCASP_RXTDM_REG,
59 DAVINCI_MCASP_TXTDM_REG,
60};
61
62struct davinci_mcasp_context {
63 u32 config_regs[ARRAY_SIZE(context_regs)];
64 u32 afifo_regs[2];
65 u32 *xrsr_regs;
66 bool pm_state;
67};
68
69struct davinci_mcasp_ruledata {
70 struct davinci_mcasp *mcasp;
71 int serializers;
72};
73
74struct davinci_mcasp {
75 struct snd_dmaengine_dai_dma_data dma_data[2];
76 void __iomem *base;
77 u32 fifo_base;
78 struct device *dev;
79 struct snd_pcm_substream *substreams[2];
80 unsigned int dai_fmt;
81
82
83 int tdm_slots;
84 u32 tdm_mask[2];
85 int slot_width;
86 u8 op_mode;
87 u8 num_serializer;
88 u8 *serial_dir;
89 u8 version;
90 u8 bclk_div;
91 int streams;
92 u32 irq_request[2];
93 int dma_request[2];
94
95 int sysclk_freq;
96 bool bclk_master;
97
98
99 u8 txnumevt;
100 u8 rxnumevt;
101
102 bool dat_port;
103
104
105 u32 channels;
106
107#ifdef CONFIG_PM_SLEEP
108 struct davinci_mcasp_context context;
109#endif
110
111 struct davinci_mcasp_ruledata ruledata[2];
112 struct snd_pcm_hw_constraint_list chconstr[2];
113};
114
115static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
116 u32 val)
117{
118 void __iomem *reg = mcasp->base + offset;
119 __raw_writel(__raw_readl(reg) | val, reg);
120}
121
122static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
123 u32 val)
124{
125 void __iomem *reg = mcasp->base + offset;
126 __raw_writel((__raw_readl(reg) & ~(val)), reg);
127}
128
129static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
130 u32 val, u32 mask)
131{
132 void __iomem *reg = mcasp->base + offset;
133 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
134}
135
136static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
137 u32 val)
138{
139 __raw_writel(val, mcasp->base + offset);
140}
141
142static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
143{
144 return (u32)__raw_readl(mcasp->base + offset);
145}
146
147static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
148{
149 int i = 0;
150
151 mcasp_set_bits(mcasp, ctl_reg, val);
152
153
154
155 for (i = 0; i < 1000; i++) {
156 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
157 break;
158 }
159
160 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
161 printk(KERN_ERR "GBLCTL write error\n");
162}
163
164static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
165{
166 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
167 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
168
169 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
170}
171
172static void mcasp_start_rx(struct davinci_mcasp *mcasp)
173{
174 if (mcasp->rxnumevt) {
175 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
176
177 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
178 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
179 }
180
181
182 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
183 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
184
185
186
187
188
189 if (mcasp_is_synchronous(mcasp)) {
190 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
191 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
192 }
193
194
195 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
196
197 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
198
199 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
200 if (mcasp_is_synchronous(mcasp))
201 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
202
203
204 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
205 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
206}
207
208static void mcasp_start_tx(struct davinci_mcasp *mcasp)
209{
210 u32 cnt;
211
212 if (mcasp->txnumevt) {
213 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
214
215 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
216 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
217 }
218
219
220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
221 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
222
223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
224
225
226 cnt = 0;
227 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
228 (cnt < 100000))
229 cnt++;
230
231
232 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
233
234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
235
236
237 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
238 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
239}
240
241static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
242{
243 mcasp->streams++;
244
245 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
246 mcasp_start_tx(mcasp);
247 else
248 mcasp_start_rx(mcasp);
249}
250
251static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
252{
253
254 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
255 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
256
257
258
259
260
261 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
262 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
263
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
265 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
266
267 if (mcasp->rxnumevt) {
268 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
269
270 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
271 }
272}
273
274static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
275{
276 u32 val = 0;
277
278
279 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
280 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
281
282
283
284
285
286 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
287 val = TXHCLKRST | TXCLKRST | TXFSRST;
288
289 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
290 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
291
292 if (mcasp->txnumevt) {
293 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
294
295 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
296 }
297}
298
299static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
300{
301 mcasp->streams--;
302
303 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
304 mcasp_stop_tx(mcasp);
305 else
306 mcasp_stop_rx(mcasp);
307}
308
309static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
310{
311 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
312 struct snd_pcm_substream *substream;
313 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
314 u32 handled_mask = 0;
315 u32 stat;
316
317 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
318 if (stat & XUNDRN & irq_mask) {
319 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
320 handled_mask |= XUNDRN;
321
322 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
323 if (substream)
324 snd_pcm_stop_xrun(substream);
325 }
326
327 if (!handled_mask)
328 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
329 stat);
330
331 if (stat & XRERR)
332 handled_mask |= XRERR;
333
334
335 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
336
337 return IRQ_RETVAL(handled_mask);
338}
339
340static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
341{
342 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
343 struct snd_pcm_substream *substream;
344 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
345 u32 handled_mask = 0;
346 u32 stat;
347
348 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
349 if (stat & ROVRN & irq_mask) {
350 dev_warn(mcasp->dev, "Receive buffer overflow\n");
351 handled_mask |= ROVRN;
352
353 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
354 if (substream)
355 snd_pcm_stop_xrun(substream);
356 }
357
358 if (!handled_mask)
359 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
360 stat);
361
362 if (stat & XRERR)
363 handled_mask |= XRERR;
364
365
366 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
367
368 return IRQ_RETVAL(handled_mask);
369}
370
371static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
372{
373 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
374 irqreturn_t ret = IRQ_NONE;
375
376 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
377 ret = davinci_mcasp_tx_irq_handler(irq, data);
378
379 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
380 ret |= davinci_mcasp_rx_irq_handler(irq, data);
381
382 return ret;
383}
384
385static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
386 unsigned int fmt)
387{
388 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
389 int ret = 0;
390 u32 data_delay;
391 bool fs_pol_rising;
392 bool inv_fs = false;
393
394 if (!fmt)
395 return 0;
396
397 pm_runtime_get_sync(mcasp->dev);
398 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
399 case SND_SOC_DAIFMT_DSP_A:
400 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
401 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
402
403 data_delay = 1;
404 break;
405 case SND_SOC_DAIFMT_DSP_B:
406 case SND_SOC_DAIFMT_AC97:
407 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
408 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
409
410 data_delay = 0;
411 break;
412 case SND_SOC_DAIFMT_I2S:
413
414 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
415 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
416
417 data_delay = 1;
418
419 inv_fs = true;
420 break;
421 case SND_SOC_DAIFMT_LEFT_J:
422
423 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
424 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
425
426 data_delay = 0;
427 break;
428 default:
429 ret = -EINVAL;
430 goto out;
431 }
432
433 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
434 FSXDLY(3));
435 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
436 FSRDLY(3));
437
438 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
439 case SND_SOC_DAIFMT_CBS_CFS:
440
441 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
442 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
443
444 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
445 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
446
447 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
448 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
449 mcasp->bclk_master = 1;
450 break;
451 case SND_SOC_DAIFMT_CBS_CFM:
452
453 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
454 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
455
456 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
457 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
458
459 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
460 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
461 mcasp->bclk_master = 1;
462 break;
463 case SND_SOC_DAIFMT_CBM_CFS:
464
465 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
466 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
467
468 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
469 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
470
471 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
472 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
473 mcasp->bclk_master = 0;
474 break;
475 case SND_SOC_DAIFMT_CBM_CFM:
476
477 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
478 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
479
480 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
481 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
482
483 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
484 ACLKX | AFSX | ACLKR | AHCLKR | AFSR);
485 mcasp->bclk_master = 0;
486 break;
487 default:
488 ret = -EINVAL;
489 goto out;
490 }
491
492 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
493 case SND_SOC_DAIFMT_IB_NF:
494 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
495 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
496 fs_pol_rising = true;
497 break;
498 case SND_SOC_DAIFMT_NB_IF:
499 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
500 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
501 fs_pol_rising = false;
502 break;
503 case SND_SOC_DAIFMT_IB_IF:
504 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
505 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
506 fs_pol_rising = false;
507 break;
508 case SND_SOC_DAIFMT_NB_NF:
509 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
510 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
511 fs_pol_rising = true;
512 break;
513 default:
514 ret = -EINVAL;
515 goto out;
516 }
517
518 if (inv_fs)
519 fs_pol_rising = !fs_pol_rising;
520
521 if (fs_pol_rising) {
522 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
523 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
524 } else {
525 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
526 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
527 }
528
529 mcasp->dai_fmt = fmt;
530out:
531 pm_runtime_put(mcasp->dev);
532 return ret;
533}
534
535static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
536 int div, bool explicit)
537{
538 pm_runtime_get_sync(mcasp->dev);
539 switch (div_id) {
540 case MCASP_CLKDIV_AUXCLK:
541 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
542 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
543 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
544 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
545 break;
546
547 case MCASP_CLKDIV_BCLK:
548 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
549 ACLKXDIV(div - 1), ACLKXDIV_MASK);
550 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
551 ACLKRDIV(div - 1), ACLKRDIV_MASK);
552 if (explicit)
553 mcasp->bclk_div = div;
554 break;
555
556 case MCASP_CLKDIV_BCLK_FS_RATIO:
557
558
559
560
561
562
563
564
565
566
567 mcasp->slot_width = div / mcasp->tdm_slots;
568 if (div % mcasp->tdm_slots)
569 dev_warn(mcasp->dev,
570 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
571 __func__, div, mcasp->tdm_slots);
572 break;
573
574 default:
575 return -EINVAL;
576 }
577
578 pm_runtime_put(mcasp->dev);
579 return 0;
580}
581
582static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
583 int div)
584{
585 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
586
587 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
588}
589
590static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
591 unsigned int freq, int dir)
592{
593 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
594
595 pm_runtime_get_sync(mcasp->dev);
596 if (dir == SND_SOC_CLOCK_OUT) {
597 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
598 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
599 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
600 } else {
601 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
602 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
603 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
604 }
605
606 mcasp->sysclk_freq = freq;
607
608 pm_runtime_put(mcasp->dev);
609 return 0;
610}
611
612
613static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
614 int serializers)
615{
616 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
617 unsigned int *list = (unsigned int *) cl->list;
618 int slots = mcasp->tdm_slots;
619 int i, count = 0;
620
621 if (mcasp->tdm_mask[stream])
622 slots = hweight32(mcasp->tdm_mask[stream]);
623
624 for (i = 1; i <= slots; i++)
625 list[count++] = i;
626
627 for (i = 2; i <= serializers; i++)
628 list[count++] = i*slots;
629
630 cl->count = count;
631
632 return 0;
633}
634
635static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
636{
637 int rx_serializers = 0, tx_serializers = 0, ret, i;
638
639 for (i = 0; i < mcasp->num_serializer; i++)
640 if (mcasp->serial_dir[i] == TX_MODE)
641 tx_serializers++;
642 else if (mcasp->serial_dir[i] == RX_MODE)
643 rx_serializers++;
644
645 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
646 tx_serializers);
647 if (ret)
648 return ret;
649
650 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
651 rx_serializers);
652
653 return ret;
654}
655
656
657static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
658 unsigned int tx_mask,
659 unsigned int rx_mask,
660 int slots, int slot_width)
661{
662 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
663
664 dev_dbg(mcasp->dev,
665 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
666 __func__, tx_mask, rx_mask, slots, slot_width);
667
668 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
669 dev_err(mcasp->dev,
670 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
671 tx_mask, rx_mask, slots);
672 return -EINVAL;
673 }
674
675 if (slot_width &&
676 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
677 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
678 __func__, slot_width);
679 return -EINVAL;
680 }
681
682 mcasp->tdm_slots = slots;
683 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
684 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
685 mcasp->slot_width = slot_width;
686
687 return davinci_mcasp_set_ch_constraints(mcasp);
688}
689
690static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
691 int sample_width)
692{
693 u32 fmt;
694 u32 tx_rotate = (sample_width / 4) & 0x7;
695 u32 mask = (1ULL << sample_width) - 1;
696 u32 slot_width = sample_width;
697
698
699
700
701
702
703
704
705
706
707 u32 rx_rotate = 0;
708
709
710
711
712
713
714
715 if (mcasp->slot_width) {
716
717
718
719
720
721 slot_width = mcasp->slot_width;
722 rx_rotate = (slot_width - sample_width) / 4;
723 }
724
725
726 fmt = (slot_width >> 1) - 1;
727
728 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
729 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
730 RXSSZ(0x0F));
731 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
732 TXSSZ(0x0F));
733 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
734 TXROT(7));
735 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
736 RXROT(7));
737 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
738 }
739
740 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
741
742 return 0;
743}
744
745static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
746 int period_words, int channels)
747{
748 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
749 int i;
750 u8 tx_ser = 0;
751 u8 rx_ser = 0;
752 u8 slots = mcasp->tdm_slots;
753 u8 max_active_serializers = (channels + slots - 1) / slots;
754 int active_serializers, numevt;
755 u32 reg;
756
757 if (mcasp->version < MCASP_VERSION_3)
758 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
759
760
761 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
762
763 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
764 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
765 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
766 } else {
767 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
768 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
769 }
770
771 for (i = 0; i < mcasp->num_serializer; i++) {
772 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
773 mcasp->serial_dir[i]);
774 if (mcasp->serial_dir[i] == TX_MODE &&
775 tx_ser < max_active_serializers) {
776 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
777 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
778 DISMOD_LOW, DISMOD_MASK);
779 tx_ser++;
780 } else if (mcasp->serial_dir[i] == RX_MODE &&
781 rx_ser < max_active_serializers) {
782 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
783 rx_ser++;
784 } else if (mcasp->serial_dir[i] == INACTIVE_MODE) {
785 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
786 SRMOD_INACTIVE, SRMOD_MASK);
787 }
788 }
789
790 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
791 active_serializers = tx_ser;
792 numevt = mcasp->txnumevt;
793 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
794 } else {
795 active_serializers = rx_ser;
796 numevt = mcasp->rxnumevt;
797 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
798 }
799
800 if (active_serializers < max_active_serializers) {
801 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
802 "enabled in mcasp (%d)\n", channels,
803 active_serializers * slots);
804 return -EINVAL;
805 }
806
807
808 if (!numevt) {
809
810 if (active_serializers > 1) {
811
812
813
814
815
816
817 dma_data->maxburst = active_serializers;
818 } else {
819 dma_data->maxburst = 0;
820 }
821 return 0;
822 }
823
824 if (period_words % active_serializers) {
825 dev_err(mcasp->dev, "Invalid combination of period words and "
826 "active serializers: %d, %d\n", period_words,
827 active_serializers);
828 return -EINVAL;
829 }
830
831
832
833
834
835
836 numevt = (numevt / active_serializers) * active_serializers;
837
838 while (period_words % numevt && numevt > 0)
839 numevt -= active_serializers;
840 if (numevt <= 0)
841 numevt = active_serializers;
842
843 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
844 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
845
846
847 if (numevt == 1)
848 numevt = 0;
849 dma_data->maxburst = numevt;
850
851 return 0;
852}
853
854static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
855 int channels)
856{
857 int i, active_slots;
858 int total_slots;
859 int active_serializers;
860 u32 mask = 0;
861 u32 busel = 0;
862
863 total_slots = mcasp->tdm_slots;
864
865
866
867
868
869
870
871 if (mcasp->tdm_mask[stream]) {
872 active_slots = hweight32(mcasp->tdm_mask[stream]);
873 active_serializers = (channels + active_slots - 1) /
874 active_slots;
875 if (active_serializers == 1) {
876 active_slots = channels;
877 for (i = 0; i < total_slots; i++) {
878 if ((1 << i) & mcasp->tdm_mask[stream]) {
879 mask |= (1 << i);
880 if (--active_slots <= 0)
881 break;
882 }
883 }
884 }
885 } else {
886 active_serializers = (channels + total_slots - 1) / total_slots;
887 if (active_serializers == 1)
888 active_slots = channels;
889 else
890 active_slots = total_slots;
891
892 for (i = 0; i < active_slots; i++)
893 mask |= (1 << i);
894 }
895 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
896
897 if (!mcasp->dat_port)
898 busel = TXSEL;
899
900 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
901 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
902 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
903 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
904 FSXMOD(total_slots), FSXMOD(0x1FF));
905 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
906 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
907 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
908 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
909 FSRMOD(total_slots), FSRMOD(0x1FF));
910
911
912
913
914
915 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
916 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
917 FSXMOD(total_slots), FSXMOD(0x1FF));
918 }
919
920 return 0;
921}
922
923
924static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
925 unsigned int rate)
926{
927 u32 cs_value = 0;
928 u8 *cs_bytes = (u8*) &cs_value;
929
930
931
932 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
933
934
935 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
936
937
938 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
939
940
941 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
942
943 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
944
945
946 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
947
948
949 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
950
951
952 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
953 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
954
955 switch (rate) {
956 case 22050:
957 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
958 break;
959 case 24000:
960 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
961 break;
962 case 32000:
963 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
964 break;
965 case 44100:
966 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
967 break;
968 case 48000:
969 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
970 break;
971 case 88200:
972 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
973 break;
974 case 96000:
975 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
976 break;
977 case 176400:
978 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
979 break;
980 case 192000:
981 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
982 break;
983 default:
984 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
985 return -EINVAL;
986 }
987
988 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
989 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
990
991 return 0;
992}
993
994static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
995 unsigned int bclk_freq, bool set)
996{
997 int error_ppm;
998 unsigned int sysclk_freq = mcasp->sysclk_freq;
999 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1000 int div = sysclk_freq / bclk_freq;
1001 int rem = sysclk_freq % bclk_freq;
1002 int aux_div = 1;
1003
1004 if (div > (ACLKXDIV_MASK + 1)) {
1005 if (reg & AHCLKXE) {
1006 aux_div = div / (ACLKXDIV_MASK + 1);
1007 if (div % (ACLKXDIV_MASK + 1))
1008 aux_div++;
1009
1010 sysclk_freq /= aux_div;
1011 div = sysclk_freq / bclk_freq;
1012 rem = sysclk_freq % bclk_freq;
1013 } else if (set) {
1014 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1015 sysclk_freq);
1016 }
1017 }
1018
1019 if (rem != 0) {
1020 if (div == 0 ||
1021 ((sysclk_freq / div) - bclk_freq) >
1022 (bclk_freq - (sysclk_freq / (div+1)))) {
1023 div++;
1024 rem = rem - bclk_freq;
1025 }
1026 }
1027 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1028 (int)bclk_freq)) / div - 1000000;
1029
1030 if (set) {
1031 if (error_ppm)
1032 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1033 error_ppm);
1034
1035 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1036 if (reg & AHCLKXE)
1037 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1038 aux_div, 0);
1039 }
1040
1041 return error_ppm;
1042}
1043
1044static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1045{
1046 if (!mcasp->txnumevt)
1047 return 0;
1048
1049 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1050}
1051
1052static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1053{
1054 if (!mcasp->rxnumevt)
1055 return 0;
1056
1057 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1058}
1059
1060static snd_pcm_sframes_t davinci_mcasp_delay(
1061 struct snd_pcm_substream *substream,
1062 struct snd_soc_dai *cpu_dai)
1063{
1064 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1065 u32 fifo_use;
1066
1067 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1068 fifo_use = davinci_mcasp_tx_delay(mcasp);
1069 else
1070 fifo_use = davinci_mcasp_rx_delay(mcasp);
1071
1072
1073
1074
1075
1076
1077 return fifo_use / substream->runtime->channels;
1078}
1079
1080static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1081 struct snd_pcm_hw_params *params,
1082 struct snd_soc_dai *cpu_dai)
1083{
1084 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1085 int word_length;
1086 int channels = params_channels(params);
1087 int period_size = params_period_size(params);
1088 int ret;
1089
1090 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1091 if (ret)
1092 return ret;
1093
1094
1095
1096
1097
1098 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1099 int slots = mcasp->tdm_slots;
1100 int rate = params_rate(params);
1101 int sbits = params_width(params);
1102
1103 if (mcasp->slot_width)
1104 sbits = mcasp->slot_width;
1105
1106 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
1107 }
1108
1109 ret = mcasp_common_hw_param(mcasp, substream->stream,
1110 period_size * channels, channels);
1111 if (ret)
1112 return ret;
1113
1114 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1115 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1116 else
1117 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1118 channels);
1119
1120 if (ret)
1121 return ret;
1122
1123 switch (params_format(params)) {
1124 case SNDRV_PCM_FORMAT_U8:
1125 case SNDRV_PCM_FORMAT_S8:
1126 word_length = 8;
1127 break;
1128
1129 case SNDRV_PCM_FORMAT_U16_LE:
1130 case SNDRV_PCM_FORMAT_S16_LE:
1131 word_length = 16;
1132 break;
1133
1134 case SNDRV_PCM_FORMAT_U24_3LE:
1135 case SNDRV_PCM_FORMAT_S24_3LE:
1136 word_length = 24;
1137 break;
1138
1139 case SNDRV_PCM_FORMAT_U24_LE:
1140 case SNDRV_PCM_FORMAT_S24_LE:
1141 word_length = 24;
1142 break;
1143
1144 case SNDRV_PCM_FORMAT_U32_LE:
1145 case SNDRV_PCM_FORMAT_S32_LE:
1146 word_length = 32;
1147 break;
1148
1149 default:
1150 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1151 return -EINVAL;
1152 }
1153
1154 davinci_config_channel_size(mcasp, word_length);
1155
1156 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1157 mcasp->channels = channels;
1158
1159 return 0;
1160}
1161
1162static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1163 int cmd, struct snd_soc_dai *cpu_dai)
1164{
1165 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1166 int ret = 0;
1167
1168 switch (cmd) {
1169 case SNDRV_PCM_TRIGGER_RESUME:
1170 case SNDRV_PCM_TRIGGER_START:
1171 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1172 davinci_mcasp_start(mcasp, substream->stream);
1173 break;
1174 case SNDRV_PCM_TRIGGER_SUSPEND:
1175 case SNDRV_PCM_TRIGGER_STOP:
1176 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1177 davinci_mcasp_stop(mcasp, substream->stream);
1178 break;
1179
1180 default:
1181 ret = -EINVAL;
1182 }
1183
1184 return ret;
1185}
1186
1187static const unsigned int davinci_mcasp_dai_rates[] = {
1188 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1189 88200, 96000, 176400, 192000,
1190};
1191
1192#define DAVINCI_MAX_RATE_ERROR_PPM 1000
1193
1194static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1195 struct snd_pcm_hw_rule *rule)
1196{
1197 struct davinci_mcasp_ruledata *rd = rule->private;
1198 struct snd_interval *ri =
1199 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1200 int sbits = params_width(params);
1201 int slots = rd->mcasp->tdm_slots;
1202 struct snd_interval range;
1203 int i;
1204
1205 if (rd->mcasp->slot_width)
1206 sbits = rd->mcasp->slot_width;
1207
1208 snd_interval_any(&range);
1209 range.empty = 1;
1210
1211 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1212 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1213 uint bclk_freq = sbits*slots*
1214 davinci_mcasp_dai_rates[i];
1215 int ppm;
1216
1217 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
1218 false);
1219 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1220 if (range.empty) {
1221 range.min = davinci_mcasp_dai_rates[i];
1222 range.empty = 0;
1223 }
1224 range.max = davinci_mcasp_dai_rates[i];
1225 }
1226 }
1227 }
1228
1229 dev_dbg(rd->mcasp->dev,
1230 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1231 ri->min, ri->max, range.min, range.max, sbits, slots);
1232
1233 return snd_interval_refine(hw_param_interval(params, rule->var),
1234 &range);
1235}
1236
1237static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1238 struct snd_pcm_hw_rule *rule)
1239{
1240 struct davinci_mcasp_ruledata *rd = rule->private;
1241 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1242 struct snd_mask nfmt;
1243 int rate = params_rate(params);
1244 int slots = rd->mcasp->tdm_slots;
1245 int i, count = 0;
1246
1247 snd_mask_none(&nfmt);
1248
1249 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1250 if (snd_mask_test(fmt, i)) {
1251 uint sbits = snd_pcm_format_width(i);
1252 int ppm;
1253
1254 if (rd->mcasp->slot_width)
1255 sbits = rd->mcasp->slot_width;
1256
1257 ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
1258 sbits * slots * rate,
1259 false);
1260 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1261 snd_mask_set(&nfmt, i);
1262 count++;
1263 }
1264 }
1265 }
1266 dev_dbg(rd->mcasp->dev,
1267 "%d possible sample format for %d Hz and %d tdm slots\n",
1268 count, rate, slots);
1269
1270 return snd_mask_refine(fmt, &nfmt);
1271}
1272
1273static int davinci_mcasp_hw_rule_min_periodsize(
1274 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1275{
1276 struct snd_interval *period_size = hw_param_interval(params,
1277 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1278 struct snd_interval frames;
1279
1280 snd_interval_any(&frames);
1281 frames.min = 64;
1282 frames.integer = 1;
1283
1284 return snd_interval_refine(period_size, &frames);
1285}
1286
1287static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1288 struct snd_soc_dai *cpu_dai)
1289{
1290 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1291 struct davinci_mcasp_ruledata *ruledata =
1292 &mcasp->ruledata[substream->stream];
1293 u32 max_channels = 0;
1294 int i, dir;
1295 int tdm_slots = mcasp->tdm_slots;
1296
1297
1298 if (mcasp->substreams[substream->stream])
1299 return -EBUSY;
1300
1301 mcasp->substreams[substream->stream] = substream;
1302
1303 if (mcasp->tdm_mask[substream->stream])
1304 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1305
1306 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1307 return 0;
1308
1309
1310
1311
1312
1313 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1314 dir = TX_MODE;
1315 else
1316 dir = RX_MODE;
1317
1318 for (i = 0; i < mcasp->num_serializer; i++) {
1319 if (mcasp->serial_dir[i] == dir)
1320 max_channels++;
1321 }
1322 ruledata->serializers = max_channels;
1323 max_channels *= tdm_slots;
1324
1325
1326
1327
1328
1329
1330
1331 if (mcasp->channels && mcasp->channels < max_channels)
1332 max_channels = mcasp->channels;
1333
1334
1335
1336
1337 if (max_channels < tdm_slots)
1338 max_channels = tdm_slots;
1339
1340 snd_pcm_hw_constraint_minmax(substream->runtime,
1341 SNDRV_PCM_HW_PARAM_CHANNELS,
1342 0, max_channels);
1343
1344 snd_pcm_hw_constraint_list(substream->runtime,
1345 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1346 &mcasp->chconstr[substream->stream]);
1347
1348 if (mcasp->slot_width)
1349 snd_pcm_hw_constraint_minmax(substream->runtime,
1350 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1351 8, mcasp->slot_width);
1352
1353
1354
1355
1356
1357 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1358 int ret;
1359
1360 ruledata->mcasp = mcasp;
1361
1362 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1363 SNDRV_PCM_HW_PARAM_RATE,
1364 davinci_mcasp_hw_rule_rate,
1365 ruledata,
1366 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1367 if (ret)
1368 return ret;
1369 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1370 SNDRV_PCM_HW_PARAM_FORMAT,
1371 davinci_mcasp_hw_rule_format,
1372 ruledata,
1373 SNDRV_PCM_HW_PARAM_RATE, -1);
1374 if (ret)
1375 return ret;
1376 }
1377
1378 snd_pcm_hw_rule_add(substream->runtime, 0,
1379 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1380 davinci_mcasp_hw_rule_min_periodsize, NULL,
1381 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1382
1383 return 0;
1384}
1385
1386static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1387 struct snd_soc_dai *cpu_dai)
1388{
1389 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1390
1391 mcasp->substreams[substream->stream] = NULL;
1392
1393 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1394 return;
1395
1396 if (!cpu_dai->active)
1397 mcasp->channels = 0;
1398}
1399
1400static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1401 .startup = davinci_mcasp_startup,
1402 .shutdown = davinci_mcasp_shutdown,
1403 .trigger = davinci_mcasp_trigger,
1404 .delay = davinci_mcasp_delay,
1405 .hw_params = davinci_mcasp_hw_params,
1406 .set_fmt = davinci_mcasp_set_dai_fmt,
1407 .set_clkdiv = davinci_mcasp_set_clkdiv,
1408 .set_sysclk = davinci_mcasp_set_sysclk,
1409 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1410};
1411
1412static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1413{
1414 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1415
1416 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1417 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1418
1419 return 0;
1420}
1421
1422#ifdef CONFIG_PM_SLEEP
1423static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1424{
1425 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1426 struct davinci_mcasp_context *context = &mcasp->context;
1427 u32 reg;
1428 int i;
1429
1430 context->pm_state = pm_runtime_active(mcasp->dev);
1431 if (!context->pm_state)
1432 pm_runtime_get_sync(mcasp->dev);
1433
1434 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1435 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1436
1437 if (mcasp->txnumevt) {
1438 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1439 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1440 }
1441 if (mcasp->rxnumevt) {
1442 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1443 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1444 }
1445
1446 for (i = 0; i < mcasp->num_serializer; i++)
1447 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1448 DAVINCI_MCASP_XRSRCTL_REG(i));
1449
1450 pm_runtime_put_sync(mcasp->dev);
1451
1452 return 0;
1453}
1454
1455static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1456{
1457 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1458 struct davinci_mcasp_context *context = &mcasp->context;
1459 u32 reg;
1460 int i;
1461
1462 pm_runtime_get_sync(mcasp->dev);
1463
1464 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1465 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1466
1467 if (mcasp->txnumevt) {
1468 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1469 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1470 }
1471 if (mcasp->rxnumevt) {
1472 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1473 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1474 }
1475
1476 for (i = 0; i < mcasp->num_serializer; i++)
1477 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1478 context->xrsr_regs[i]);
1479
1480 if (!context->pm_state)
1481 pm_runtime_put_sync(mcasp->dev);
1482
1483 return 0;
1484}
1485#else
1486#define davinci_mcasp_suspend NULL
1487#define davinci_mcasp_resume NULL
1488#endif
1489
1490#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1491
1492#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1493 SNDRV_PCM_FMTBIT_U8 | \
1494 SNDRV_PCM_FMTBIT_S16_LE | \
1495 SNDRV_PCM_FMTBIT_U16_LE | \
1496 SNDRV_PCM_FMTBIT_S24_LE | \
1497 SNDRV_PCM_FMTBIT_U24_LE | \
1498 SNDRV_PCM_FMTBIT_S24_3LE | \
1499 SNDRV_PCM_FMTBIT_U24_3LE | \
1500 SNDRV_PCM_FMTBIT_S32_LE | \
1501 SNDRV_PCM_FMTBIT_U32_LE)
1502
1503static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1504 {
1505 .name = "davinci-mcasp.0",
1506 .probe = davinci_mcasp_dai_probe,
1507 .suspend = davinci_mcasp_suspend,
1508 .resume = davinci_mcasp_resume,
1509 .playback = {
1510 .channels_min = 1,
1511 .channels_max = 32 * 16,
1512 .rates = DAVINCI_MCASP_RATES,
1513 .formats = DAVINCI_MCASP_PCM_FMTS,
1514 },
1515 .capture = {
1516 .channels_min = 1,
1517 .channels_max = 32 * 16,
1518 .rates = DAVINCI_MCASP_RATES,
1519 .formats = DAVINCI_MCASP_PCM_FMTS,
1520 },
1521 .ops = &davinci_mcasp_dai_ops,
1522
1523 .symmetric_samplebits = 1,
1524 .symmetric_rates = 1,
1525 },
1526 {
1527 .name = "davinci-mcasp.1",
1528 .probe = davinci_mcasp_dai_probe,
1529 .playback = {
1530 .channels_min = 1,
1531 .channels_max = 384,
1532 .rates = DAVINCI_MCASP_RATES,
1533 .formats = DAVINCI_MCASP_PCM_FMTS,
1534 },
1535 .ops = &davinci_mcasp_dai_ops,
1536 },
1537
1538};
1539
1540static const struct snd_soc_component_driver davinci_mcasp_component = {
1541 .name = "davinci-mcasp",
1542};
1543
1544
1545static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1546 .tx_dma_offset = 0x400,
1547 .rx_dma_offset = 0x400,
1548 .version = MCASP_VERSION_1,
1549};
1550
1551static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1552 .tx_dma_offset = 0x2000,
1553 .rx_dma_offset = 0x2000,
1554 .version = MCASP_VERSION_2,
1555};
1556
1557static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1558 .tx_dma_offset = 0,
1559 .rx_dma_offset = 0,
1560 .version = MCASP_VERSION_3,
1561};
1562
1563static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1564
1565 .tx_dma_offset = 0,
1566 .rx_dma_offset = 0,
1567 .version = MCASP_VERSION_4,
1568};
1569
1570static const struct of_device_id mcasp_dt_ids[] = {
1571 {
1572 .compatible = "ti,dm646x-mcasp-audio",
1573 .data = &dm646x_mcasp_pdata,
1574 },
1575 {
1576 .compatible = "ti,da830-mcasp-audio",
1577 .data = &da830_mcasp_pdata,
1578 },
1579 {
1580 .compatible = "ti,am33xx-mcasp-audio",
1581 .data = &am33xx_mcasp_pdata,
1582 },
1583 {
1584 .compatible = "ti,dra7-mcasp-audio",
1585 .data = &dra7_mcasp_pdata,
1586 },
1587 { }
1588};
1589MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1590
1591static int mcasp_reparent_fck(struct platform_device *pdev)
1592{
1593 struct device_node *node = pdev->dev.of_node;
1594 struct clk *gfclk, *parent_clk;
1595 const char *parent_name;
1596 int ret;
1597
1598 if (!node)
1599 return 0;
1600
1601 parent_name = of_get_property(node, "fck_parent", NULL);
1602 if (!parent_name)
1603 return 0;
1604
1605 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1606
1607 gfclk = clk_get(&pdev->dev, "fck");
1608 if (IS_ERR(gfclk)) {
1609 dev_err(&pdev->dev, "failed to get fck\n");
1610 return PTR_ERR(gfclk);
1611 }
1612
1613 parent_clk = clk_get(NULL, parent_name);
1614 if (IS_ERR(parent_clk)) {
1615 dev_err(&pdev->dev, "failed to get parent clock\n");
1616 ret = PTR_ERR(parent_clk);
1617 goto err1;
1618 }
1619
1620 ret = clk_set_parent(gfclk, parent_clk);
1621 if (ret) {
1622 dev_err(&pdev->dev, "failed to reparent fck\n");
1623 goto err2;
1624 }
1625
1626err2:
1627 clk_put(parent_clk);
1628err1:
1629 clk_put(gfclk);
1630 return ret;
1631}
1632
1633static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1634 struct platform_device *pdev)
1635{
1636 struct device_node *np = pdev->dev.of_node;
1637 struct davinci_mcasp_pdata *pdata = NULL;
1638 const struct of_device_id *match =
1639 of_match_device(mcasp_dt_ids, &pdev->dev);
1640 struct of_phandle_args dma_spec;
1641
1642 const u32 *of_serial_dir32;
1643 u32 val;
1644 int i, ret = 0;
1645
1646 if (pdev->dev.platform_data) {
1647 pdata = pdev->dev.platform_data;
1648 return pdata;
1649 } else if (match) {
1650 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1651 GFP_KERNEL);
1652 if (!pdata) {
1653 ret = -ENOMEM;
1654 return pdata;
1655 }
1656 } else {
1657
1658 ret = -EINVAL;
1659 goto nodata;
1660 }
1661
1662 ret = of_property_read_u32(np, "op-mode", &val);
1663 if (ret >= 0)
1664 pdata->op_mode = val;
1665
1666 ret = of_property_read_u32(np, "tdm-slots", &val);
1667 if (ret >= 0) {
1668 if (val < 2 || val > 32) {
1669 dev_err(&pdev->dev,
1670 "tdm-slots must be in rage [2-32]\n");
1671 ret = -EINVAL;
1672 goto nodata;
1673 }
1674
1675 pdata->tdm_slots = val;
1676 }
1677
1678 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1679 val /= sizeof(u32);
1680 if (of_serial_dir32) {
1681 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1682 (sizeof(*of_serial_dir) * val),
1683 GFP_KERNEL);
1684 if (!of_serial_dir) {
1685 ret = -ENOMEM;
1686 goto nodata;
1687 }
1688
1689 for (i = 0; i < val; i++)
1690 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1691
1692 pdata->num_serializer = val;
1693 pdata->serial_dir = of_serial_dir;
1694 }
1695
1696 ret = of_property_match_string(np, "dma-names", "tx");
1697 if (ret < 0)
1698 goto nodata;
1699
1700 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1701 &dma_spec);
1702 if (ret < 0)
1703 goto nodata;
1704
1705 pdata->tx_dma_channel = dma_spec.args[0];
1706
1707
1708 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1709 ret = of_property_match_string(np, "dma-names", "rx");
1710 if (ret < 0)
1711 goto nodata;
1712
1713 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1714 &dma_spec);
1715 if (ret < 0)
1716 goto nodata;
1717
1718 pdata->rx_dma_channel = dma_spec.args[0];
1719 }
1720
1721 ret = of_property_read_u32(np, "tx-num-evt", &val);
1722 if (ret >= 0)
1723 pdata->txnumevt = val;
1724
1725 ret = of_property_read_u32(np, "rx-num-evt", &val);
1726 if (ret >= 0)
1727 pdata->rxnumevt = val;
1728
1729 ret = of_property_read_u32(np, "sram-size-playback", &val);
1730 if (ret >= 0)
1731 pdata->sram_size_playback = val;
1732
1733 ret = of_property_read_u32(np, "sram-size-capture", &val);
1734 if (ret >= 0)
1735 pdata->sram_size_capture = val;
1736
1737 return pdata;
1738
1739nodata:
1740 if (ret < 0) {
1741 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1742 ret);
1743 pdata = NULL;
1744 }
1745 return pdata;
1746}
1747
1748enum {
1749 PCM_EDMA,
1750 PCM_SDMA,
1751};
1752static const char *sdma_prefix = "ti,omap";
1753
1754static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1755{
1756 struct dma_chan *chan;
1757 const char *tmp;
1758 int ret = PCM_EDMA;
1759
1760 if (!mcasp->dev->of_node)
1761 return PCM_EDMA;
1762
1763 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1764 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1765 if (IS_ERR(chan)) {
1766 if (PTR_ERR(chan) != -EPROBE_DEFER)
1767 dev_err(mcasp->dev,
1768 "Can't verify DMA configuration (%ld)\n",
1769 PTR_ERR(chan));
1770 return PTR_ERR(chan);
1771 }
1772 if (WARN_ON(!chan->device || !chan->device->dev))
1773 return -EINVAL;
1774
1775 if (chan->device->dev->of_node)
1776 ret = of_property_read_string(chan->device->dev->of_node,
1777 "compatible", &tmp);
1778 else
1779 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1780
1781 dma_release_channel(chan);
1782 if (ret)
1783 return ret;
1784
1785 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1786 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1787 return PCM_SDMA;
1788
1789 return PCM_EDMA;
1790}
1791
1792static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1793{
1794 int i;
1795 u32 offset = 0;
1796
1797 if (pdata->version != MCASP_VERSION_4)
1798 return pdata->tx_dma_offset;
1799
1800 for (i = 0; i < pdata->num_serializer; i++) {
1801 if (pdata->serial_dir[i] == TX_MODE) {
1802 if (!offset) {
1803 offset = DAVINCI_MCASP_TXBUF_REG(i);
1804 } else {
1805 pr_err("%s: Only one serializer allowed!\n",
1806 __func__);
1807 break;
1808 }
1809 }
1810 }
1811
1812 return offset;
1813}
1814
1815static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1816{
1817 int i;
1818 u32 offset = 0;
1819
1820 if (pdata->version != MCASP_VERSION_4)
1821 return pdata->rx_dma_offset;
1822
1823 for (i = 0; i < pdata->num_serializer; i++) {
1824 if (pdata->serial_dir[i] == RX_MODE) {
1825 if (!offset) {
1826 offset = DAVINCI_MCASP_RXBUF_REG(i);
1827 } else {
1828 pr_err("%s: Only one serializer allowed!\n",
1829 __func__);
1830 break;
1831 }
1832 }
1833 }
1834
1835 return offset;
1836}
1837
1838static int davinci_mcasp_probe(struct platform_device *pdev)
1839{
1840 struct snd_dmaengine_dai_dma_data *dma_data;
1841 struct resource *mem, *res, *dat;
1842 struct davinci_mcasp_pdata *pdata;
1843 struct davinci_mcasp *mcasp;
1844 char *irq_name;
1845 int *dma;
1846 int irq;
1847 int ret;
1848
1849 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1850 dev_err(&pdev->dev, "No platform data supplied\n");
1851 return -EINVAL;
1852 }
1853
1854 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1855 GFP_KERNEL);
1856 if (!mcasp)
1857 return -ENOMEM;
1858
1859 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1860 if (!pdata) {
1861 dev_err(&pdev->dev, "no platform data\n");
1862 return -EINVAL;
1863 }
1864
1865 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1866 if (!mem) {
1867 dev_warn(mcasp->dev,
1868 "\"mpu\" mem resource not found, using index 0\n");
1869 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1870 if (!mem) {
1871 dev_err(&pdev->dev, "no mem resource?\n");
1872 return -ENODEV;
1873 }
1874 }
1875
1876 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1877 if (IS_ERR(mcasp->base))
1878 return PTR_ERR(mcasp->base);
1879
1880 pm_runtime_enable(&pdev->dev);
1881
1882 mcasp->op_mode = pdata->op_mode;
1883
1884 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1885 if (pdata->tdm_slots < 2) {
1886 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1887 pdata->tdm_slots);
1888 mcasp->tdm_slots = 2;
1889 } else if (pdata->tdm_slots > 32) {
1890 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1891 pdata->tdm_slots);
1892 mcasp->tdm_slots = 32;
1893 } else {
1894 mcasp->tdm_slots = pdata->tdm_slots;
1895 }
1896 }
1897
1898 mcasp->num_serializer = pdata->num_serializer;
1899#ifdef CONFIG_PM_SLEEP
1900 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
1901 mcasp->num_serializer, sizeof(u32),
1902 GFP_KERNEL);
1903 if (!mcasp->context.xrsr_regs) {
1904 ret = -ENOMEM;
1905 goto err;
1906 }
1907#endif
1908 mcasp->serial_dir = pdata->serial_dir;
1909 mcasp->version = pdata->version;
1910 mcasp->txnumevt = pdata->txnumevt;
1911 mcasp->rxnumevt = pdata->rxnumevt;
1912
1913 mcasp->dev = &pdev->dev;
1914
1915 irq = platform_get_irq_byname(pdev, "common");
1916 if (irq >= 0) {
1917 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1918 dev_name(&pdev->dev));
1919 if (!irq_name) {
1920 ret = -ENOMEM;
1921 goto err;
1922 }
1923 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1924 davinci_mcasp_common_irq_handler,
1925 IRQF_ONESHOT | IRQF_SHARED,
1926 irq_name, mcasp);
1927 if (ret) {
1928 dev_err(&pdev->dev, "common IRQ request failed\n");
1929 goto err;
1930 }
1931
1932 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1933 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1934 }
1935
1936 irq = platform_get_irq_byname(pdev, "rx");
1937 if (irq >= 0) {
1938 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1939 dev_name(&pdev->dev));
1940 if (!irq_name) {
1941 ret = -ENOMEM;
1942 goto err;
1943 }
1944 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1945 davinci_mcasp_rx_irq_handler,
1946 IRQF_ONESHOT, irq_name, mcasp);
1947 if (ret) {
1948 dev_err(&pdev->dev, "RX IRQ request failed\n");
1949 goto err;
1950 }
1951
1952 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1953 }
1954
1955 irq = platform_get_irq_byname(pdev, "tx");
1956 if (irq >= 0) {
1957 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1958 dev_name(&pdev->dev));
1959 if (!irq_name) {
1960 ret = -ENOMEM;
1961 goto err;
1962 }
1963 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1964 davinci_mcasp_tx_irq_handler,
1965 IRQF_ONESHOT, irq_name, mcasp);
1966 if (ret) {
1967 dev_err(&pdev->dev, "TX IRQ request failed\n");
1968 goto err;
1969 }
1970
1971 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1972 }
1973
1974 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1975 if (dat)
1976 mcasp->dat_port = true;
1977
1978 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1979 if (dat)
1980 dma_data->addr = dat->start;
1981 else
1982 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
1983
1984 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1985 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1986 if (res)
1987 *dma = res->start;
1988 else
1989 *dma = pdata->tx_dma_channel;
1990
1991
1992 if (pdev->dev.of_node)
1993 dma_data->filter_data = "tx";
1994 else
1995 dma_data->filter_data = dma;
1996
1997
1998 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1999 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2000 if (dat)
2001 dma_data->addr = dat->start;
2002 else
2003 dma_data->addr =
2004 mem->start + davinci_mcasp_rxdma_offset(pdata);
2005
2006 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
2007 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
2008 if (res)
2009 *dma = res->start;
2010 else
2011 *dma = pdata->rx_dma_channel;
2012
2013
2014 if (pdev->dev.of_node)
2015 dma_data->filter_data = "rx";
2016 else
2017 dma_data->filter_data = dma;
2018 }
2019
2020 if (mcasp->version < MCASP_VERSION_3) {
2021 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2022
2023 mcasp->dat_port = true;
2024 } else {
2025 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2026 }
2027
2028
2029
2030
2031
2032
2033
2034
2035 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2036 devm_kcalloc(mcasp->dev,
2037 32 + mcasp->num_serializer - 1,
2038 sizeof(unsigned int),
2039 GFP_KERNEL);
2040
2041 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2042 devm_kcalloc(mcasp->dev,
2043 32 + mcasp->num_serializer - 1,
2044 sizeof(unsigned int),
2045 GFP_KERNEL);
2046
2047 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2048 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2049 ret = -ENOMEM;
2050 goto err;
2051 }
2052
2053 ret = davinci_mcasp_set_ch_constraints(mcasp);
2054 if (ret)
2055 goto err;
2056
2057 dev_set_drvdata(&pdev->dev, mcasp);
2058
2059 mcasp_reparent_fck(pdev);
2060
2061 ret = devm_snd_soc_register_component(&pdev->dev,
2062 &davinci_mcasp_component,
2063 &davinci_mcasp_dai[pdata->op_mode], 1);
2064
2065 if (ret != 0)
2066 goto err;
2067
2068 ret = davinci_mcasp_get_dma_type(mcasp);
2069 switch (ret) {
2070 case PCM_EDMA:
2071#if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
2072 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2073 IS_MODULE(CONFIG_SND_EDMA_SOC))
2074 ret = edma_pcm_platform_register(&pdev->dev);
2075#else
2076 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
2077 ret = -EINVAL;
2078 goto err;
2079#endif
2080 break;
2081 case PCM_SDMA:
2082#if IS_BUILTIN(CONFIG_SND_SDMA_SOC) || \
2083 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2084 IS_MODULE(CONFIG_SND_SDMA_SOC))
2085 ret = sdma_pcm_platform_register(&pdev->dev, NULL, NULL);
2086#else
2087 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
2088 ret = -EINVAL;
2089 goto err;
2090#endif
2091 break;
2092 default:
2093 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2094 case -EPROBE_DEFER:
2095 goto err;
2096 break;
2097 }
2098
2099 if (ret) {
2100 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2101 goto err;
2102 }
2103
2104 return 0;
2105
2106err:
2107 pm_runtime_disable(&pdev->dev);
2108 return ret;
2109}
2110
2111static int davinci_mcasp_remove(struct platform_device *pdev)
2112{
2113 pm_runtime_disable(&pdev->dev);
2114
2115 return 0;
2116}
2117
2118static struct platform_driver davinci_mcasp_driver = {
2119 .probe = davinci_mcasp_probe,
2120 .remove = davinci_mcasp_remove,
2121 .driver = {
2122 .name = "davinci-mcasp",
2123 .of_match_table = mcasp_dt_ids,
2124 },
2125};
2126
2127module_platform_driver(davinci_mcasp_driver);
2128
2129MODULE_AUTHOR("Steve Chen");
2130MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2131MODULE_LICENSE("GPL");
2132
