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13#include <linux/module.h>
14#include <linux/mfd/syscon.h>
15#include <linux/delay.h>
16#include <linux/of_gpio.h>
17#include <linux/of_device.h>
18#include <linux/clk.h>
19#include <linux/pm_runtime.h>
20#include <linux/regmap.h>
21#include <sound/pcm_params.h>
22#include <sound/dmaengine_pcm.h>
23
24#include "rockchip_i2s.h"
25#include "rockchip_pcm.h"
26
27#define DRV_NAME "rockchip-i2s"
28
29struct rk_i2s_pins {
30 u32 reg_offset;
31 u32 shift;
32};
33
34struct rk_i2s_dev {
35 struct device *dev;
36
37 struct clk *hclk;
38 struct clk *mclk;
39
40 struct snd_dmaengine_dai_dma_data capture_dma_data;
41 struct snd_dmaengine_dai_dma_data playback_dma_data;
42
43 struct regmap *regmap;
44 struct regmap *grf;
45
46
47
48
49
50
51 bool tx_start;
52 bool rx_start;
53 bool is_master_mode;
54 const struct rk_i2s_pins *pins;
55};
56
57static int i2s_runtime_suspend(struct device *dev)
58{
59 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
60
61 regcache_cache_only(i2s->regmap, true);
62 clk_disable_unprepare(i2s->mclk);
63
64 return 0;
65}
66
67static int i2s_runtime_resume(struct device *dev)
68{
69 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
70 int ret;
71
72 ret = clk_prepare_enable(i2s->mclk);
73 if (ret) {
74 dev_err(i2s->dev, "clock enable failed %d\n", ret);
75 return ret;
76 }
77
78 regcache_cache_only(i2s->regmap, false);
79 regcache_mark_dirty(i2s->regmap);
80
81 ret = regcache_sync(i2s->regmap);
82 if (ret)
83 clk_disable_unprepare(i2s->mclk);
84
85 return ret;
86}
87
88static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
89{
90 return snd_soc_dai_get_drvdata(dai);
91}
92
93static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
94{
95 unsigned int val = 0;
96 int retry = 10;
97
98 if (on) {
99 regmap_update_bits(i2s->regmap, I2S_DMACR,
100 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
101
102 regmap_update_bits(i2s->regmap, I2S_XFER,
103 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
104 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
105
106 i2s->tx_start = true;
107 } else {
108 i2s->tx_start = false;
109
110 regmap_update_bits(i2s->regmap, I2S_DMACR,
111 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
112
113 if (!i2s->rx_start) {
114 regmap_update_bits(i2s->regmap, I2S_XFER,
115 I2S_XFER_TXS_START |
116 I2S_XFER_RXS_START,
117 I2S_XFER_TXS_STOP |
118 I2S_XFER_RXS_STOP);
119
120 udelay(150);
121 regmap_update_bits(i2s->regmap, I2S_CLR,
122 I2S_CLR_TXC | I2S_CLR_RXC,
123 I2S_CLR_TXC | I2S_CLR_RXC);
124
125 regmap_read(i2s->regmap, I2S_CLR, &val);
126
127
128 while (val) {
129 regmap_read(i2s->regmap, I2S_CLR, &val);
130 retry--;
131 if (!retry) {
132 dev_warn(i2s->dev, "fail to clear\n");
133 break;
134 }
135 }
136 }
137 }
138}
139
140static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
141{
142 unsigned int val = 0;
143 int retry = 10;
144
145 if (on) {
146 regmap_update_bits(i2s->regmap, I2S_DMACR,
147 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
148
149 regmap_update_bits(i2s->regmap, I2S_XFER,
150 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
151 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
152
153 i2s->rx_start = true;
154 } else {
155 i2s->rx_start = false;
156
157 regmap_update_bits(i2s->regmap, I2S_DMACR,
158 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
159
160 if (!i2s->tx_start) {
161 regmap_update_bits(i2s->regmap, I2S_XFER,
162 I2S_XFER_TXS_START |
163 I2S_XFER_RXS_START,
164 I2S_XFER_TXS_STOP |
165 I2S_XFER_RXS_STOP);
166
167 udelay(150);
168 regmap_update_bits(i2s->regmap, I2S_CLR,
169 I2S_CLR_TXC | I2S_CLR_RXC,
170 I2S_CLR_TXC | I2S_CLR_RXC);
171
172 regmap_read(i2s->regmap, I2S_CLR, &val);
173
174
175 while (val) {
176 regmap_read(i2s->regmap, I2S_CLR, &val);
177 retry--;
178 if (!retry) {
179 dev_warn(i2s->dev, "fail to clear\n");
180 break;
181 }
182 }
183 }
184 }
185}
186
187static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
188 unsigned int fmt)
189{
190 struct rk_i2s_dev *i2s = to_info(cpu_dai);
191 unsigned int mask = 0, val = 0;
192
193 mask = I2S_CKR_MSS_MASK;
194 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
195 case SND_SOC_DAIFMT_CBS_CFS:
196
197 val = I2S_CKR_MSS_MASTER;
198 i2s->is_master_mode = true;
199 break;
200 case SND_SOC_DAIFMT_CBM_CFM:
201 val = I2S_CKR_MSS_SLAVE;
202 i2s->is_master_mode = false;
203 break;
204 default:
205 return -EINVAL;
206 }
207
208 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
209
210 mask = I2S_CKR_CKP_MASK;
211 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
212 case SND_SOC_DAIFMT_NB_NF:
213 val = I2S_CKR_CKP_NEG;
214 break;
215 case SND_SOC_DAIFMT_IB_NF:
216 val = I2S_CKR_CKP_POS;
217 break;
218 default:
219 return -EINVAL;
220 }
221
222 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
223
224 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
225 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
226 case SND_SOC_DAIFMT_RIGHT_J:
227 val = I2S_TXCR_IBM_RSJM;
228 break;
229 case SND_SOC_DAIFMT_LEFT_J:
230 val = I2S_TXCR_IBM_LSJM;
231 break;
232 case SND_SOC_DAIFMT_I2S:
233 val = I2S_TXCR_IBM_NORMAL;
234 break;
235 case SND_SOC_DAIFMT_DSP_A:
236 val = I2S_TXCR_TFS_PCM;
237 break;
238 case SND_SOC_DAIFMT_DSP_B:
239 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
240 break;
241 default:
242 return -EINVAL;
243 }
244
245 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
246
247 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
248 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
249 case SND_SOC_DAIFMT_RIGHT_J:
250 val = I2S_RXCR_IBM_RSJM;
251 break;
252 case SND_SOC_DAIFMT_LEFT_J:
253 val = I2S_RXCR_IBM_LSJM;
254 break;
255 case SND_SOC_DAIFMT_I2S:
256 val = I2S_RXCR_IBM_NORMAL;
257 break;
258 case SND_SOC_DAIFMT_DSP_A:
259 val = I2S_RXCR_TFS_PCM;
260 break;
261 case SND_SOC_DAIFMT_DSP_B:
262 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
263 break;
264 default:
265 return -EINVAL;
266 }
267
268 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
269
270 return 0;
271}
272
273static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
274 struct snd_pcm_hw_params *params,
275 struct snd_soc_dai *dai)
276{
277 struct rk_i2s_dev *i2s = to_info(dai);
278 struct snd_soc_pcm_runtime *rtd = substream->private_data;
279 unsigned int val = 0;
280 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
281
282 if (i2s->is_master_mode) {
283 mclk_rate = clk_get_rate(i2s->mclk);
284 bclk_rate = 2 * 32 * params_rate(params);
285 if (bclk_rate && mclk_rate % bclk_rate)
286 return -EINVAL;
287
288 div_bclk = mclk_rate / bclk_rate;
289 div_lrck = bclk_rate / params_rate(params);
290 regmap_update_bits(i2s->regmap, I2S_CKR,
291 I2S_CKR_MDIV_MASK,
292 I2S_CKR_MDIV(div_bclk));
293
294 regmap_update_bits(i2s->regmap, I2S_CKR,
295 I2S_CKR_TSD_MASK |
296 I2S_CKR_RSD_MASK,
297 I2S_CKR_TSD(div_lrck) |
298 I2S_CKR_RSD(div_lrck));
299 }
300
301 switch (params_format(params)) {
302 case SNDRV_PCM_FORMAT_S8:
303 val |= I2S_TXCR_VDW(8);
304 break;
305 case SNDRV_PCM_FORMAT_S16_LE:
306 val |= I2S_TXCR_VDW(16);
307 break;
308 case SNDRV_PCM_FORMAT_S20_3LE:
309 val |= I2S_TXCR_VDW(20);
310 break;
311 case SNDRV_PCM_FORMAT_S24_LE:
312 val |= I2S_TXCR_VDW(24);
313 break;
314 case SNDRV_PCM_FORMAT_S32_LE:
315 val |= I2S_TXCR_VDW(32);
316 break;
317 default:
318 return -EINVAL;
319 }
320
321 switch (params_channels(params)) {
322 case 8:
323 val |= I2S_CHN_8;
324 break;
325 case 6:
326 val |= I2S_CHN_6;
327 break;
328 case 4:
329 val |= I2S_CHN_4;
330 break;
331 case 2:
332 case 1:
333 val |= I2S_CHN_2;
334 break;
335 default:
336 dev_err(i2s->dev, "invalid channel: %d\n",
337 params_channels(params));
338 return -EINVAL;
339 }
340
341 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
342 regmap_update_bits(i2s->regmap, I2S_RXCR,
343 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
344 val);
345 else
346 regmap_update_bits(i2s->regmap, I2S_TXCR,
347 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
348 val);
349
350 if (!IS_ERR(i2s->grf) && i2s->pins) {
351 regmap_read(i2s->regmap, I2S_TXCR, &val);
352 val &= I2S_TXCR_CSR_MASK;
353
354 switch (val) {
355 case I2S_CHN_4:
356 val = I2S_IO_4CH_OUT_6CH_IN;
357 break;
358 case I2S_CHN_6:
359 val = I2S_IO_6CH_OUT_4CH_IN;
360 break;
361 case I2S_CHN_8:
362 val = I2S_IO_8CH_OUT_2CH_IN;
363 break;
364 default:
365 val = I2S_IO_2CH_OUT_8CH_IN;
366 break;
367 }
368
369 val <<= i2s->pins->shift;
370 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
371 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
372 }
373
374 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
375 I2S_DMACR_TDL(16));
376 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
377 I2S_DMACR_RDL(16));
378
379 val = I2S_CKR_TRCM_TXRX;
380 if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
381 val = I2S_CKR_TRCM_TXONLY;
382
383 regmap_update_bits(i2s->regmap, I2S_CKR,
384 I2S_CKR_TRCM_MASK,
385 val);
386 return 0;
387}
388
389static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
390 int cmd, struct snd_soc_dai *dai)
391{
392 struct rk_i2s_dev *i2s = to_info(dai);
393 int ret = 0;
394
395 switch (cmd) {
396 case SNDRV_PCM_TRIGGER_START:
397 case SNDRV_PCM_TRIGGER_RESUME:
398 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
399 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
400 rockchip_snd_rxctrl(i2s, 1);
401 else
402 rockchip_snd_txctrl(i2s, 1);
403 break;
404 case SNDRV_PCM_TRIGGER_SUSPEND:
405 case SNDRV_PCM_TRIGGER_STOP:
406 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
407 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
408 rockchip_snd_rxctrl(i2s, 0);
409 else
410 rockchip_snd_txctrl(i2s, 0);
411 break;
412 default:
413 ret = -EINVAL;
414 break;
415 }
416
417 return ret;
418}
419
420static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
421 unsigned int freq, int dir)
422{
423 struct rk_i2s_dev *i2s = to_info(cpu_dai);
424 int ret;
425
426 ret = clk_set_rate(i2s->mclk, freq);
427 if (ret)
428 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
429
430 return ret;
431}
432
433static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
434{
435 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
436
437 dai->capture_dma_data = &i2s->capture_dma_data;
438 dai->playback_dma_data = &i2s->playback_dma_data;
439
440 return 0;
441}
442
443static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
444 .hw_params = rockchip_i2s_hw_params,
445 .set_sysclk = rockchip_i2s_set_sysclk,
446 .set_fmt = rockchip_i2s_set_fmt,
447 .trigger = rockchip_i2s_trigger,
448};
449
450static struct snd_soc_dai_driver rockchip_i2s_dai = {
451 .probe = rockchip_i2s_dai_probe,
452 .playback = {
453 .stream_name = "Playback",
454 .channels_min = 2,
455 .channels_max = 8,
456 .rates = SNDRV_PCM_RATE_8000_192000,
457 .formats = (SNDRV_PCM_FMTBIT_S8 |
458 SNDRV_PCM_FMTBIT_S16_LE |
459 SNDRV_PCM_FMTBIT_S20_3LE |
460 SNDRV_PCM_FMTBIT_S24_LE |
461 SNDRV_PCM_FMTBIT_S32_LE),
462 },
463 .capture = {
464 .stream_name = "Capture",
465 .channels_min = 1,
466 .channels_max = 2,
467 .rates = SNDRV_PCM_RATE_8000_192000,
468 .formats = (SNDRV_PCM_FMTBIT_S8 |
469 SNDRV_PCM_FMTBIT_S16_LE |
470 SNDRV_PCM_FMTBIT_S20_3LE |
471 SNDRV_PCM_FMTBIT_S24_LE |
472 SNDRV_PCM_FMTBIT_S32_LE),
473 },
474 .ops = &rockchip_i2s_dai_ops,
475 .symmetric_rates = 1,
476};
477
478static const struct snd_soc_component_driver rockchip_i2s_component = {
479 .name = DRV_NAME,
480};
481
482static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
483{
484 switch (reg) {
485 case I2S_TXCR:
486 case I2S_RXCR:
487 case I2S_CKR:
488 case I2S_DMACR:
489 case I2S_INTCR:
490 case I2S_XFER:
491 case I2S_CLR:
492 case I2S_TXDR:
493 return true;
494 default:
495 return false;
496 }
497}
498
499static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
500{
501 switch (reg) {
502 case I2S_TXCR:
503 case I2S_RXCR:
504 case I2S_CKR:
505 case I2S_DMACR:
506 case I2S_INTCR:
507 case I2S_XFER:
508 case I2S_CLR:
509 case I2S_TXDR:
510 case I2S_RXDR:
511 case I2S_FIFOLR:
512 case I2S_INTSR:
513 return true;
514 default:
515 return false;
516 }
517}
518
519static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
520{
521 switch (reg) {
522 case I2S_INTSR:
523 case I2S_CLR:
524 case I2S_FIFOLR:
525 case I2S_TXDR:
526 case I2S_RXDR:
527 return true;
528 default:
529 return false;
530 }
531}
532
533static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
534{
535 switch (reg) {
536 case I2S_RXDR:
537 return true;
538 default:
539 return false;
540 }
541}
542
543static const struct reg_default rockchip_i2s_reg_defaults[] = {
544 {0x00, 0x0000000f},
545 {0x04, 0x0000000f},
546 {0x08, 0x00071f1f},
547 {0x10, 0x001f0000},
548 {0x14, 0x01f00000},
549};
550
551static const struct regmap_config rockchip_i2s_regmap_config = {
552 .reg_bits = 32,
553 .reg_stride = 4,
554 .val_bits = 32,
555 .max_register = I2S_RXDR,
556 .reg_defaults = rockchip_i2s_reg_defaults,
557 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
558 .writeable_reg = rockchip_i2s_wr_reg,
559 .readable_reg = rockchip_i2s_rd_reg,
560 .volatile_reg = rockchip_i2s_volatile_reg,
561 .precious_reg = rockchip_i2s_precious_reg,
562 .cache_type = REGCACHE_FLAT,
563};
564
565static const struct rk_i2s_pins rk3399_i2s_pins = {
566 .reg_offset = 0xe220,
567 .shift = 11,
568};
569
570static const struct of_device_id rockchip_i2s_match[] = {
571 { .compatible = "rockchip,rk3066-i2s", },
572 { .compatible = "rockchip,rk3188-i2s", },
573 { .compatible = "rockchip,rk3288-i2s", },
574 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
575 {},
576};
577
578static int rockchip_i2s_probe(struct platform_device *pdev)
579{
580 struct device_node *node = pdev->dev.of_node;
581 const struct of_device_id *of_id;
582 struct rk_i2s_dev *i2s;
583 struct snd_soc_dai_driver *soc_dai;
584 struct resource *res;
585 void __iomem *regs;
586 int ret;
587 int val;
588
589 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
590 if (!i2s)
591 return -ENOMEM;
592
593 i2s->dev = &pdev->dev;
594
595 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
596 if (!IS_ERR(i2s->grf)) {
597 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
598 if (!of_id || !of_id->data)
599 return -EINVAL;
600
601 i2s->pins = of_id->data;
602 }
603
604
605 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
606 if (IS_ERR(i2s->hclk)) {
607 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
608 return PTR_ERR(i2s->hclk);
609 }
610 ret = clk_prepare_enable(i2s->hclk);
611 if (ret) {
612 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
613 return ret;
614 }
615
616 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
617 if (IS_ERR(i2s->mclk)) {
618 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
619 return PTR_ERR(i2s->mclk);
620 }
621
622 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
623 regs = devm_ioremap_resource(&pdev->dev, res);
624 if (IS_ERR(regs))
625 return PTR_ERR(regs);
626
627 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
628 &rockchip_i2s_regmap_config);
629 if (IS_ERR(i2s->regmap)) {
630 dev_err(&pdev->dev,
631 "Failed to initialise managed register map\n");
632 return PTR_ERR(i2s->regmap);
633 }
634
635 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
636 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
637 i2s->playback_dma_data.maxburst = 4;
638
639 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
640 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
641 i2s->capture_dma_data.maxburst = 4;
642
643 dev_set_drvdata(&pdev->dev, i2s);
644
645 pm_runtime_enable(&pdev->dev);
646 if (!pm_runtime_enabled(&pdev->dev)) {
647 ret = i2s_runtime_resume(&pdev->dev);
648 if (ret)
649 goto err_pm_disable;
650 }
651
652 soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai,
653 sizeof(*soc_dai), GFP_KERNEL);
654 if (!soc_dai) {
655 ret = -ENOMEM;
656 goto err_pm_disable;
657 }
658
659 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
660 if (val >= 2 && val <= 8)
661 soc_dai->playback.channels_max = val;
662 }
663
664 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
665 if (val >= 1 && val <= 8)
666 soc_dai->capture.channels_max = val;
667 }
668
669 ret = devm_snd_soc_register_component(&pdev->dev,
670 &rockchip_i2s_component,
671 soc_dai, 1);
672
673 if (ret) {
674 dev_err(&pdev->dev, "Could not register DAI\n");
675 goto err_suspend;
676 }
677
678 ret = rockchip_pcm_platform_register(&pdev->dev);
679 if (ret) {
680 dev_err(&pdev->dev, "Could not register PCM\n");
681 return ret;
682 }
683
684 return 0;
685
686err_suspend:
687 if (!pm_runtime_status_suspended(&pdev->dev))
688 i2s_runtime_suspend(&pdev->dev);
689err_pm_disable:
690 pm_runtime_disable(&pdev->dev);
691
692 return ret;
693}
694
695static int rockchip_i2s_remove(struct platform_device *pdev)
696{
697 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
698
699 pm_runtime_disable(&pdev->dev);
700 if (!pm_runtime_status_suspended(&pdev->dev))
701 i2s_runtime_suspend(&pdev->dev);
702
703 clk_disable_unprepare(i2s->hclk);
704
705 return 0;
706}
707
708static const struct dev_pm_ops rockchip_i2s_pm_ops = {
709 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
710 NULL)
711};
712
713static struct platform_driver rockchip_i2s_driver = {
714 .probe = rockchip_i2s_probe,
715 .remove = rockchip_i2s_remove,
716 .driver = {
717 .name = DRV_NAME,
718 .of_match_table = of_match_ptr(rockchip_i2s_match),
719 .pm = &rockchip_i2s_pm_ops,
720 },
721};
722module_platform_driver(rockchip_i2s_driver);
723
724MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
725MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
726MODULE_LICENSE("GPL v2");
727MODULE_ALIAS("platform:" DRV_NAME);
728MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
729
