LXR linux/arch/arm/kernel/entry-armv.S

   1/*
   2 *  linux/arch/arm/kernel/entry-armv.S
   3 *
   4 *  Copyright (C) 1996,1997,1998 Russell King.
   5 *  ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
   6 *  nommu support by Hyok S. Choi (hyok.choi@samsung.com)
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11 *
  12 *  Low-level vector interface routines
  13 *
  14 *  Note:  there is a StrongARM bug in the STMIA rn, {regs}^ instruction
  15 *  that causes it to save wrong values...  Be aware!
  16 */
  17
  18#include <linux/init.h>
  19
  20#include <asm/assembler.h>
  21#include <asm/memory.h>
  22#include <asm/glue-df.h>
  23#include <asm/glue-pf.h>
  24#include <asm/vfpmacros.h>
  25#ifndef CONFIG_MULTI_IRQ_HANDLER
  26#include <mach/entry-macro.S>
  27#endif
  28#include <asm/thread_notify.h>
  29#include <asm/unwind.h>
  30#include <asm/unistd.h>
  31#include <asm/tls.h>
  32#include <asm/system_info.h>
  33
  34#include "entry-header.S"
  35#include <asm/entry-macro-multi.S>
  36#include <asm/probes.h>
  37
  38/*
  39 * Interrupt handling.
  40 */
  41        .macro  irq_handler
  42#ifdef CONFIG_MULTI_IRQ_HANDLER
  43        ldr     r1, =handle_arch_irq
  44        mov     r0, sp
  45        badr    lr, 9997f
  46        ldr     pc, [r1]
  47#else
  48        arch_irq_handler_default
  49#endif
  509997:
  51        .endm
  52
  53        .macro  pabt_helper
  54        @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
  55#ifdef MULTI_PABORT
  56        ldr     ip, .LCprocfns
  57        mov     lr, pc
  58        ldr     pc, [ip, #PROCESSOR_PABT_FUNC]
  59#else
  60        bl      CPU_PABORT_HANDLER
  61#endif
  62        .endm
  63
  64        .macro  dabt_helper
  65
  66        @
  67        @ Call the processor-specific abort handler:
  68        @
  69        @  r2 - pt_regs
  70        @  r4 - aborted context pc
  71        @  r5 - aborted context psr
  72        @
  73        @ The abort handler must return the aborted address in r0, and
  74        @ the fault status register in r1.  r9 must be preserved.
  75        @
  76#ifdef MULTI_DABORT
  77        ldr     ip, .LCprocfns
  78        mov     lr, pc
  79        ldr     pc, [ip, #PROCESSOR_DABT_FUNC]
  80#else
  81        bl      CPU_DABORT_HANDLER
  82#endif
  83        .endm
  84
  85#ifdef CONFIG_KPROBES
  86        .section        .kprobes.text,"ax",%progbits
  87#else
  88        .text
  89#endif
  90
  91/*
  92 * Invalid mode handlers
  93 */
  94        .macro  inv_entry, reason
  95        sub     sp, sp, #S_FRAME_SIZE
  96 ARM(   stmib   sp, {r1 - lr}           )
  97 THUMB( stmia   sp, {r0 - r12}          )
  98 THUMB( str     sp, [sp, #S_SP]         )
  99 THUMB( str     lr, [sp, #S_LR]         )
 100        mov     r1, #\reason
 101        .endm
 102
 103__pabt_invalid:
 104        inv_entry BAD_PREFETCH
 105        b       common_invalid
 106ENDPROC(__pabt_invalid)
 107
 108__dabt_invalid:
 109        inv_entry BAD_DATA
 110        b       common_invalid
 111ENDPROC(__dabt_invalid)
 112
 113__irq_invalid:
 114        inv_entry BAD_IRQ
 115        b       common_invalid
 116ENDPROC(__irq_invalid)
 117
 118__und_invalid:
 119        inv_entry BAD_UNDEFINSTR
 120
 121        @
 122        @ XXX fall through to common_invalid
 123        @
 124
 125@
 126@ common_invalid - generic code for failed exception (re-entrant version of handlers)
 127@
 128common_invalid:
 129        zero_fp
 130
 131        ldmia   r0, {r4 - r6}
 132        add     r0, sp, #S_PC           @ here for interlock avoidance
 133        mov     r7, #-1                 @  ""   ""    ""        ""
 134        str     r4, [sp]                @ save preserved r0
 135        stmia   r0, {r5 - r7}           @ lr_<exception>,
 136                                        @ cpsr_<exception>, "old_r0"
 137
 138        mov     r0, sp
 139        b       bad_mode
 140ENDPROC(__und_invalid)
 141
 142/*
 143 * SVC mode handlers
 144 */
 145
 146#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
 147#define SPFIX(code...) code
 148#else
 149#define SPFIX(code...)
 150#endif
 151
 152        .macro  svc_entry, stack_hole=0, trace=1, uaccess=1
 153 UNWIND(.fnstart                )
 154 UNWIND(.save {r0 - pc}         )
 155        sub     sp, sp, #(S_FRAME_SIZE + 8 + \stack_hole - 4)
 156#ifdef CONFIG_THUMB2_KERNEL
 157 SPFIX( str     r0, [sp]        )       @ temporarily saved
 158 SPFIX( mov     r0, sp          )
 159 SPFIX( tst     r0, #4          )       @ test original stack alignment
 160 SPFIX( ldr     r0, [sp]        )       @ restored
 161#else
 162 SPFIX( tst     sp, #4          )
 163#endif
 164 SPFIX( subeq   sp, sp, #4      )
 165        stmia   sp, {r1 - r12}
 166
 167        ldmia   r0, {r3 - r5}
 168        add     r7, sp, #S_SP - 4       @ here for interlock avoidance
 169        mov     r6, #-1                 @  ""  ""      ""       ""
 170        add     r2, sp, #(S_FRAME_SIZE + 8 + \stack_hole - 4)
 171 SPFIX( addeq   r2, r2, #4      )
 172        str     r3, [sp, #-4]!          @ save the "real" r0 copied
 173                                        @ from the exception stack
 174
 175        mov     r3, lr
 176
 177        @
 178        @ We are now ready to fill in the remaining blanks on the stack:
 179        @
 180        @  r2 - sp_svc
 181        @  r3 - lr_svc
 182        @  r4 - lr_<exception>, already fixed up for correct return/restart
 183        @  r5 - spsr_<exception>
 184        @  r6 - orig_r0 (see pt_regs definition in ptrace.h)
 185        @
 186        stmia   r7, {r2 - r6}
 187
 188        uaccess_save r0
 189        .if \uaccess
 190        uaccess_disable r0
 191        .endif
 192
 193        .if \trace
 194#ifdef CONFIG_TRACE_IRQFLAGS
 195        bl      trace_hardirqs_off
 196#endif
 197        .endif
 198        .endm
 199
 200        .align  5
 201__dabt_svc:
 202        svc_entry uaccess=0
 203        mov     r2, sp
 204        dabt_helper
 205 THUMB( ldr     r5, [sp, #S_PSR]        )       @ potentially updated CPSR
 206        svc_exit r5                             @ return from exception
 207 UNWIND(.fnend          )
 208ENDPROC(__dabt_svc)
 209
 210        .align  5
 211__irq_svc:
 212        svc_entry
 213        irq_handler
 214
 215#ifdef CONFIG_PREEMPT
 216        get_thread_info tsk
 217        ldr     r8, [tsk, #TI_PREEMPT]          @ get preempt count
 218        ldr     r0, [tsk, #TI_FLAGS]            @ get flags
 219        teq     r8, #0                          @ if preempt count != 0
 220        movne   r0, #0                          @ force flags to 0
 221        tst     r0, #_TIF_NEED_RESCHED
 222        blne    svc_preempt
 223#endif
 224
 225        svc_exit r5, irq = 1                    @ return from exception
 226 UNWIND(.fnend          )
 227ENDPROC(__irq_svc)
 228
 229        .ltorg
 230
 231#ifdef CONFIG_PREEMPT
 232svc_preempt:
 233        mov     r8, lr
 2341:      bl      preempt_schedule_irq            @ irq en/disable is done inside
 235        ldr     r0, [tsk, #TI_FLAGS]            @ get new tasks TI_FLAGS
 236        tst     r0, #_TIF_NEED_RESCHED
 237        reteq   r8                              @ go again
 238        b       1b
 239#endif
 240
 241__und_fault:
 242        @ Correct the PC such that it is pointing at the instruction
 243        @ which caused the fault.  If the faulting instruction was ARM
 244        @ the PC will be pointing at the next instruction, and have to
 245        @ subtract 4.  Otherwise, it is Thumb, and the PC will be
 246        @ pointing at the second half of the Thumb instruction.  We
 247        @ have to subtract 2.
 248        ldr     r2, [r0, #S_PC]
 249        sub     r2, r2, r1
 250        str     r2, [r0, #S_PC]
 251        b       do_undefinstr
 252ENDPROC(__und_fault)
 253
 254        .align  5
 255__und_svc:
 256#ifdef CONFIG_KPROBES
 257        @ If a kprobe is about to simulate a "stmdb sp..." instruction,
 258        @ it obviously needs free stack space which then will belong to
 259        @ the saved context.
 260        svc_entry MAX_STACK_SIZE
 261#else
 262        svc_entry
 263#endif
 264        @
 265        @ call emulation code, which returns using r9 if it has emulated
 266        @ the instruction, or the more conventional lr if we are to treat
 267        @ this as a real undefined instruction
 268        @
 269        @  r0 - instruction
 270        @
 271#ifndef CONFIG_THUMB2_KERNEL
 272        ldr     r0, [r4, #-4]
 273#else
 274        mov     r1, #2
 275        ldrh    r0, [r4, #-2]                   @ Thumb instruction at LR - 2
 276        cmp     r0, #0xe800                     @ 32-bit instruction if xx >= 0
 277        blo     __und_svc_fault
 278        ldrh    r9, [r4]                        @ bottom 16 bits
 279        add     r4, r4, #2
 280        str     r4, [sp, #S_PC]
 281        orr     r0, r9, r0, lsl #16
 282#endif
 283        badr    r9, __und_svc_finish
 284        mov     r2, r4
 285        bl      call_fpe
 286
 287        mov     r1, #4                          @ PC correction to apply
 288__und_svc_fault:
 289        mov     r0, sp                          @ struct pt_regs *regs
 290        bl      __und_fault
 291
 292__und_svc_finish:
 293        ldr     r5, [sp, #S_PSR]                @ Get SVC cpsr
 294        svc_exit r5                             @ return from exception
 295 UNWIND(.fnend          )
 296ENDPROC(__und_svc)
 297
 298        .align  5
 299__pabt_svc:
 300        svc_entry
 301        mov     r2, sp                          @ regs
 302        pabt_helper
 303        svc_exit r5                             @ return from exception
 304 UNWIND(.fnend          )
 305ENDPROC(__pabt_svc)
 306
 307        .align  5
 308__fiq_svc:
 309        svc_entry trace=0
 310        mov     r0, sp                          @ struct pt_regs *regs
 311        bl      handle_fiq_as_nmi
 312        svc_exit_via_fiq
 313 UNWIND(.fnend          )
 314ENDPROC(__fiq_svc)
 315
 316        .align  5
 317.LCcralign:
 318        .word   cr_alignment
 319#ifdef MULTI_DABORT
 320.LCprocfns:
 321        .word   processor
 322#endif
 323.LCfp:
 324        .word   fp_enter
 325
 326/*
 327 * Abort mode handlers
 328 */
 329
 330@
 331@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
 332@ and reuses the same macros. However in abort mode we must also
 333@ save/restore lr_abt and spsr_abt to make nested aborts safe.
 334@
 335        .align 5
 336__fiq_abt:
 337        svc_entry trace=0
 338
 339 ARM(   msr     cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
 340 THUMB( mov     r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
 341 THUMB( msr     cpsr_c, r0 )
 342        mov     r1, lr          @ Save lr_abt
 343        mrs     r2, spsr        @ Save spsr_abt, abort is now safe
 344 ARM(   msr     cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
 345 THUMB( mov     r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
 346 THUMB( msr     cpsr_c, r0 )
 347        stmfd   sp!, {r1 - r2}
 348
 349        add     r0, sp, #8                      @ struct pt_regs *regs
 350        bl      handle_fiq_as_nmi
 351
 352        ldmfd   sp!, {r1 - r2}
 353 ARM(   msr     cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
 354 THUMB( mov     r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
 355 THUMB( msr     cpsr_c, r0 )
 356        mov     lr, r1          @ Restore lr_abt, abort is unsafe
 357        msr     spsr_cxsf, r2   @ Restore spsr_abt
 358 ARM(   msr     cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
 359 THUMB( mov     r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
 360 THUMB( msr     cpsr_c, r0 )
 361
 362        svc_exit_via_fiq
 363 UNWIND(.fnend          )
 364ENDPROC(__fiq_abt)
 365
 366/*
 367 * User mode handlers
 368 *
 369 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
 370 */
 371
 372#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
 373#error "sizeof(struct pt_regs) must be a multiple of 8"
 374#endif
 375
 376        .macro  usr_entry, trace=1, uaccess=1
 377 UNWIND(.fnstart        )
 378 UNWIND(.cantunwind     )       @ don't unwind the user space
 379        sub     sp, sp, #S_FRAME_SIZE
 380 ARM(   stmib   sp, {r1 - r12}  )
 381 THUMB( stmia   sp, {r0 - r12}  )
 382
 383 ATRAP( mrc     p15, 0, r7, c1, c0, 0)
 384 ATRAP( ldr     r8, .LCcralign)
 385
 386        ldmia   r0, {r3 - r5}
 387        add     r0, sp, #S_PC           @ here for interlock avoidance
 388        mov     r6, #-1                 @  ""  ""     ""        ""
 389
 390        str     r3, [sp]                @ save the "real" r0 copied
 391                                        @ from the exception stack
 392
 393 ATRAP( ldr     r8, [r8, #0])
 394
 395        @
 396        @ We are now ready to fill in the remaining blanks on the stack:
 397        @
 398        @  r4 - lr_<exception>, already fixed up for correct return/restart
 399        @  r5 - spsr_<exception>
 400        @  r6 - orig_r0 (see pt_regs definition in ptrace.h)
 401        @
 402        @ Also, separately save sp_usr and lr_usr
 403        @
 404        stmia   r0, {r4 - r6}
 405 ARM(   stmdb   r0, {sp, lr}^                   )
 406 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC    )
 407
 408        .if \uaccess
 409        uaccess_disable ip
 410        .endif
 411
 412        @ Enable the alignment trap while in kernel mode
 413 ATRAP( teq     r8, r7)
 414 ATRAP( mcrne   p15, 0, r8, c1, c0, 0)
 415
 416        @
 417        @ Clear FP to mark the first stack frame
 418        @
 419        zero_fp
 420
 421        .if     \trace
 422#ifdef CONFIG_TRACE_IRQFLAGS
 423        bl      trace_hardirqs_off
 424#endif
 425        ct_user_exit save = 0
 426        .endif
 427        .endm
 428
 429        .macro  kuser_cmpxchg_check
 430#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) && \
 431    !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
 432#ifndef CONFIG_MMU
 433#warning "NPTL on non MMU needs fixing"
 434#else
 435        @ Make sure our user space atomic helper is restarted
 436        @ if it was interrupted in a critical region.  Here we
 437        @ perform a quick test inline since it should be false
 438        @ 99.9999% of the time.  The rest is done out of line.
 439        cmp     r4, #TASK_SIZE
 440        blhs    kuser_cmpxchg64_fixup
 441#endif
 442#endif
 443        .endm
 444
 445        .align  5
 446__dabt_usr:
 447        usr_entry uaccess=0
 448        kuser_cmpxchg_check
 449        mov     r2, sp
 450        dabt_helper
 451        b       ret_from_exception
 452 UNWIND(.fnend          )
 453ENDPROC(__dabt_usr)
 454
 455        .align  5
 456__irq_usr:
 457        usr_entry
 458        kuser_cmpxchg_check
 459        irq_handler
 460        get_thread_info tsk
 461        mov     why, #0
 462        b       ret_to_user_from_irq
 463 UNWIND(.fnend          )
 464ENDPROC(__irq_usr)
 465
 466        .ltorg
 467
 468        .align  5
 469__und_usr:
 470        usr_entry uaccess=0
 471
 472        mov     r2, r4
 473        mov     r3, r5
 474
 475        @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
 476        @      faulting instruction depending on Thumb mode.
 477        @ r3 = regs->ARM_cpsr
 478        @
 479        @ The emulation code returns using r9 if it has emulated the
 480        @ instruction, or the more conventional lr if we are to treat
 481        @ this as a real undefined instruction
 482        @
 483        badr    r9, ret_from_exception
 484
 485        @ IRQs must be enabled before attempting to read the instruction from
 486        @ user space since that could cause a page/translation fault if the
 487        @ page table was modified by another CPU.
 488        enable_irq
 489
 490        tst     r3, #PSR_T_BIT                  @ Thumb mode?
 491        bne     __und_usr_thumb
 492        sub     r4, r2, #4                      @ ARM instr at LR - 4
 4931:      ldrt    r0, [r4]
 494 ARM_BE8(rev    r0, r0)                         @ little endian instruction
 495
 496        uaccess_disable ip
 497
 498        @ r0 = 32-bit ARM instruction which caused the exception
 499        @ r2 = PC value for the following instruction (:= regs->ARM_pc)
 500        @ r4 = PC value for the faulting instruction
 501        @ lr = 32-bit undefined instruction function
 502        badr    lr, __und_usr_fault_32
 503        b       call_fpe
 504
 505__und_usr_thumb:
 506        @ Thumb instruction
 507        sub     r4, r2, #2                      @ First half of thumb instr at LR - 2
 508#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
 509/*
 510 * Thumb-2 instruction handling.  Note that because pre-v6 and >= v6 platforms
 511 * can never be supported in a single kernel, this code is not applicable at
 512 * all when __LINUX_ARM_ARCH__ < 6.  This allows simplifying assumptions to be
 513 * made about .arch directives.
 514 */
 515#if __LINUX_ARM_ARCH__ < 7
 516/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
 517#define NEED_CPU_ARCHITECTURE
 518        ldr     r5, .LCcpu_architecture
 519        ldr     r5, [r5]
 520        cmp     r5, #CPU_ARCH_ARMv7
 521        blo     __und_usr_fault_16              @ 16bit undefined instruction
 522/*
 523 * The following code won't get run unless the running CPU really is v7, so
 524 * coding round the lack of ldrht on older arches is pointless.  Temporarily
 525 * override the assembler target arch with the minimum required instead:
 526 */
 527        .arch   armv6t2
 528#endif
 5292:      ldrht   r5, [r4]
 530ARM_BE8(rev16   r5, r5)                         @ little endian instruction
 531        cmp     r5, #0xe800                     @ 32bit instruction if xx != 0
 532        blo     __und_usr_fault_16_pan          @ 16bit undefined instruction
 5333:      ldrht   r0, [r2]
 534ARM_BE8(rev16   r0, r0)                         @ little endian instruction
 535        uaccess_disable ip
 536        add     r2, r2, #2                      @ r2 is PC + 2, make it PC + 4
 537        str     r2, [sp, #S_PC]                 @ it's a 2x16bit instr, update
 538        orr     r0, r0, r5, lsl #16
 539        badr    lr, __und_usr_fault_32
 540        @ r0 = the two 16-bit Thumb instructions which caused the exception
 541        @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
 542        @ r4 = PC value for the first 16-bit Thumb instruction
 543        @ lr = 32bit undefined instruction function
 544
 545#if __LINUX_ARM_ARCH__ < 7
 546/* If the target arch was overridden, change it back: */
 547#ifdef CONFIG_CPU_32v6K
 548        .arch   armv6k
 549#else
 550        .arch   armv6
 551#endif
 552#endif /* __LINUX_ARM_ARCH__ < 7 */
 553#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
 554        b       __und_usr_fault_16
 555#endif
 556 UNWIND(.fnend)
 557ENDPROC(__und_usr)
 558
 559/*
 560 * The out of line fixup for the ldrt instructions above.
 561 */
 562        .pushsection .text.fixup, "ax"
 563        .align  2
 5644:      str     r4, [sp, #S_PC]                 @ retry current instruction
 565        ret     r9
 566        .popsection
 567        .pushsection __ex_table,"a"
 568        .long   1b, 4b
 569#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
 570        .long   2b, 4b
 571        .long   3b, 4b
 572#endif
 573        .popsection
 574
 575/*
 576 * Check whether the instruction is a co-processor instruction.
 577 * If yes, we need to call the relevant co-processor handler.
 578 *
 579 * Note that we don't do a full check here for the co-processor
 580 * instructions; all instructions with bit 27 set are well
 581 * defined.  The only instructions that should fault are the
 582 * co-processor instructions.  However, we have to watch out
 583 * for the ARM6/ARM7 SWI bug.
 584 *
 585 * NEON is a special case that has to be handled here. Not all
 586 * NEON instructions are co-processor instructions, so we have
 587 * to make a special case of checking for them. Plus, there's
 588 * five groups of them, so we have a table of mask/opcode pairs
 589 * to check against, and if any match then we branch off into the
 590 * NEON handler code.
 591 *
 592 * Emulators may wish to make use of the following registers:
 593 *  r0  = instruction opcode (32-bit ARM or two 16-bit Thumb)
 594 *  r2  = PC value to resume execution after successful emulation
 595 *  r9  = normal "successful" return address
 596 *  r10 = this threads thread_info structure
 597 *  lr  = unrecognised instruction return address
 598 * IRQs enabled, FIQs enabled.
 599 */
 600        @
 601        @ Fall-through from Thumb-2 __und_usr
 602        @
 603#ifdef CONFIG_NEON
 604        get_thread_info r10                     @ get current thread
 605        adr     r6, .LCneon_thumb_opcodes
 606        b       2f
 607#endif
 608call_fpe:
 609        get_thread_info r10                     @ get current thread
 610#ifdef CONFIG_NEON
 611        adr     r6, .LCneon_arm_opcodes
 6122:      ldr     r5, [r6], #4                    @ mask value
 613        ldr     r7, [r6], #4                    @ opcode bits matching in mask
 614        cmp     r5, #0                          @ end mask?
 615        beq     1f
 616        and     r8, r0, r5
 617        cmp     r8, r7                          @ NEON instruction?
 618        bne     2b
 619        mov     r7, #1
 620        strb    r7, [r10, #TI_USED_CP + 10]     @ mark CP#10 as used
 621        strb    r7, [r10, #TI_USED_CP + 11]     @ mark CP#11 as used
 622        b       do_vfp                          @ let VFP handler handle this
 6231:
 624#endif
 625        tst     r0, #0x08000000                 @ only CDP/CPRT/LDC/STC have bit 27
 626        tstne   r0, #0x04000000                 @ bit 26 set on both ARM and Thumb-2
 627        reteq   lr
 628        and     r8, r0, #0x00000f00             @ mask out CP number
 629 THUMB( lsr     r8, r8, #8              )
 630        mov     r7, #1
 631        add     r6, r10, #TI_USED_CP
 632 ARM(   strb    r7, [r6, r8, lsr #8]    )       @ set appropriate used_cp[]
 633 THUMB( strb    r7, [r6, r8]            )       @ set appropriate used_cp[]
 634#ifdef CONFIG_IWMMXT
 635        @ Test if we need to give access to iWMMXt coprocessors
 636        ldr     r5, [r10, #TI_FLAGS]
 637        rsbs    r7, r8, #(1 << 8)               @ CP 0 or 1 only
 638        movcss  r7, r5, lsr #(TIF_USING_IWMMXT + 1)
 639        bcs     iwmmxt_task_enable
 640#endif
 641 ARM(   add     pc, pc, r8, lsr #6      )
 642 THUMB( lsl     r8, r8, #2              )
 643 THUMB( add     pc, r8                  )
 644        nop
 645
 646        ret.w   lr                              @ CP#0
 647        W(b)    do_fpe                          @ CP#1 (FPE)
 648        W(b)    do_fpe                          @ CP#2 (FPE)
 649        ret.w   lr                              @ CP#3
 650#ifdef CONFIG_CRUNCH
 651        b       crunch_task_enable              @ CP#4 (MaverickCrunch)
 652        b       crunch_task_enable              @ CP#5 (MaverickCrunch)
 653        b       crunch_task_enable              @ CP#6 (MaverickCrunch)
 654#else
 655        ret.w   lr                              @ CP#4
 656        ret.w   lr                              @ CP#5
 657        ret.w   lr                              @ CP#6
 658#endif
 659        ret.w   lr                              @ CP#7
 660        ret.w   lr                              @ CP#8
 661        ret.w   lr                              @ CP#9
 662#ifdef CONFIG_VFP
 663        W(b)    do_vfp                          @ CP#10 (VFP)
 664        W(b)    do_vfp                          @ CP#11 (VFP)
 665#else
 666        ret.w   lr                              @ CP#10 (VFP)
 667        ret.w   lr                              @ CP#11 (VFP)
 668#endif
 669        ret.w   lr                              @ CP#12
 670        ret.w   lr                              @ CP#13
 671        ret.w   lr                              @ CP#14 (Debug)
 672        ret.w   lr                              @ CP#15 (Control)
 673
 674#ifdef NEED_CPU_ARCHITECTURE
 675        .align  2
 676.LCcpu_architecture:
 677        .word   __cpu_architecture
 678#endif
 679
 680#ifdef CONFIG_NEON
 681        .align  6
 682
 683.LCneon_arm_opcodes:
 684        .word   0xfe000000                      @ mask
 685        .word   0xf2000000                      @ opcode
 686
 687        .word   0xff100000                      @ mask
 688        .word   0xf4000000                      @ opcode
 689
 690        .word   0x00000000                      @ mask
 691        .word   0x00000000                      @ opcode
 692
 693.LCneon_thumb_opcodes:
 694        .word   0xef000000                      @ mask
 695        .word   0xef000000                      @ opcode
 696
 697        .word   0xff100000                      @ mask
 698        .word   0xf9000000                      @ opcode
 699
 700        .word   0x00000000                      @ mask
 701        .word   0x00000000                      @ opcode
 702#endif
 703
 704do_fpe:
 705        ldr     r4, .LCfp
 706        add     r10, r10, #TI_FPSTATE           @ r10 = workspace
 707        ldr     pc, [r4]                        @ Call FP module USR entry point
 708
 709/*
 710 * The FP module is called with these registers set:
 711 *  r0  = instruction
 712 *  r2  = PC+4
 713 *  r9  = normal "successful" return address
 714 *  r10 = FP workspace
 715 *  lr  = unrecognised FP instruction return address
 716 */
 717
 718        .pushsection .data
 719ENTRY(fp_enter)
 720        .word   no_fp
 721        .popsection
 722
 723ENTRY(no_fp)
 724        ret     lr
 725ENDPROC(no_fp)
 726
 727__und_usr_fault_32:
 728        mov     r1, #4
 729        b       1f
 730__und_usr_fault_16_pan:
 731        uaccess_disable ip
 732__und_usr_fault_16:
 733        mov     r1, #2
 7341:      mov     r0, sp
 735        badr    lr, ret_from_exception
 736        b       __und_fault
 737ENDPROC(__und_usr_fault_32)
 738ENDPROC(__und_usr_fault_16)
 739
 740        .align  5
 741__pabt_usr:
 742        usr_entry
 743        mov     r2, sp                          @ regs
 744        pabt_helper
 745 UNWIND(.fnend          )
 746        /* fall through */
 747/*
 748 * This is the return code to user mode for abort handlers
 749 */
 750ENTRY(ret_from_exception)
 751 UNWIND(.fnstart        )
 752 UNWIND(.cantunwind     )
 753        get_thread_info tsk
 754        mov     why, #0
 755        b       ret_to_user
 756 UNWIND(.fnend          )
 757ENDPROC(__pabt_usr)
 758ENDPROC(ret_from_exception)
 759
 760        .align  5
 761__fiq_usr:
 762        usr_entry trace=0
 763        kuser_cmpxchg_check
 764        mov     r0, sp                          @ struct pt_regs *regs
 765        bl      handle_fiq_as_nmi
 766        get_thread_info tsk
 767        restore_user_regs fast = 0, offset = 0
 768 UNWIND(.fnend          )
 769ENDPROC(__fiq_usr)
 770
 771/*
 772 * Register switch for ARMv3 and ARMv4 processors
 773 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
 774 * previous and next are guaranteed not to be the same.
 775 */
 776ENTRY(__switch_to)
 777 UNWIND(.fnstart        )
 778 UNWIND(.cantunwind     )
 779        add     ip, r1, #TI_CPU_SAVE
 780 ARM(   stmia   ip!, {r4 - sl, fp, sp, lr} )    @ Store most regs on stack
 781 THUMB( stmia   ip!, {r4 - sl, fp}         )    @ Store most regs on stack
 782 THUMB( str     sp, [ip], #4               )
 783 THUMB( str     lr, [ip], #4               )
 784        ldr     r4, [r2, #TI_TP_VALUE]
 785        ldr     r5, [r2, #TI_TP_VALUE + 4]
 786#ifdef CONFIG_CPU_USE_DOMAINS
 787        mrc     p15, 0, r6, c3, c0, 0           @ Get domain register
 788        str     r6, [r1, #TI_CPU_DOMAIN]        @ Save old domain register
 789        ldr     r6, [r2, #TI_CPU_DOMAIN]
 790#endif
 791        switch_tls r1, r4, r5, r3, r7
 792#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 793        ldr     r7, [r2, #TI_TASK]
 794        ldr     r8, =__stack_chk_guard
 795        ldr     r7, [r7, #TSK_STACK_CANARY]
 796#endif
 797#ifdef CONFIG_CPU_USE_DOMAINS
 798        mcr     p15, 0, r6, c3, c0, 0           @ Set domain register
 799#endif
 800        mov     r5, r0
 801        add     r4, r2, #TI_CPU_SAVE
 802        ldr     r0, =thread_notify_head
 803        mov     r1, #THREAD_NOTIFY_SWITCH
 804        bl      atomic_notifier_call_chain
 805#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
 806        str     r7, [r8]
 807#endif
 808 THUMB( mov     ip, r4                     )
 809        mov     r0, r5
 810 ARM(   ldmia   r4, {r4 - sl, fp, sp, pc}  )    @ Load all regs saved previously
 811 THUMB( ldmia   ip!, {r4 - sl, fp}         )    @ Load all regs saved previously
 812 THUMB( ldr     sp, [ip], #4               )
 813 THUMB( ldr     pc, [ip]                   )
 814 UNWIND(.fnend          )
 815ENDPROC(__switch_to)
 816
 817        __INIT
 818
 819/*
 820 * User helpers.
 821 *
 822 * Each segment is 32-byte aligned and will be moved to the top of the high
 823 * vector page.  New segments (if ever needed) must be added in front of
 824 * existing ones.  This mechanism should be used only for things that are
 825 * really small and justified, and not be abused freely.
 826 *
 827 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
 828 */
 829 THUMB( .arm    )
 830
 831        .macro  usr_ret, reg
 832#ifdef CONFIG_ARM_THUMB
 833        bx      \reg
 834#else
 835        ret     \reg
 836#endif
 837        .endm
 838
 839        .macro  kuser_pad, sym, size
 840        .if     (. - \sym) & 3
 841        .rept   4 - (. - \sym) & 3
 842        .byte   0
 843        .endr
 844        .endif
 845        .rept   (\size - (. - \sym)) / 4
 846        .word   0xe7fddef1
 847        .endr
 848        .endm
 849
 850#ifdef CONFIG_KUSER_HELPERS
 851        .align  5
 852        .globl  __kuser_helper_start
 853__kuser_helper_start:
 854
 855/*
 856 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
 857 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
 858 */
 859
 860__kuser_cmpxchg64:                              @ 0xffff0f60
 861
 862#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
 863
 864        /*
 865         * Poor you.  No fast solution possible...
 866         * The kernel itself must perform the operation.
 867         * A special ghost syscall is used for that (see traps.c).
 868         */
 869        stmfd   sp!, {r7, lr}
 870        ldr     r7, 1f                  @ it's 20 bits
 871        swi     __ARM_NR_cmpxchg64
 872        ldmfd   sp!, {r7, pc}
 8731:      .word   __ARM_NR_cmpxchg64
 874
 875#elif defined(CONFIG_CPU_32v6K)
 876
 877        stmfd   sp!, {r4, r5, r6, r7}
 878        ldrd    r4, r5, [r0]                    @ load old val
 879        ldrd    r6, r7, [r1]                    @ load new val
 880        smp_dmb arm
 8811:      ldrexd  r0, r1, [r2]                    @ load current val
 882        eors    r3, r0, r4                      @ compare with oldval (1)
 883        eoreqs  r3, r1, r5                      @ compare with oldval (2)
 884        strexdeq r3, r6, r7, [r2]               @ store newval if eq
 885        teqeq   r3, #1                          @ success?
 886        beq     1b                              @ if no then retry
 887        smp_dmb arm
 888        rsbs    r0, r3, #0                      @ set returned val and C flag
 889        ldmfd   sp!, {r4, r5, r6, r7}
 890        usr_ret lr
 891
 892#elif !defined(CONFIG_SMP)
 893
 894#ifdef CONFIG_MMU
 895
 896        /*
 897         * The only thing that can break atomicity in this cmpxchg64
 898         * implementation is either an IRQ or a data abort exception
 899         * causing another process/thread to be scheduled in the middle of
 900         * the critical sequence.  The same strategy as for cmpxchg is used.
 901         */
 902        stmfd   sp!, {r4, r5, r6, lr}
 903        ldmia   r0, {r4, r5}                    @ load old val
 904        ldmia   r1, {r6, lr}                    @ load new val
 9051:      ldmia   r2, {r0, r1}                    @ load current val
 906        eors    r3, r0, r4                      @ compare with oldval (1)
 907        eoreqs  r3, r1, r5                      @ compare with oldval (2)
 9082:      stmeqia r2, {r6, lr}                    @ store newval if eq
 909        rsbs    r0, r3, #0                      @ set return val and C flag
 910        ldmfd   sp!, {r4, r5, r6, pc}
 911
 912        .text
 913kuser_cmpxchg64_fixup:
 914        @ Called from kuser_cmpxchg_fixup.
 915        @ r4 = address of interrupted insn (must be preserved).
 916        @ sp = saved regs. r7 and r8 are clobbered.
 917        @ 1b = first critical insn, 2b = last critical insn.
 918        @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
 919        mov     r7, #0xffff0fff
 920        sub     r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
 921        subs    r8, r4, r7
 922        rsbcss  r8, r8, #(2b - 1b)
 923        strcs   r7, [sp, #S_PC]
 924#if __LINUX_ARM_ARCH__ < 6
 925        bcc     kuser_cmpxchg32_fixup
 926#endif
 927        ret     lr
 928        .previous
 929
 930#else
 931#warning "NPTL on non MMU needs fixing"
 932        mov     r0, #-1
 933        adds    r0, r0, #0
 934        usr_ret lr
 935#endif
 936
 937#else
 938#error "incoherent kernel configuration"
 939#endif
 940
 941        kuser_pad __kuser_cmpxchg64, 64
 942
 943__kuser_memory_barrier:                         @ 0xffff0fa0
 944        smp_dmb arm
 945        usr_ret lr
 946
 947        kuser_pad __kuser_memory_barrier, 32
 948
 949__kuser_cmpxchg:                                @ 0xffff0fc0
 950
 951#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
 952
 953        /*
 954         * Poor you.  No fast solution possible...
 955         * The kernel itself must perform the operation.
 956         * A special ghost syscall is used for that (see traps.c).
 957         */
 958        stmfd   sp!, {r7, lr}
 959        ldr     r7, 1f                  @ it's 20 bits
 960        swi     __ARM_NR_cmpxchg
 961        ldmfd   sp!, {r7, pc}
 9621:      .word   __ARM_NR_cmpxchg
 963
 964#elif __LINUX_ARM_ARCH__ < 6
 965
 966#ifdef CONFIG_MMU
 967
 968        /*
 969         * The only thing that can break atomicity in this cmpxchg
 970         * implementation is either an IRQ or a data abort exception
 971         * causing another process/thread to be scheduled in the middle
 972         * of the critical sequence.  To prevent this, code is added to
 973         * the IRQ and data abort exception handlers to set the pc back
 974         * to the beginning of the critical section if it is found to be
 975         * within that critical section (see kuser_cmpxchg_fixup).
 976         */
 9771:      ldr     r3, [r2]                        @ load current val
 978        subs    r3, r3, r0                      @ compare with oldval
 9792:      streq   r1, [r2]                        @ store newval if eq
 980        rsbs    r0, r3, #0                      @ set return val and C flag
 981        usr_ret lr
 982
 983        .text
 984kuser_cmpxchg32_fixup:
 985        @ Called from kuser_cmpxchg_check macro.
 986        @ r4 = address of interrupted insn (must be preserved).
 987        @ sp = saved regs. r7 and r8 are clobbered.
 988        @ 1b = first critical insn, 2b = last critical insn.
 989        @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
 990        mov     r7, #0xffff0fff
 991        sub     r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
 992        subs    r8, r4, r7
 993        rsbcss  r8, r8, #(2b - 1b)
 994        strcs   r7, [sp, #S_PC]
 995        ret     lr
 996        .previous
 997
 998#else
 999#warning "NPTL on non MMU needs fixing"
1000        mov     r0, #-1

1001        adds    r0, r0, #0
1002        usr_ret lr
1003#endif
1004
1005#else
1006
1007        smp_dmb arm
10081:      ldrex   r3, [r2]
1009        subs    r3, r3, r0
1010        strexeq r3, r1, [r2]
1011        teqeq   r3, #1
1012        beq     1b
1013        rsbs    r0, r3, #0
1014        /* beware -- each __kuser slot must be 8 instructions max */
1015        ALT_SMP(b       __kuser_memory_barrier)
1016        ALT_UP(usr_ret  lr)
1017
1018#endif
1019
1020        kuser_pad __kuser_cmpxchg, 32
1021
1022__kuser_get_tls:                                @ 0xffff0fe0
1023        ldr     r0, [pc, #(16 - 8)]     @ read TLS, set in kuser_get_tls_init
1024        usr_ret lr
1025        mrc     p15, 0, r0, c13, c0, 3  @ 0xffff0fe8 hardware TLS code
1026        kuser_pad __kuser_get_tls, 16
1027        .rep    3
1028        .word   0                       @ 0xffff0ff0 software TLS value, then
1029        .endr                           @ pad up to __kuser_helper_version
1030
1031__kuser_helper_version:                         @ 0xffff0ffc
1032        .word   ((__kuser_helper_end - __kuser_helper_start) >> 5)
1033
1034        .globl  __kuser_helper_end
1035__kuser_helper_end:
1036
1037#endif
1038
1039 THUMB( .thumb  )
1040
1041/*
1042 * Vector stubs.
1043 *
1044 * This code is copied to 0xffff1000 so we can use branches in the
1045 * vectors, rather than ldr's.  Note that this code must not exceed
1046 * a page size.
1047 *
1048 * Common stub entry macro:
1049 *   Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1050 *
1051 * SP points to a minimal amount of processor-private memory, the address
1052 * of which is copied into r0 for the mode specific abort handler.
1053 */
1054        .macro  vector_stub, name, mode, correction=0
1055        .align  5
1056
1057vector_\name:
1058        .if \correction
1059        sub     lr, lr, #\correction
1060        .endif
1061
1062        @
1063        @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1064        @ (parent CPSR)
1065        @
1066        stmia   sp, {r0, lr}            @ save r0, lr
1067        mrs     lr, spsr
1068        str     lr, [sp, #8]            @ save spsr
1069
1070        @
1071        @ Prepare for SVC32 mode.  IRQs remain disabled.
1072        @
1073        mrs     r0, cpsr
1074        eor     r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1075        msr     spsr_cxsf, r0
1076
1077        @
1078        @ the branch table must immediately follow this code
1079        @
1080        and     lr, lr, #0x0f
1081 THUMB( adr     r0, 1f                  )
1082 THUMB( ldr     lr, [r0, lr, lsl #2]    )
1083        mov     r0, sp
1084 ARM(   ldr     lr, [pc, lr, lsl #2]    )
1085        movs    pc, lr                  @ branch to handler in SVC mode
1086ENDPROC(vector_\name)
1087
1088        .align  2
1089        @ handler addresses follow this label
10901:
1091        .endm
1092
1093        .section .stubs, "ax", %progbits
1094__stubs_start:
1095        @ This must be the first word
1096        .word   vector_swi
1097
1098vector_rst:
1099 ARM(   swi     SYS_ERROR0      )
1100 THUMB( svc     #0              )
1101 THUMB( nop                     )
1102        b       vector_und
1103
1104/*
1105 * Interrupt dispatcher
1106 */
1107        vector_stub     irq, IRQ_MODE, 4
1108
1109        .long   __irq_usr                       @  0  (USR_26 / USR_32)
1110        .long   __irq_invalid                   @  1  (FIQ_26 / FIQ_32)
1111        .long   __irq_invalid                   @  2  (IRQ_26 / IRQ_32)
1112        .long   __irq_svc                       @  3  (SVC_26 / SVC_32)
1113        .long   __irq_invalid                   @  4
1114        .long   __irq_invalid                   @  5
1115        .long   __irq_invalid                   @  6
1116        .long   __irq_invalid                   @  7
1117        .long   __irq_invalid                   @  8
1118        .long   __irq_invalid                   @  9
1119        .long   __irq_invalid                   @  a
1120        .long   __irq_invalid                   @  b
1121        .long   __irq_invalid                   @  c
1122        .long   __irq_invalid                   @  d
1123        .long   __irq_invalid                   @  e
1124        .long   __irq_invalid                   @  f
1125
1126/*
1127 * Data abort dispatcher
1128 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1129 */
1130        vector_stub     dabt, ABT_MODE, 8
1131
1132        .long   __dabt_usr                      @  0  (USR_26 / USR_32)
1133        .long   __dabt_invalid                  @  1  (FIQ_26 / FIQ_32)
1134        .long   __dabt_invalid                  @  2  (IRQ_26 / IRQ_32)
1135        .long   __dabt_svc                      @  3  (SVC_26 / SVC_32)
1136        .long   __dabt_invalid                  @  4
1137        .long   __dabt_invalid                  @  5
1138        .long   __dabt_invalid                  @  6
1139        .long   __dabt_invalid                  @  7
1140        .long   __dabt_invalid                  @  8
1141        .long   __dabt_invalid                  @  9
1142        .long   __dabt_invalid                  @  a
1143        .long   __dabt_invalid                  @  b
1144        .long   __dabt_invalid                  @  c
1145        .long   __dabt_invalid                  @  d
1146        .long   __dabt_invalid                  @  e
1147        .long   __dabt_invalid                  @  f
1148
1149/*
1150 * Prefetch abort dispatcher
1151 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1152 */
1153        vector_stub     pabt, ABT_MODE, 4
1154
1155        .long   __pabt_usr                      @  0 (USR_26 / USR_32)
1156        .long   __pabt_invalid                  @  1 (FIQ_26 / FIQ_32)
1157        .long   __pabt_invalid                  @  2 (IRQ_26 / IRQ_32)
1158        .long   __pabt_svc                      @  3 (SVC_26 / SVC_32)
1159        .long   __pabt_invalid                  @  4
1160        .long   __pabt_invalid                  @  5
1161        .long   __pabt_invalid                  @  6
1162        .long   __pabt_invalid                  @  7
1163        .long   __pabt_invalid                  @  8
1164        .long   __pabt_invalid                  @  9
1165        .long   __pabt_invalid                  @  a
1166        .long   __pabt_invalid                  @  b
1167        .long   __pabt_invalid                  @  c
1168        .long   __pabt_invalid                  @  d
1169        .long   __pabt_invalid                  @  e
1170        .long   __pabt_invalid                  @  f
1171
1172/*
1173 * Undef instr entry dispatcher
1174 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1175 */
1176        vector_stub     und, UND_MODE
1177
1178        .long   __und_usr                       @  0 (USR_26 / USR_32)
1179        .long   __und_invalid                   @  1 (FIQ_26 / FIQ_32)
1180        .long   __und_invalid                   @  2 (IRQ_26 / IRQ_32)
1181        .long   __und_svc                       @  3 (SVC_26 / SVC_32)
1182        .long   __und_invalid                   @  4
1183        .long   __und_invalid                   @  5
1184        .long   __und_invalid                   @  6
1185        .long   __und_invalid                   @  7
1186        .long   __und_invalid                   @  8
1187        .long   __und_invalid                   @  9
1188        .long   __und_invalid                   @  a
1189        .long   __und_invalid                   @  b
1190        .long   __und_invalid                   @  c
1191        .long   __und_invalid                   @  d
1192        .long   __und_invalid                   @  e
1193        .long   __und_invalid                   @  f
1194
1195        .align  5
1196
1197/*=============================================================================
1198 * Address exception handler
1199 *-----------------------------------------------------------------------------
1200 * These aren't too critical.
1201 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1202 */
1203
1204vector_addrexcptn:
1205        b       vector_addrexcptn
1206
1207/*=============================================================================
1208 * FIQ "NMI" handler
1209 *-----------------------------------------------------------------------------
1210 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
1211 * systems.
1212 */
1213        vector_stub     fiq, FIQ_MODE, 4
1214
1215        .long   __fiq_usr                       @  0  (USR_26 / USR_32)
1216        .long   __fiq_svc                       @  1  (FIQ_26 / FIQ_32)
1217        .long   __fiq_svc                       @  2  (IRQ_26 / IRQ_32)
1218        .long   __fiq_svc                       @  3  (SVC_26 / SVC_32)
1219        .long   __fiq_svc                       @  4
1220        .long   __fiq_svc                       @  5
1221        .long   __fiq_svc                       @  6
1222        .long   __fiq_abt                       @  7
1223        .long   __fiq_svc                       @  8
1224        .long   __fiq_svc                       @  9
1225        .long   __fiq_svc                       @  a
1226        .long   __fiq_svc                       @  b
1227        .long   __fiq_svc                       @  c
1228        .long   __fiq_svc                       @  d
1229        .long   __fiq_svc                       @  e
1230        .long   __fiq_svc                       @  f
1231
1232        .globl  vector_fiq_offset
1233        .equ    vector_fiq_offset, vector_fiq
1234
1235        .section .vectors, "ax", %progbits
1236__vectors_start:
1237        W(b)    vector_rst
1238        W(b)    vector_und
1239        W(ldr)  pc, __vectors_start + 0x1000
1240        W(b)    vector_pabt
1241        W(b)    vector_dabt
1242        W(b)    vector_addrexcptn
1243        W(b)    vector_irq
1244        W(b)    vector_fiq
1245
1246        .data
1247
1248        .globl  cr_alignment
1249cr_alignment:
1250        .space  4
1251
1252#ifdef CONFIG_MULTI_IRQ_HANDLER
1253        .globl  handle_arch_irq
1254handle_arch_irq:
1255        .space  4
1256#endif
1257