LXR linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S

   1/*
   2 *  linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
   3 *
   4 *  Based on  linux/arch/arm/lib/floppydma.S
   5 *  Renamed and modified to work with 2.6 kernel by Matt Callow
   6 *  Copyright (C) 1995, 1996 Russell King
   7 *  Copyright (C) 2004 Pete Trapps
   8 *  Copyright (C) 2006 Matt Callow
   9 *  Copyright (C) 2010 Janusz Krzysztofik
  10 *
  11 * This program is free software; you can redistribute it and/or modify it
  12 * under the terms of the GNU General Public License version 2
  13 * as published by the Free Software Foundation.
  14 */
  15
  16#include <linux/linkage.h>
  17#include <asm/assembler.h>
  18
  19#include <mach/board-ams-delta.h>
  20#include <mach/ams-delta-fiq.h>
  21
  22#include "iomap.h"
  23#include "soc.h"
  24
  25/*
  26 * GPIO related definitions, copied from arch/arm/plat-omap/gpio.c.
  27 * Unfortunately, those were not placed in a separate header file.
  28 */
  29#define OMAP1510_GPIO_BASE              0xFFFCE000
  30#define OMAP1510_GPIO_DATA_INPUT        0x00
  31#define OMAP1510_GPIO_DATA_OUTPUT       0x04
  32#define OMAP1510_GPIO_DIR_CONTROL       0x08
  33#define OMAP1510_GPIO_INT_CONTROL       0x0c
  34#define OMAP1510_GPIO_INT_MASK          0x10
  35#define OMAP1510_GPIO_INT_STATUS        0x14
  36#define OMAP1510_GPIO_PIN_CONTROL       0x18
  37
  38/* GPIO register bitmasks */
  39#define KEYBRD_DATA_MASK                (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_DATA)
  40#define KEYBRD_CLK_MASK                 (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_CLK)
  41#define MODEM_IRQ_MASK                  (0x1 << AMS_DELTA_GPIO_PIN_MODEM_IRQ)
  42#define HOOK_SWITCH_MASK                (0x1 << AMS_DELTA_GPIO_PIN_HOOK_SWITCH)
  43#define OTHERS_MASK                     (MODEM_IRQ_MASK | HOOK_SWITCH_MASK)
  44
  45/* IRQ handler register bitmasks */
  46#define DEFERRED_FIQ_MASK               (0x1 << (INT_DEFERRED_FIQ % IH2_BASE))
  47#define GPIO_BANK1_MASK                 (0x1 << INT_GPIO_BANK1)
  48
  49/* Driver buffer byte offsets */
  50#define BUF_MASK                        (FIQ_MASK * 4)
  51#define BUF_STATE                       (FIQ_STATE * 4)
  52#define BUF_KEYS_CNT                    (FIQ_KEYS_CNT * 4)
  53#define BUF_TAIL_OFFSET                 (FIQ_TAIL_OFFSET * 4)
  54#define BUF_HEAD_OFFSET                 (FIQ_HEAD_OFFSET * 4)
  55#define BUF_BUF_LEN                     (FIQ_BUF_LEN * 4)
  56#define BUF_KEY                         (FIQ_KEY * 4)
  57#define BUF_MISSED_KEYS                 (FIQ_MISSED_KEYS * 4)
  58#define BUF_BUFFER_START                (FIQ_BUFFER_START * 4)
  59#define BUF_GPIO_INT_MASK               (FIQ_GPIO_INT_MASK * 4)
  60#define BUF_KEYS_HICNT                  (FIQ_KEYS_HICNT * 4)
  61#define BUF_IRQ_PEND                    (FIQ_IRQ_PEND * 4)
  62#define BUF_SIR_CODE_L1                 (FIQ_SIR_CODE_L1 * 4)
  63#define BUF_SIR_CODE_L2                 (IRQ_SIR_CODE_L2 * 4)
  64#define BUF_CNT_INT_00                  (FIQ_CNT_INT_00 * 4)
  65#define BUF_CNT_INT_KEY                 (FIQ_CNT_INT_KEY * 4)
  66#define BUF_CNT_INT_MDM                 (FIQ_CNT_INT_MDM * 4)
  67#define BUF_CNT_INT_03                  (FIQ_CNT_INT_03 * 4)
  68#define BUF_CNT_INT_HSW                 (FIQ_CNT_INT_HSW * 4)
  69#define BUF_CNT_INT_05                  (FIQ_CNT_INT_05 * 4)
  70#define BUF_CNT_INT_06                  (FIQ_CNT_INT_06 * 4)
  71#define BUF_CNT_INT_07                  (FIQ_CNT_INT_07 * 4)
  72#define BUF_CNT_INT_08                  (FIQ_CNT_INT_08 * 4)
  73#define BUF_CNT_INT_09                  (FIQ_CNT_INT_09 * 4)
  74#define BUF_CNT_INT_10                  (FIQ_CNT_INT_10 * 4)
  75#define BUF_CNT_INT_11                  (FIQ_CNT_INT_11 * 4)
  76#define BUF_CNT_INT_12                  (FIQ_CNT_INT_12 * 4)
  77#define BUF_CNT_INT_13                  (FIQ_CNT_INT_13 * 4)
  78#define BUF_CNT_INT_14                  (FIQ_CNT_INT_14 * 4)
  79#define BUF_CNT_INT_15                  (FIQ_CNT_INT_15 * 4)
  80#define BUF_CIRC_BUFF                   (FIQ_CIRC_BUFF * 4)
  81
  82
  83/*
  84 * Register usage
  85 * r8  - temporary
  86 * r9  - the driver buffer
  87 * r10 - temporary
  88 * r11 - interrupts mask
  89 * r12 - base pointers
  90 * r13 - interrupts status
  91 */
  92
  93        .text
  94
  95        .global qwerty_fiqin_end
  96
  97ENTRY(qwerty_fiqin_start)
  98        @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
  99        @ FIQ intrrupt handler
 100        ldr r12, omap_ih1_base                  @ set pointer to level1 handler
 101
 102        ldr r11, [r12, #IRQ_MIR_REG_OFFSET]     @ fetch interrupts mask
 103
 104        ldr r13, [r12, #IRQ_ITR_REG_OFFSET]     @ fetch interrupts status
 105        bics r13, r13, r11                      @ clear masked - any left?
 106        beq exit                                @ none - spurious FIQ? exit
 107
 108        ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET] @ get requested interrupt number
 109
 110        mov r8, #2                              @ reset FIQ agreement
 111        str r8, [r12, #IRQ_CONTROL_REG_OFFSET]
 112
 113        cmp r10, #INT_GPIO_BANK1                @ is it GPIO bank interrupt?
 114        beq gpio                                @ yes - process it
 115
 116        mov r8, #1
 117        orr r8, r11, r8, lsl r10                @ mask spurious interrupt
 118        str r8, [r12, #IRQ_MIR_REG_OFFSET]
 119exit:
 120        subs    pc, lr, #4                      @ return from FIQ
 121        @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 122
 123
 124        @@@@@@@@@@@@@@@@@@@@@@@@@@@
 125gpio:   @ GPIO bank interrupt handler
 126        ldr r12, omap1510_gpio_base             @ set base pointer to GPIO bank
 127
 128        ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask
 129restart:
 130        ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS]       @ fetch status bits
 131        bics r13, r13, r11                      @ clear masked - any left?
 132        beq exit                                @ no - spurious interrupt? exit
 133
 134        orr r11, r11, r13                       @ mask all requested interrupts
 135        str r11, [r12, #OMAP1510_GPIO_INT_MASK]
 136
 137        ands r10, r13, #KEYBRD_CLK_MASK         @ extract keyboard status - set?
 138        beq hksw                                @ no - try next source
 139
 140
 141        @@@@@@@@@@@@@@@@@@@@@@
 142        @ Keyboard clock FIQ mode interrupt handler
 143        @ r10 now contains KEYBRD_CLK_MASK, use it
 144        str r10, [r12, #OMAP1510_GPIO_INT_STATUS]       @ ack the interrupt
 145        bic r11, r11, r10                               @ unmask it
 146        str r11, [r12, #OMAP1510_GPIO_INT_MASK]
 147
 148        @ Process keyboard data
 149        ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT]        @ fetch GPIO input
 150
 151        ldr r10, [r9, #BUF_STATE]               @ fetch kbd interface state
 152        cmp r10, #0                             @ are we expecting start bit?
 153        bne data                                @ no - go to data processing
 154
 155        ands r8, r8, #KEYBRD_DATA_MASK          @ check start bit - detected?
 156        beq hksw                                @ no - try next source
 157
 158        @ r8 contains KEYBRD_DATA_MASK, use it
 159        str r8, [r9, #BUF_STATE]                @ enter data processing state
 160        @ r10 already contains 0, reuse it
 161        str r10, [r9, #BUF_KEY]                 @ clear keycode
 162        mov r10, #2                             @ reset input bit mask
 163        str r10, [r9, #BUF_MASK]
 164
 165        @ Mask other GPIO line interrupts till key done
 166        str r11, [r9, #BUF_GPIO_INT_MASK]       @ save mask for later restore
 167        mvn r11, #KEYBRD_CLK_MASK               @ prepare all except kbd mask
 168        str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ store into the mask register
 169
 170        b restart                               @ restart
 171
 172data:   ldr r10, [r9, #BUF_MASK]                @ fetch current input bit mask
 173
 174        @ r8 still contains GPIO input bits
 175        ands r8, r8, #KEYBRD_DATA_MASK          @ is keyboard data line low?
 176        ldreq r8, [r9, #BUF_KEY]                @ yes - fetch collected so far,
 177        orreq r8, r8, r10                       @ set 1 at current mask position
 178        streq r8, [r9, #BUF_KEY]                @ and save back
 179
 180        mov r10, r10, lsl #1                    @ shift mask left
 181        bics r10, r10, #0x800                   @ have we got all the bits?
 182        strne r10, [r9, #BUF_MASK]              @ not yet - store the mask
 183        bne restart                             @ and restart
 184
 185        @ r10 already contains 0, reuse it
 186        str r10, [r9, #BUF_STATE]               @ reset state to start
 187
 188        @ Key done - restore interrupt mask
 189        ldr r10, [r9, #BUF_GPIO_INT_MASK]       @ fetch saved mask
 190        and r11, r11, r10                       @ unmask all saved as unmasked
 191        str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ restore into the mask register
 192
 193        @ Try appending the keycode to the circular buffer
 194        ldr r10, [r9, #BUF_KEYS_CNT]            @ get saved keystrokes count
 195        ldr r8, [r9, #BUF_BUF_LEN]              @ get buffer size
 196        cmp r10, r8                             @ is buffer full?
 197        beq hksw                                @ yes - key lost, next source
 198
 199        add r10, r10, #1                        @ incremet keystrokes counter
 200        str r10, [r9, #BUF_KEYS_CNT]
 201
 202        ldr r10, [r9, #BUF_TAIL_OFFSET]         @ get buffer tail offset
 203        @ r8 already contains buffer size
 204        cmp r10, r8                             @ end of buffer?
 205        moveq r10, #0                           @ yes - rewind to buffer start
 206
 207        ldr r12, [r9, #BUF_BUFFER_START]        @ get buffer start address
 208        add r12, r12, r10, LSL #2               @ calculate buffer tail address
 209        ldr r8, [r9, #BUF_KEY]                  @ get last keycode
 210        str r8, [r12]                           @ append it to the buffer tail
 211
 212        add r10, r10, #1                        @ increment buffer tail offset
 213        str r10, [r9, #BUF_TAIL_OFFSET]
 214
 215        ldr r10, [r9, #BUF_CNT_INT_KEY]         @ increment interrupts counter
 216        add r10, r10, #1
 217        str r10, [r9, #BUF_CNT_INT_KEY]
 218        @@@@@@@@@@@@@@@@@@@@@@@@
 219
 220
 221hksw:   @Is hook switch interrupt requested?
 222        tst r13, #HOOK_SWITCH_MASK              @ is hook switch status bit set?
 223        beq mdm                                 @ no - try next source
 224
 225
 226        @@@@@@@@@@@@@@@@@@@@@@@@
 227        @ Hook switch interrupt FIQ mode simple handler
 228
 229        @ Don't toggle active edge, the switch always bounces
 230
 231        @ Increment hook switch interrupt counter
 232        ldr r10, [r9, #BUF_CNT_INT_HSW]
 233        add r10, r10, #1
 234        str r10, [r9, #BUF_CNT_INT_HSW]
 235        @@@@@@@@@@@@@@@@@@@@@@@@
 236
 237
 238mdm:    @Is it a modem interrupt?
 239        tst r13, #MODEM_IRQ_MASK                @ is modem status bit set?
 240        beq irq                                 @ no - check for next interrupt
 241
 242
 243        @@@@@@@@@@@@@@@@@@@@@@@@
 244        @ Modem FIQ mode interrupt handler stub
 245
 246        @ Increment modem interrupt counter
 247        ldr r10, [r9, #BUF_CNT_INT_MDM]
 248        add r10, r10, #1
 249        str r10, [r9, #BUF_CNT_INT_MDM]
 250        @@@@@@@@@@@@@@@@@@@@@@@@
 251
 252
 253irq:    @ Place deferred_fiq interrupt request
 254        ldr r12, deferred_fiq_ih_base           @ set pointer to IRQ handler
 255        mov r10, #DEFERRED_FIQ_MASK             @ set deferred_fiq bit
 256        str r10, [r12, #IRQ_ISR_REG_OFFSET]     @ place it in the ISR register
 257
 258        ldr r12, omap1510_gpio_base             @ set pointer back to GPIO bank
 259        b restart                               @ check for next GPIO interrupt
 260        @@@@@@@@@@@@@@@@@@@@@@@@@@@
 261
 262
 263/*
 264 * Virtual addresses for IO
 265 */
 266omap_ih1_base:
 267        .word OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
 268deferred_fiq_ih_base:
 269        .word OMAP1_IO_ADDRESS(DEFERRED_FIQ_IH_BASE)
 270omap1510_gpio_base:
 271        .word OMAP1_IO_ADDRESS(OMAP1510_GPIO_BASE)
 272qwerty_fiqin_end:
 273
 274/*
 275 * Check the size of the FIQ,
 276 * it cannot go beyond 0xffff0200, and is copied to 0xffff001c
 277 */
 278.if (qwerty_fiqin_end - qwerty_fiqin_start) > (0x200 - 0x1c)
 279        .err
 280.endif
 281