LXR linux/arch/arm/mach-socfpga/socfpga.c

   1/*
   2 *  Copyright (C) 2012-2015 Altera Corporation
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License as published by
   6 * the Free Software Foundation; either version 2 of the License, or
   7 * (at your option) any later version.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 *
  14 * You should have received a copy of the GNU General Public License
  15 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17#include <linux/irqchip.h>
  18#include <linux/of_address.h>
  19#include <linux/of_irq.h>
  20#include <linux/of_platform.h>
  21#include <linux/reboot.h>
  22
  23#include <asm/hardware/cache-l2x0.h>
  24#include <asm/mach/arch.h>
  25#include <asm/mach/map.h>
  26#include <asm/cacheflush.h>
  27
  28#include "core.h"
  29
  30void __iomem *sys_manager_base_addr;
  31void __iomem *rst_manager_base_addr;
  32void __iomem *sdr_ctl_base_addr;
  33unsigned long socfpga_cpu1start_addr;
  34
  35void __init socfpga_sysmgr_init(void)
  36{
  37        struct device_node *np;
  38
  39        np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
  40
  41        if (of_property_read_u32(np, "cpu1-start-addr",
  42                        (u32 *) &socfpga_cpu1start_addr))
  43                pr_err("SMP: Need cpu1-start-addr in device tree.\n");
  44
  45        /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
  46        smp_wmb();
  47        sync_cache_w(&socfpga_cpu1start_addr);
  48
  49        sys_manager_base_addr = of_iomap(np, 0);
  50
  51        np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
  52        rst_manager_base_addr = of_iomap(np, 0);
  53
  54        np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
  55        sdr_ctl_base_addr = of_iomap(np, 0);
  56}
  57
  58static void __init socfpga_init_irq(void)
  59{
  60        irqchip_init();
  61        socfpga_sysmgr_init();
  62}
  63
  64static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
  65{
  66        u32 temp;
  67
  68        temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
  69
  70        if (mode == REBOOT_HARD)
  71                temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
  72        else
  73                temp |= RSTMGR_CTRL_SWWARMRSTREQ;
  74        writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
  75}
  76
  77static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
  78{
  79        u32 temp;
  80
  81        temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
  82
  83        if (mode == REBOOT_HARD)
  84                temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
  85        else
  86                temp |= RSTMGR_CTRL_SWWARMRSTREQ;
  87        writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
  88}
  89
  90static const char *altera_dt_match[] = {
  91        "altr,socfpga",
  92        NULL
  93};
  94
  95DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
  96        .l2c_aux_val    = 0,
  97        .l2c_aux_mask   = ~0,
  98        .init_irq       = socfpga_init_irq,
  99        .restart        = socfpga_cyclone5_restart,
 100        .dt_compat      = altera_dt_match,
 101MACHINE_END
 102
 103static const char *altera_a10_dt_match[] = {
 104        "altr,socfpga-arria10",
 105        NULL
 106};
 107
 108DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
 109        .l2c_aux_val    = 0,
 110        .l2c_aux_mask   = ~0,
 111        .init_irq       = socfpga_init_irq,
 112        .restart        = socfpga_arria10_restart,
 113        .dt_compat      = altera_a10_dt_match,
 114MACHINE_END
 115