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10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/mman.h>
15#include <linux/nodemask.h>
16#include <linux/memblock.h>
17#include <linux/fs.h>
18#include <linux/vmalloc.h>
19#include <linux/sizes.h>
20
21#include <asm/cp15.h>
22#include <asm/cputype.h>
23#include <asm/sections.h>
24#include <asm/cachetype.h>
25#include <asm/fixmap.h>
26#include <asm/sections.h>
27#include <asm/setup.h>
28#include <asm/smp_plat.h>
29#include <asm/tlb.h>
30#include <asm/highmem.h>
31#include <asm/system_info.h>
32#include <asm/traps.h>
33#include <asm/procinfo.h>
34#include <asm/memory.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/pci.h>
39#include <asm/fixmap.h>
40
41#include "mm.h"
42#include "tcm.h"
43
44
45
46
47
48struct page *empty_zero_page;
49EXPORT_SYMBOL(empty_zero_page);
50
51
52
53
54pmd_t *top_pmd;
55
56pmdval_t user_pmd_table = _PAGE_USER_TABLE;
57
58#define CPOLICY_UNCACHED 0
59#define CPOLICY_BUFFERED 1
60#define CPOLICY_WRITETHROUGH 2
61#define CPOLICY_WRITEBACK 3
62#define CPOLICY_WRITEALLOC 4
63
64static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
65static unsigned int ecc_mask __initdata = 0;
66pgprot_t pgprot_user;
67pgprot_t pgprot_kernel;
68pgprot_t pgprot_hyp_device;
69pgprot_t pgprot_s2;
70pgprot_t pgprot_s2_device;
71
72EXPORT_SYMBOL(pgprot_user);
73EXPORT_SYMBOL(pgprot_kernel);
74
75struct cachepolicy {
76 const char policy[16];
77 unsigned int cr_mask;
78 pmdval_t pmd;
79 pteval_t pte;
80 pteval_t pte_s2;
81};
82
83#ifdef CONFIG_ARM_LPAE
84#define s2_policy(policy) policy
85#else
86#define s2_policy(policy) 0
87#endif
88
89static struct cachepolicy cache_policies[] __initdata = {
90 {
91 .policy = "uncached",
92 .cr_mask = CR_W|CR_C,
93 .pmd = PMD_SECT_UNCACHED,
94 .pte = L_PTE_MT_UNCACHED,
95 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
96 }, {
97 .policy = "buffered",
98 .cr_mask = CR_C,
99 .pmd = PMD_SECT_BUFFERED,
100 .pte = L_PTE_MT_BUFFERABLE,
101 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
102 }, {
103 .policy = "writethrough",
104 .cr_mask = 0,
105 .pmd = PMD_SECT_WT,
106 .pte = L_PTE_MT_WRITETHROUGH,
107 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
108 }, {
109 .policy = "writeback",
110 .cr_mask = 0,
111 .pmd = PMD_SECT_WB,
112 .pte = L_PTE_MT_WRITEBACK,
113 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
114 }, {
115 .policy = "writealloc",
116 .cr_mask = 0,
117 .pmd = PMD_SECT_WBWA,
118 .pte = L_PTE_MT_WRITEALLOC,
119 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
120 }
121};
122
123#ifdef CONFIG_CPU_CP15
124static unsigned long initial_pmd_value __initdata = 0;
125
126
127
128
129
130
131
132
133void __init init_default_cache_policy(unsigned long pmd)
134{
135 int i;
136
137 initial_pmd_value = pmd;
138
139 pmd &= PMD_SECT_TEX(1) | PMD_SECT_BUFFERABLE | PMD_SECT_CACHEABLE;
140
141 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
142 if (cache_policies[i].pmd == pmd) {
143 cachepolicy = i;
144 break;
145 }
146
147 if (i == ARRAY_SIZE(cache_policies))
148 pr_err("ERROR: could not find cache policy\n");
149}
150
151
152
153
154
155
156static int __init early_cachepolicy(char *p)
157{
158 int i, selected = -1;
159
160 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
161 int len = strlen(cache_policies[i].policy);
162
163 if (memcmp(p, cache_policies[i].policy, len) == 0) {
164 selected = i;
165 break;
166 }
167 }
168
169 if (selected == -1)
170 pr_err("ERROR: unknown or unsupported cache policy\n");
171
172
173
174
175
176
177
178
179 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
180 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
181 cache_policies[cachepolicy].policy);
182 return 0;
183 }
184
185 if (selected != cachepolicy) {
186 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
187 cachepolicy = selected;
188 flush_cache_all();
189 set_cr(cr);
190 }
191 return 0;
192}
193early_param("cachepolicy", early_cachepolicy);
194
195static int __init early_nocache(char *__unused)
196{
197 char *p = "buffered";
198 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
199 early_cachepolicy(p);
200 return 0;
201}
202early_param("nocache", early_nocache);
203
204static int __init early_nowrite(char *__unused)
205{
206 char *p = "uncached";
207 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
208 early_cachepolicy(p);
209 return 0;
210}
211early_param("nowb", early_nowrite);
212
213#ifndef CONFIG_ARM_LPAE
214static int __init early_ecc(char *p)
215{
216 if (memcmp(p, "on", 2) == 0)
217 ecc_mask = PMD_PROTECTION;
218 else if (memcmp(p, "off", 3) == 0)
219 ecc_mask = 0;
220 return 0;
221}
222early_param("ecc", early_ecc);
223#endif
224
225#else
226
227static int __init early_cachepolicy(char *p)
228{
229 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
230}
231early_param("cachepolicy", early_cachepolicy);
232
233static int __init noalign_setup(char *__unused)
234{
235 pr_warn("noalign kernel parameter not supported without cp15\n");
236}
237__setup("noalign", noalign_setup);
238
239#endif
240
241#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
242#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
243#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
244
245static struct mem_type mem_types[] = {
246 [MT_DEVICE] = {
247 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
248 L_PTE_SHARED,
249 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
250 s2_policy(L_PTE_S2_MT_DEV_SHARED) |
251 L_PTE_SHARED,
252 .prot_l1 = PMD_TYPE_TABLE,
253 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
254 .domain = DOMAIN_IO,
255 },
256 [MT_DEVICE_NONSHARED] = {
257 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
258 .prot_l1 = PMD_TYPE_TABLE,
259 .prot_sect = PROT_SECT_DEVICE,
260 .domain = DOMAIN_IO,
261 },
262 [MT_DEVICE_CACHED] = {
263 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
264 .prot_l1 = PMD_TYPE_TABLE,
265 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
266 .domain = DOMAIN_IO,
267 },
268 [MT_DEVICE_WC] = {
269 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
270 .prot_l1 = PMD_TYPE_TABLE,
271 .prot_sect = PROT_SECT_DEVICE,
272 .domain = DOMAIN_IO,
273 },
274 [MT_UNCACHED] = {
275 .prot_pte = PROT_PTE_DEVICE,
276 .prot_l1 = PMD_TYPE_TABLE,
277 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
278 .domain = DOMAIN_IO,
279 },
280 [MT_CACHECLEAN] = {
281 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
282 .domain = DOMAIN_KERNEL,
283 },
284#ifndef CONFIG_ARM_LPAE
285 [MT_MINICLEAN] = {
286 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
287 .domain = DOMAIN_KERNEL,
288 },
289#endif
290 [MT_LOW_VECTORS] = {
291 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
292 L_PTE_RDONLY,
293 .prot_l1 = PMD_TYPE_TABLE,
294 .domain = DOMAIN_VECTORS,
295 },
296 [MT_HIGH_VECTORS] = {
297 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
298 L_PTE_USER | L_PTE_RDONLY,
299 .prot_l1 = PMD_TYPE_TABLE,
300 .domain = DOMAIN_VECTORS,
301 },
302 [MT_MEMORY_RWX] = {
303 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
304 .prot_l1 = PMD_TYPE_TABLE,
305 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
306 .domain = DOMAIN_KERNEL,
307 },
308 [MT_MEMORY_RW] = {
309 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
310 L_PTE_XN,
311 .prot_l1 = PMD_TYPE_TABLE,
312 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
313 .domain = DOMAIN_KERNEL,
314 },
315 [MT_ROM] = {
316 .prot_sect = PMD_TYPE_SECT,
317 .domain = DOMAIN_KERNEL,
318 },
319 [MT_MEMORY_RWX_NONCACHED] = {
320 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
321 L_PTE_MT_BUFFERABLE,
322 .prot_l1 = PMD_TYPE_TABLE,
323 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
324 .domain = DOMAIN_KERNEL,
325 },
326 [MT_MEMORY_RW_DTCM] = {
327 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
328 L_PTE_XN,
329 .prot_l1 = PMD_TYPE_TABLE,
330 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
331 .domain = DOMAIN_KERNEL,
332 },
333 [MT_MEMORY_RWX_ITCM] = {
334 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
335 .prot_l1 = PMD_TYPE_TABLE,
336 .domain = DOMAIN_KERNEL,
337 },
338 [MT_MEMORY_RW_SO] = {
339 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
340 L_PTE_MT_UNCACHED | L_PTE_XN,
341 .prot_l1 = PMD_TYPE_TABLE,
342 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
343 PMD_SECT_UNCACHED | PMD_SECT_XN,
344 .domain = DOMAIN_KERNEL,
345 },
346 [MT_MEMORY_DMA_READY] = {
347 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
348 L_PTE_XN,
349 .prot_l1 = PMD_TYPE_TABLE,
350 .domain = DOMAIN_KERNEL,
351 },
352};
353
354const struct mem_type *get_mem_type(unsigned int type)
355{
356 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
357}
358EXPORT_SYMBOL(get_mem_type);
359
360static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
361
362static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
363 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
364
365static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
366{
367 return &bm_pte[pte_index(addr)];
368}
369
370static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
371{
372 return pte_offset_kernel(dir, addr);
373}
374
375static inline pmd_t * __init fixmap_pmd(unsigned long addr)
376{
377 pgd_t *pgd = pgd_offset_k(addr);
378 pud_t *pud = pud_offset(pgd, addr);
379 pmd_t *pmd = pmd_offset(pud, addr);
380
381 return pmd;
382}
383
384void __init early_fixmap_init(void)
385{
386 pmd_t *pmd;
387
388
389
390
391
392 BUILD_BUG_ON((__fix_to_virt(__end_of_permanent_fixed_addresses) >> PMD_SHIFT)
393 != FIXADDR_TOP >> PMD_SHIFT);
394
395 pmd = fixmap_pmd(FIXADDR_TOP);
396 pmd_populate_kernel(&init_mm, pmd, bm_pte);
397
398 pte_offset_fixmap = pte_offset_early_fixmap;
399}
400
401
402
403
404
405
406void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
407{
408 unsigned long vaddr = __fix_to_virt(idx);
409 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
410
411
412 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
413 FIXADDR_END);
414 BUG_ON(idx >= __end_of_fixed_addresses);
415
416 if (pgprot_val(prot))
417 set_pte_at(NULL, vaddr, pte,
418 pfn_pte(phys >> PAGE_SHIFT, prot));
419 else
420 pte_clear(NULL, vaddr, pte);
421 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
422}
423
424
425
426
427static void __init build_mem_type_table(void)
428{
429 struct cachepolicy *cp;
430 unsigned int cr = get_cr();
431 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
432 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
433 int cpu_arch = cpu_architecture();
434 int i;
435
436 if (cpu_arch < CPU_ARCH_ARMv6) {
437#if defined(CONFIG_CPU_DCACHE_DISABLE)
438 if (cachepolicy > CPOLICY_BUFFERED)
439 cachepolicy = CPOLICY_BUFFERED;
440#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
441 if (cachepolicy > CPOLICY_WRITETHROUGH)
442 cachepolicy = CPOLICY_WRITETHROUGH;
443#endif
444 }
445 if (cpu_arch < CPU_ARCH_ARMv5) {
446 if (cachepolicy >= CPOLICY_WRITEALLOC)
447 cachepolicy = CPOLICY_WRITEBACK;
448 ecc_mask = 0;
449 }
450
451 if (is_smp()) {
452 if (cachepolicy != CPOLICY_WRITEALLOC) {
453 pr_warn("Forcing write-allocate cache policy for SMP\n");
454 cachepolicy = CPOLICY_WRITEALLOC;
455 }
456 if (!(initial_pmd_value & PMD_SECT_S)) {
457 pr_warn("Forcing shared mappings for SMP\n");
458 initial_pmd_value |= PMD_SECT_S;
459 }
460 }
461
462
463
464
465
466
467 if (cpu_arch < CPU_ARCH_ARMv5)
468 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
469 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
470 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
471 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
472 mem_types[i].prot_sect &= ~PMD_SECT_S;
473
474
475
476
477
478
479 if (cpu_is_xscale() || cpu_is_xsc3()) {
480 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
481 mem_types[i].prot_sect &= ~PMD_BIT4;
482 mem_types[i].prot_l1 &= ~PMD_BIT4;
483 }
484 } else if (cpu_arch < CPU_ARCH_ARMv6) {
485 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
486 if (mem_types[i].prot_l1)
487 mem_types[i].prot_l1 |= PMD_BIT4;
488 if (mem_types[i].prot_sect)
489 mem_types[i].prot_sect |= PMD_BIT4;
490 }
491 }
492
493
494
495
496 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
497 if (!cpu_is_xsc3()) {
498
499
500
501
502 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
503 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
504 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
505 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
506
507
508 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
509 }
510 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
511
512
513
514
515
516
517
518 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
519 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
520 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
521 } else if (cpu_is_xsc3()) {
522
523
524
525
526
527
528
529 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
530 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
531 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
532 } else {
533
534
535
536
537
538
539
540 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
541 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
542 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
543 }
544 } else {
545
546
547
548 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
549 }
550
551
552
553
554 cp = &cache_policies[cachepolicy];
555 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
556 s2_pgprot = cp->pte_s2;
557 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
558 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
559
560#ifndef CONFIG_ARM_LPAE
561
562
563
564
565
566 if (cpu_arch == CPU_ARCH_ARMv6)
567 vecs_pgprot |= L_PTE_MT_VECTORS;
568
569
570
571
572
573 if (cpu_arch == CPU_ARCH_ARMv7 &&
574 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) == 4) {
575 user_pmd_table |= PMD_PXNTABLE;
576 }
577#endif
578
579
580
581
582 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
583#ifndef CONFIG_ARM_LPAE
584
585
586
587
588 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
589 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
590 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
591#endif
592
593
594
595
596
597
598 if (initial_pmd_value & PMD_SECT_S) {
599 user_pgprot |= L_PTE_SHARED;
600 kern_pgprot |= L_PTE_SHARED;
601 vecs_pgprot |= L_PTE_SHARED;
602 s2_pgprot |= L_PTE_SHARED;
603 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
604 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
605 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
606 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
607 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
608 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
609 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
610 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
611 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
612 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
613 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
614 }
615 }
616
617
618
619
620
621 if (cpu_arch >= CPU_ARCH_ARMv6) {
622 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
623
624 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
625 PMD_SECT_BUFFERED;
626 } else {
627
628 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
629 PMD_SECT_TEX(1);
630 }
631 } else {
632 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
633 }
634
635#ifdef CONFIG_ARM_LPAE
636
637
638
639 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
640 mem_types[i].prot_pte |= PTE_EXT_AF;
641 if (mem_types[i].prot_sect)
642 mem_types[i].prot_sect |= PMD_SECT_AF;
643 }
644 kern_pgprot |= PTE_EXT_AF;
645 vecs_pgprot |= PTE_EXT_AF;
646
647
648
649
650 user_pgprot |= PTE_EXT_PXN;
651#endif
652
653 for (i = 0; i < 16; i++) {
654 pteval_t v = pgprot_val(protection_map[i]);
655 protection_map[i] = __pgprot(v | user_pgprot);
656 }
657
658 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
659 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
660
661 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
662 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
663 L_PTE_DIRTY | kern_pgprot);
664 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
665 pgprot_s2_device = __pgprot(s2_device_pgprot);
666 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
667
668 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
669 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
670 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
671 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
672 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
673 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
674 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
675 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
676 mem_types[MT_ROM].prot_sect |= cp->pmd;
677
678 switch (cp->pmd) {
679 case PMD_SECT_WT:
680 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
681 break;
682 case PMD_SECT_WB:
683 case PMD_SECT_WBWA:
684 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
685 break;
686 }
687 pr_info("Memory policy: %sData cache %s\n",
688 ecc_mask ? "ECC enabled, " : "", cp->policy);
689
690 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
691 struct mem_type *t = &mem_types[i];
692 if (t->prot_l1)
693 t->prot_l1 |= PMD_DOMAIN(t->domain);
694 if (t->prot_sect)
695 t->prot_sect |= PMD_DOMAIN(t->domain);
696 }
697}
698
699#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
700pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
701 unsigned long size, pgprot_t vma_prot)
702{
703 if (!pfn_valid(pfn))
704 return pgprot_noncached(vma_prot);
705 else if (file->f_flags & O_SYNC)
706 return pgprot_writecombine(vma_prot);
707 return vma_prot;
708}
709EXPORT_SYMBOL(phys_mem_access_prot);
710#endif
711
712#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
713
714static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
715{
716 void *ptr = __va(memblock_alloc(sz, align));
717 memset(ptr, 0, sz);
718 return ptr;
719}
720
721static void __init *early_alloc(unsigned long sz)
722{
723 return early_alloc_aligned(sz, sz);
724}
725
726static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
727{
728 if (pmd_none(*pmd)) {
729 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
730 __pmd_populate(pmd, __pa(pte), prot);
731 }
732 BUG_ON(pmd_bad(*pmd));
733 return pte_offset_kernel(pmd, addr);
734}
735
736static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
737 unsigned long end, unsigned long pfn,
738 const struct mem_type *type)
739{
740 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
741 do {
742 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
743 pfn++;
744 } while (pte++, addr += PAGE_SIZE, addr != end);
745}
746
747static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
748 unsigned long end, phys_addr_t phys,
749 const struct mem_type *type)
750{
751 pmd_t *p = pmd;
752
753#ifndef CONFIG_ARM_LPAE
754
755
756
757
758
759
760
761
762
763 if (addr & SECTION_SIZE)
764 pmd++;
765#endif
766 do {
767 *pmd = __pmd(phys | type->prot_sect);
768 phys += SECTION_SIZE;
769 } while (pmd++, addr += SECTION_SIZE, addr != end);
770
771 flush_pmd_entry(p);
772}
773
774static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
775 unsigned long end, phys_addr_t phys,
776 const struct mem_type *type)
777{
778 pmd_t *pmd = pmd_offset(pud, addr);
779 unsigned long next;
780
781 do {
782
783
784
785
786 next = pmd_addr_end(addr, end);
787
788
789
790
791
792 if (type->prot_sect &&
793 ((addr | next | phys) & ~SECTION_MASK) == 0) {
794 __map_init_section(pmd, addr, next, phys, type);
795 } else {
796 alloc_init_pte(pmd, addr, next,
797 __phys_to_pfn(phys), type);
798 }
799
800 phys += next - addr;
801
802 } while (pmd++, addr = next, addr != end);
803}
804
805static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
806 unsigned long end, phys_addr_t phys,
807 const struct mem_type *type)
808{
809 pud_t *pud = pud_offset(pgd, addr);
810 unsigned long next;
811
812 do {
813 next = pud_addr_end(addr, end);
814 alloc_init_pmd(pud, addr, next, phys, type);
815 phys += next - addr;
816 } while (pud++, addr = next, addr != end);
817}
818
819#ifndef CONFIG_ARM_LPAE
820static void __init create_36bit_mapping(struct map_desc *md,
821 const struct mem_type *type)
822{
823 unsigned long addr, length, end;
824 phys_addr_t phys;
825 pgd_t *pgd;
826
827 addr = md->virtual;
828 phys = __pfn_to_phys(md->pfn);
829 length = PAGE_ALIGN(md->length);
830
831 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
832 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
833 (long long)__pfn_to_phys((u64)md->pfn), addr);
834 return;
835 }
836
837
838
839
840
841
842
843 if (type->domain) {
844 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
845 (long long)__pfn_to_phys((u64)md->pfn), addr);
846 return;
847 }
848
849 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
850 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
851 (long long)__pfn_to_phys((u64)md->pfn), addr);
852 return;
853 }
854
855
856
857
858
859 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
860
861 pgd = pgd_offset_k(addr);
862 end = addr + length;
863 do {
864 pud_t *pud = pud_offset(pgd, addr);
865 pmd_t *pmd = pmd_offset(pud, addr);
866 int i;
867
868 for (i = 0; i < 16; i++)
869 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
870
871 addr += SUPERSECTION_SIZE;
872 phys += SUPERSECTION_SIZE;
873 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
874 } while (addr != end);
875}
876#endif
877
878
879
880
881
882
883
884
885static void __init create_mapping(struct map_desc *md)
886{
887 unsigned long addr, length, end;
888 phys_addr_t phys;
889 const struct mem_type *type;
890 pgd_t *pgd;
891
892 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
893 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
894 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
895 return;
896 }
897
898 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
899 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
900 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
901 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
902 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
903 }
904
905 type = &mem_types[md->type];
906
907#ifndef CONFIG_ARM_LPAE
908
909
910
911 if (md->pfn >= 0x100000) {
912 create_36bit_mapping(md, type);
913 return;
914 }
915#endif
916
917 addr = md->virtual & PAGE_MASK;
918 phys = __pfn_to_phys(md->pfn);
919 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
920
921 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
922 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
923 (long long)__pfn_to_phys(md->pfn), addr);
924 return;
925 }
926
927 pgd = pgd_offset_k(addr);
928 end = addr + length;
929 do {
930 unsigned long next = pgd_addr_end(addr, end);
931
932 alloc_init_pud(pgd, addr, next, phys, type);
933
934 phys += next - addr;
935 addr = next;
936 } while (pgd++, addr != end);
937}
938
939
940
941
942void __init iotable_init(struct map_desc *io_desc, int nr)
943{
944 struct map_desc *md;
945 struct vm_struct *vm;
946 struct static_vm *svm;
947
948 if (!nr)
949 return;
950
951 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
952
953 for (md = io_desc; nr; md++, nr--) {
954 create_mapping(md);
955
956 vm = &svm->vm;
957 vm->addr = (void *)(md->virtual & PAGE_MASK);
958 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
959 vm->phys_addr = __pfn_to_phys(md->pfn);
960 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
961 vm->flags |= VM_ARM_MTYPE(md->type);
962 vm->caller = iotable_init;
963 add_static_vm_early(svm++);
964 }
965}
966
967void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
968 void *caller)
969{
970 struct vm_struct *vm;
971 struct static_vm *svm;
972
973 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
974
975 vm = &svm->vm;
976 vm->addr = (void *)addr;
977 vm->size = size;
978 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
979 vm->caller = caller;
980 add_static_vm_early(svm);
981}
982
983#ifndef CONFIG_ARM_LPAE
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998static void __init pmd_empty_section_gap(unsigned long addr)
999{
1000 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1001}
1002
1003static void __init fill_pmd_gaps(void)
1004{
1005 struct static_vm *svm;
1006 struct vm_struct *vm;
1007 unsigned long addr, next = 0;
1008 pmd_t *pmd;
1009
1010 list_for_each_entry(svm, &static_vmlist, list) {
1011 vm = &svm->vm;
1012 addr = (unsigned long)vm->addr;
1013 if (addr < next)
1014 continue;
1015
1016
1017
1018
1019
1020
1021 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1022 pmd = pmd_off_k(addr);
1023 if (pmd_none(*pmd))
1024 pmd_empty_section_gap(addr & PMD_MASK);
1025 }
1026
1027
1028
1029
1030
1031
1032 addr += vm->size;
1033 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1034 pmd = pmd_off_k(addr) + 1;
1035 if (pmd_none(*pmd))
1036 pmd_empty_section_gap(addr);
1037 }
1038
1039
1040 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1041 }
1042}
1043
1044#else
1045#define fill_pmd_gaps() do { } while (0)
1046#endif
1047
1048#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1049static void __init pci_reserve_io(void)
1050{
1051 struct static_vm *svm;
1052
1053 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1054 if (svm)
1055 return;
1056
1057 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1058}
1059#else
1060#define pci_reserve_io() do { } while (0)
1061#endif
1062
1063#ifdef CONFIG_DEBUG_LL
1064void __init debug_ll_io_init(void)
1065{
1066 struct map_desc map;
1067
1068 debug_ll_addr(&map.pfn, &map.virtual);
1069 if (!map.pfn || !map.virtual)
1070 return;
1071 map.pfn = __phys_to_pfn(map.pfn);
1072 map.virtual &= PAGE_MASK;
1073 map.length = PAGE_SIZE;
1074 map.type = MT_DEVICE;
1075 iotable_init(&map, 1);
1076}
1077#endif
1078
1079static void * __initdata vmalloc_min =
1080 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1081
1082
1083
1084
1085
1086
1087static int __init early_vmalloc(char *arg)
1088{
1089 unsigned long vmalloc_reserve = memparse(arg, NULL);
1090
1091 if (vmalloc_reserve < SZ_16M) {
1092 vmalloc_reserve = SZ_16M;
1093 pr_warn("vmalloc area too small, limiting to %luMB\n",
1094 vmalloc_reserve >> 20);
1095 }
1096
1097 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1098 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1099 pr_warn("vmalloc area is too big, limiting to %luMB\n",
1100 vmalloc_reserve >> 20);
1101 }
1102
1103 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1104 return 0;
1105}
1106early_param("vmalloc", early_vmalloc);
1107
1108phys_addr_t arm_lowmem_limit __initdata = 0;
1109
1110void __init sanity_check_meminfo(void)
1111{
1112 phys_addr_t memblock_limit = 0;
1113 int highmem = 0;
1114 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
1115 struct memblock_region *reg;
1116 bool should_use_highmem = false;
1117
1118 for_each_memblock(memory, reg) {
1119 phys_addr_t block_start = reg->base;
1120 phys_addr_t block_end = reg->base + reg->size;
1121 phys_addr_t size_limit = reg->size;
1122
1123 if (reg->base >= vmalloc_limit)
1124 highmem = 1;
1125 else
1126 size_limit = vmalloc_limit - reg->base;
1127
1128
1129 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1130
1131 if (highmem) {
1132 pr_notice("Ignoring RAM at %pa-%pa (!CONFIG_HIGHMEM)\n",
1133 &block_start, &block_end);
1134 memblock_remove(reg->base, reg->size);
1135 should_use_highmem = true;
1136 continue;
1137 }
1138
1139 if (reg->size > size_limit) {
1140 phys_addr_t overlap_size = reg->size - size_limit;
1141
1142 pr_notice("Truncating RAM at %pa-%pa to -%pa",
1143 &block_start, &block_end, &vmalloc_limit);
1144 memblock_remove(vmalloc_limit, overlap_size);
1145 block_end = vmalloc_limit;
1146 should_use_highmem = true;
1147 }
1148 }
1149
1150 if (!highmem) {
1151 if (block_end > arm_lowmem_limit) {
1152 if (reg->size > size_limit)
1153 arm_lowmem_limit = vmalloc_limit;
1154 else
1155 arm_lowmem_limit = block_end;
1156 }
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171 if (!memblock_limit) {
1172 if (!IS_ALIGNED(block_start, PMD_SIZE))
1173 memblock_limit = block_start;
1174 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1175 memblock_limit = arm_lowmem_limit;
1176 }
1177
1178 }
1179 }
1180
1181 if (should_use_highmem)
1182 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1183
1184 high_memory = __va(arm_lowmem_limit - 1) + 1;
1185
1186
1187
1188
1189
1190
1191 if (memblock_limit)
1192 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1193 if (!memblock_limit)
1194 memblock_limit = arm_lowmem_limit;
1195
1196 memblock_set_current_limit(memblock_limit);
1197}
1198
1199static inline void prepare_page_table(void)
1200{
1201 unsigned long addr;
1202 phys_addr_t end;
1203
1204
1205
1206
1207 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1208 pmd_clear(pmd_off_k(addr));
1209
1210#ifdef CONFIG_XIP_KERNEL
1211
1212 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1213#endif
1214 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1215 pmd_clear(pmd_off_k(addr));
1216
1217
1218
1219
1220 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1221 if (end >= arm_lowmem_limit)
1222 end = arm_lowmem_limit;
1223
1224
1225
1226
1227
1228 for (addr = __phys_to_virt(end);
1229 addr < VMALLOC_START; addr += PMD_SIZE)
1230 pmd_clear(pmd_off_k(addr));
1231}
1232
1233#ifdef CONFIG_ARM_LPAE
1234
1235#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1236 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1237#else
1238#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1239#endif
1240
1241
1242
1243
1244void __init arm_mm_memblock_reserve(void)
1245{
1246
1247
1248
1249
1250 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1251
1252#ifdef CONFIG_SA1111
1253
1254
1255
1256
1257 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1258#endif
1259}
1260
1261
1262
1263
1264
1265
1266
1267
1268static void __init devicemaps_init(const struct machine_desc *mdesc)
1269{
1270 struct map_desc map;
1271 unsigned long addr;
1272 void *vectors;
1273
1274
1275
1276
1277 vectors = early_alloc(PAGE_SIZE * 2);
1278
1279 early_trap_init(vectors);
1280
1281
1282
1283
1284 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1285 pmd_clear(pmd_off_k(addr));
1286
1287
1288
1289
1290
1291#ifdef CONFIG_XIP_KERNEL
1292 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1293 map.virtual = MODULES_VADDR;
1294 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1295 map.type = MT_ROM;
1296 create_mapping(&map);
1297#endif
1298
1299
1300
1301
1302#ifdef FLUSH_BASE
1303 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1304 map.virtual = FLUSH_BASE;
1305 map.length = SZ_1M;
1306 map.type = MT_CACHECLEAN;
1307 create_mapping(&map);
1308#endif
1309#ifdef FLUSH_BASE_MINICACHE
1310 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1311 map.virtual = FLUSH_BASE_MINICACHE;
1312 map.length = SZ_1M;
1313 map.type = MT_MINICLEAN;
1314 create_mapping(&map);
1315#endif
1316
1317
1318
1319
1320
1321
1322 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1323 map.virtual = 0xffff0000;
1324 map.length = PAGE_SIZE;
1325#ifdef CONFIG_KUSER_HELPERS
1326 map.type = MT_HIGH_VECTORS;
1327#else
1328 map.type = MT_LOW_VECTORS;
1329#endif
1330 create_mapping(&map);
1331
1332 if (!vectors_high()) {
1333 map.virtual = 0;
1334 map.length = PAGE_SIZE * 2;
1335 map.type = MT_LOW_VECTORS;
1336 create_mapping(&map);
1337 }
1338
1339
1340 map.pfn += 1;
1341 map.virtual = 0xffff0000 + PAGE_SIZE;
1342 map.length = PAGE_SIZE;
1343 map.type = MT_LOW_VECTORS;
1344 create_mapping(&map);
1345
1346
1347
1348
1349 if (mdesc->map_io)
1350 mdesc->map_io();
1351 else
1352 debug_ll_io_init();
1353 fill_pmd_gaps();
1354
1355
1356 pci_reserve_io();
1357
1358
1359
1360
1361
1362
1363
1364 local_flush_tlb_all();
1365 flush_cache_all();
1366}
1367
1368static void __init kmap_init(void)
1369{
1370#ifdef CONFIG_HIGHMEM
1371 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1372 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1373#endif
1374
1375 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1376 _PAGE_KERNEL_TABLE);
1377}
1378
1379static void __init map_lowmem(void)
1380{
1381 struct memblock_region *reg;
1382 phys_addr_t kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
1383 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1384
1385
1386 for_each_memblock(memory, reg) {
1387 phys_addr_t start = reg->base;
1388 phys_addr_t end = start + reg->size;
1389 struct map_desc map;
1390
1391 if (end > arm_lowmem_limit)
1392 end = arm_lowmem_limit;
1393 if (start >= end)
1394 break;
1395
1396 if (end < kernel_x_start) {
1397 map.pfn = __phys_to_pfn(start);
1398 map.virtual = __phys_to_virt(start);
1399 map.length = end - start;
1400 map.type = MT_MEMORY_RWX;
1401
1402 create_mapping(&map);
1403 } else if (start >= kernel_x_end) {
1404 map.pfn = __phys_to_pfn(start);
1405 map.virtual = __phys_to_virt(start);
1406 map.length = end - start;
1407 map.type = MT_MEMORY_RW;
1408
1409 create_mapping(&map);
1410 } else {
1411
1412 if (start < kernel_x_start) {
1413 map.pfn = __phys_to_pfn(start);
1414 map.virtual = __phys_to_virt(start);
1415 map.length = kernel_x_start - start;
1416 map.type = MT_MEMORY_RW;
1417
1418 create_mapping(&map);
1419 }
1420
1421 map.pfn = __phys_to_pfn(kernel_x_start);
1422 map.virtual = __phys_to_virt(kernel_x_start);
1423 map.length = kernel_x_end - kernel_x_start;
1424 map.type = MT_MEMORY_RWX;
1425
1426 create_mapping(&map);
1427
1428 if (kernel_x_end < end) {
1429 map.pfn = __phys_to_pfn(kernel_x_end);
1430 map.virtual = __phys_to_virt(kernel_x_end);
1431 map.length = end - kernel_x_end;
1432 map.type = MT_MEMORY_RW;
1433
1434 create_mapping(&map);
1435 }
1436 }
1437 }
1438}
1439
1440#ifdef CONFIG_ARM_PV_FIXUP
1441extern unsigned long __atags_pointer;
1442typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata);
1443pgtables_remap lpae_pgtables_remap_asm;
1444
1445
1446
1447
1448
1449void __init early_paging_init(const struct machine_desc *mdesc)
1450{
1451 pgtables_remap *lpae_pgtables_remap;
1452 unsigned long pa_pgd;
1453 unsigned int cr, ttbcr;
1454 long long offset;
1455 void *boot_data;
1456
1457 if (!mdesc->pv_fixup)
1458 return;
1459
1460 offset = mdesc->pv_fixup();
1461 if (offset == 0)
1462 return;
1463
1464
1465
1466
1467
1468
1469
1470 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1471 pa_pgd = __pa(swapper_pg_dir);
1472 boot_data = __va(__atags_pointer);
1473 barrier();
1474
1475 pr_info("Switching physical address space to 0x%08llx\n",
1476 (u64)PHYS_OFFSET + offset);
1477
1478
1479 __pv_offset += offset;
1480 __pv_phys_pfn_offset += PFN_DOWN(offset);
1481
1482
1483 fixup_pv_table(&__pv_table_begin,
1484 (&__pv_table_end - &__pv_table_begin) << 2);
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495 cr = get_cr();
1496 set_cr(cr & ~(CR_I | CR_C));
1497 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1498 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1499 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1500 flush_cache_all();
1501
1502
1503
1504
1505
1506
1507
1508 lpae_pgtables_remap(offset, pa_pgd, boot_data);
1509
1510
1511 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1512 set_cr(cr);
1513}
1514
1515#else
1516
1517void __init early_paging_init(const struct machine_desc *mdesc)
1518{
1519 long long offset;
1520
1521 if (!mdesc->pv_fixup)
1522 return;
1523
1524 offset = mdesc->pv_fixup();
1525 if (offset == 0)
1526 return;
1527
1528 pr_crit("Physical address space modification is only to support Keystone2.\n");
1529 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1530 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1531 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1532}
1533
1534#endif
1535
1536static void __init early_fixmap_shutdown(void)
1537{
1538 int i;
1539 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1540
1541 pte_offset_fixmap = pte_offset_late_fixmap;
1542 pmd_clear(fixmap_pmd(va));
1543 local_flush_tlb_kernel_page(va);
1544
1545 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1546 pte_t *pte;
1547 struct map_desc map;
1548
1549 map.virtual = fix_to_virt(i);
1550 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1551
1552
1553 if (pte_none(*pte) ||
1554 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1555 continue;
1556
1557 map.pfn = pte_pfn(*pte);
1558 map.type = MT_DEVICE;
1559 map.length = PAGE_SIZE;
1560
1561 create_mapping(&map);
1562 }
1563}
1564
1565
1566
1567
1568
1569void __init paging_init(const struct machine_desc *mdesc)
1570{
1571 void *zero_page;
1572
1573 build_mem_type_table();
1574 prepare_page_table();
1575 map_lowmem();
1576 memblock_set_current_limit(arm_lowmem_limit);
1577 dma_contiguous_remap();
1578 early_fixmap_shutdown();
1579 devicemaps_init(mdesc);
1580 kmap_init();
1581 tcm_init();
1582
1583 top_pmd = pmd_off_k(0xffff0000);
1584
1585
1586 zero_page = early_alloc(PAGE_SIZE);
1587
1588 bootmem_init();
1589
1590 empty_zero_page = virt_to_page(zero_page);
1591 __flush_dcache_page(NULL, empty_zero_page);
1592}
1593