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9#include <linux/device.h>
10#include <linux/export.h>
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/nand.h>
16#include <linux/mtd/partitions.h>
17#include <linux/mtd/plat-ram.h>
18#include <linux/mtd/physmap.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/flash.h>
21#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
22#include <linux/usb/isp1362.h>
23#endif
24#include <linux/i2c.h>
25#include <linux/i2c/adp5588.h>
26#include <linux/etherdevice.h>
27#include <linux/ata_platform.h>
28#include <linux/irq.h>
29#include <linux/interrupt.h>
30#include <linux/usb/sl811.h>
31#include <linux/spi/mmc_spi.h>
32#include <linux/leds.h>
33#include <linux/input.h>
34#include <asm/dma.h>
35#include <asm/bfin5xx_spi.h>
36#include <asm/reboot.h>
37#include <asm/portmux.h>
38#include <asm/dpmc.h>
39#include <asm/bfin_sport.h>
40#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
41#include <linux/regulator/fixed.h>
42#endif
43#include <linux/regulator/machine.h>
44#include <linux/regulator/consumer.h>
45#include <linux/regulator/userspace-consumer.h>
46
47
48
49
50const char bfin_board_name[] = "ADI BF537-STAMP";
51
52
53
54
55
56#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
57#include <linux/usb/isp1760.h>
58static struct resource bfin_isp1760_resources[] = {
59 [0] = {
60 .start = 0x203C0000,
61 .end = 0x203C0000 + 0x000fffff,
62 .flags = IORESOURCE_MEM,
63 },
64 [1] = {
65 .start = IRQ_PF7,
66 .end = IRQ_PF7,
67 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
68 },
69};
70
71static struct isp1760_platform_data isp1760_priv = {
72 .is_isp1761 = 0,
73 .bus_width_16 = 1,
74 .port1_otg = 0,
75 .analog_oc = 0,
76 .dack_polarity_high = 0,
77 .dreq_polarity_high = 0,
78};
79
80static struct platform_device bfin_isp1760_device = {
81 .name = "isp1760",
82 .id = 0,
83 .dev = {
84 .platform_data = &isp1760_priv,
85 },
86 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
87 .resource = bfin_isp1760_resources,
88};
89#endif
90
91#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
92#include <linux/gpio_keys.h>
93
94static struct gpio_keys_button bfin_gpio_keys_table[] = {
95 {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
96 {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
97 {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
98 {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
99};
100
101static struct gpio_keys_platform_data bfin_gpio_keys_data = {
102 .buttons = bfin_gpio_keys_table,
103 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
104};
105
106static struct platform_device bfin_device_gpiokeys = {
107 .name = "gpio-keys",
108 .dev = {
109 .platform_data = &bfin_gpio_keys_data,
110 },
111};
112#endif
113
114#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
115static struct resource bfin_pcmcia_cf_resources[] = {
116 {
117 .start = 0x20310000,
118 .end = 0x20312000,
119 .flags = IORESOURCE_MEM,
120 }, {
121 .start = 0x20311000,
122 .end = 0x20311FFF,
123 .flags = IORESOURCE_MEM,
124 }, {
125 .start = IRQ_PF4,
126 .end = IRQ_PF4,
127 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
128 }, {
129 .start = 6,
130 .end = 6,
131 .flags = IORESOURCE_IRQ,
132 },
133};
134
135static struct platform_device bfin_pcmcia_cf_device = {
136 .name = "bfin_cf_pcmcia",
137 .id = -1,
138 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
139 .resource = bfin_pcmcia_cf_resources,
140};
141#endif
142
143#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
144static struct platform_device rtc_device = {
145 .name = "rtc-bfin",
146 .id = -1,
147};
148#endif
149
150#if IS_ENABLED(CONFIG_SMC91X)
151#include <linux/smc91x.h>
152
153static struct smc91x_platdata smc91x_info = {
154 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
155 .leda = RPC_LED_100_10,
156 .ledb = RPC_LED_TX_RX,
157};
158
159static struct resource smc91x_resources[] = {
160 {
161 .name = "smc91x-regs",
162 .start = 0x20300300,
163 .end = 0x20300300 + 16,
164 .flags = IORESOURCE_MEM,
165 }, {
166
167 .start = IRQ_PF7,
168 .end = IRQ_PF7,
169 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
170 },
171};
172static struct platform_device smc91x_device = {
173 .name = "smc91x",
174 .id = 0,
175 .num_resources = ARRAY_SIZE(smc91x_resources),
176 .resource = smc91x_resources,
177 .dev = {
178 .platform_data = &smc91x_info,
179 },
180};
181#endif
182
183#if IS_ENABLED(CONFIG_DM9000)
184static struct resource dm9000_resources[] = {
185 [0] = {
186 .start = 0x203FB800,
187 .end = 0x203FB800 + 1,
188 .flags = IORESOURCE_MEM,
189 },
190 [1] = {
191 .start = 0x203FB804,
192 .end = 0x203FB804 + 1,
193 .flags = IORESOURCE_MEM,
194 },
195 [2] = {
196 .start = IRQ_PF9,
197 .end = IRQ_PF9,
198 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
199 },
200};
201
202static struct platform_device dm9000_device = {
203 .name = "dm9000",
204 .id = -1,
205 .num_resources = ARRAY_SIZE(dm9000_resources),
206 .resource = dm9000_resources,
207};
208#endif
209
210#if IS_ENABLED(CONFIG_USB_SL811_HCD)
211static struct resource sl811_hcd_resources[] = {
212 {
213 .start = 0x20340000,
214 .end = 0x20340000,
215 .flags = IORESOURCE_MEM,
216 }, {
217 .start = 0x20340004,
218 .end = 0x20340004,
219 .flags = IORESOURCE_MEM,
220 }, {
221 .start = IRQ_PF4,
222 .end = IRQ_PF4,
223 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
224 },
225};
226
227#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
228void sl811_port_power(struct device *dev, int is_on)
229{
230 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
231 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
232}
233#endif
234
235static struct sl811_platform_data sl811_priv = {
236 .potpg = 10,
237 .power = 250,
238#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
239 .port_power = &sl811_port_power,
240#endif
241};
242
243static struct platform_device sl811_hcd_device = {
244 .name = "sl811-hcd",
245 .id = 0,
246 .dev = {
247 .platform_data = &sl811_priv,
248 },
249 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
250 .resource = sl811_hcd_resources,
251};
252#endif
253
254#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
255static struct resource isp1362_hcd_resources[] = {
256 {
257 .start = 0x20360000,
258 .end = 0x20360000,
259 .flags = IORESOURCE_MEM,
260 }, {
261 .start = 0x20360004,
262 .end = 0x20360004,
263 .flags = IORESOURCE_MEM,
264 }, {
265 .start = IRQ_PF3,
266 .end = IRQ_PF3,
267 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
268 },
269};
270
271static struct isp1362_platform_data isp1362_priv = {
272 .sel15Kres = 1,
273 .clknotstop = 0,
274 .oc_enable = 0,
275 .int_act_high = 0,
276 .int_edge_triggered = 0,
277 .remote_wakeup_connected = 0,
278 .no_power_switching = 1,
279 .power_switching_mode = 0,
280};
281
282static struct platform_device isp1362_hcd_device = {
283 .name = "isp1362-hcd",
284 .id = 0,
285 .dev = {
286 .platform_data = &isp1362_priv,
287 },
288 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
289 .resource = isp1362_hcd_resources,
290};
291#endif
292
293#if IS_ENABLED(CONFIG_CAN_BFIN)
294static unsigned short bfin_can_peripherals[] = {
295 P_CAN0_RX, P_CAN0_TX, 0
296};
297
298static struct resource bfin_can_resources[] = {
299 {
300 .start = 0xFFC02A00,
301 .end = 0xFFC02FFF,
302 .flags = IORESOURCE_MEM,
303 },
304 {
305 .start = IRQ_CAN_RX,
306 .end = IRQ_CAN_RX,
307 .flags = IORESOURCE_IRQ,
308 },
309 {
310 .start = IRQ_CAN_TX,
311 .end = IRQ_CAN_TX,
312 .flags = IORESOURCE_IRQ,
313 },
314 {
315 .start = IRQ_CAN_ERROR,
316 .end = IRQ_CAN_ERROR,
317 .flags = IORESOURCE_IRQ,
318 },
319};
320
321static struct platform_device bfin_can_device = {
322 .name = "bfin_can",
323 .num_resources = ARRAY_SIZE(bfin_can_resources),
324 .resource = bfin_can_resources,
325 .dev = {
326 .platform_data = &bfin_can_peripherals,
327 },
328};
329#endif
330
331#if IS_ENABLED(CONFIG_BFIN_MAC)
332#include <linux/bfin_mac.h>
333static const unsigned short bfin_mac_peripherals[] = P_MII0;
334
335static struct bfin_phydev_platform_data bfin_phydev_data[] = {
336 {
337 .addr = 1,
338 .irq = PHY_POLL,
339 },
340};
341
342static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
343 .phydev_number = 1,
344 .phydev_data = bfin_phydev_data,
345 .phy_mode = PHY_INTERFACE_MODE_MII,
346 .mac_peripherals = bfin_mac_peripherals,
347};
348
349static struct platform_device bfin_mii_bus = {
350 .name = "bfin_mii_bus",
351 .dev = {
352 .platform_data = &bfin_mii_bus_data,
353 }
354};
355
356static struct platform_device bfin_mac_device = {
357 .name = "bfin_mac",
358 .dev = {
359 .platform_data = &bfin_mii_bus,
360 }
361};
362#endif
363
364#if IS_ENABLED(CONFIG_USB_NET2272)
365static struct resource net2272_bfin_resources[] = {
366 {
367 .start = 0x20300000,
368 .end = 0x20300000 + 0x100,
369 .flags = IORESOURCE_MEM,
370 }, {
371 .start = 1,
372 .flags = IORESOURCE_BUS,
373 }, {
374 .start = IRQ_PF7,
375 .end = IRQ_PF7,
376 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
377 },
378};
379
380static struct platform_device net2272_bfin_device = {
381 .name = "net2272",
382 .id = -1,
383 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
384 .resource = net2272_bfin_resources,
385};
386#endif
387
388#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
389const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
390
391static struct mtd_partition bfin_plat_nand_partitions[] = {
392 {
393 .name = "linux kernel(nand)",
394 .size = 0x400000,
395 .offset = 0,
396 }, {
397 .name = "file system(nand)",
398 .size = MTDPART_SIZ_FULL,
399 .offset = MTDPART_OFS_APPEND,
400 },
401};
402
403#define BFIN_NAND_PLAT_CLE 2
404#define BFIN_NAND_PLAT_ALE 1
405static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
406{
407 struct nand_chip *this = mtd->priv;
408
409 if (cmd == NAND_CMD_NONE)
410 return;
411
412 if (ctrl & NAND_CLE)
413 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
414 else
415 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
416}
417
418#define BFIN_NAND_PLAT_READY GPIO_PF3
419static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
420{
421 return gpio_get_value(BFIN_NAND_PLAT_READY);
422}
423
424static struct platform_nand_data bfin_plat_nand_data = {
425 .chip = {
426 .nr_chips = 1,
427 .chip_delay = 30,
428 .part_probe_types = part_probes,
429 .partitions = bfin_plat_nand_partitions,
430 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
431 },
432 .ctrl = {
433 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
434 .dev_ready = bfin_plat_nand_dev_ready,
435 },
436};
437
438#define MAX(x, y) (x > y ? x : y)
439static struct resource bfin_plat_nand_resources = {
440 .start = 0x20212000,
441 .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
442 .flags = IORESOURCE_MEM,
443};
444
445static struct platform_device bfin_async_nand_device = {
446 .name = "gen_nand",
447 .id = -1,
448 .num_resources = 1,
449 .resource = &bfin_plat_nand_resources,
450 .dev = {
451 .platform_data = &bfin_plat_nand_data,
452 },
453};
454
455static void bfin_plat_nand_init(void)
456{
457 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
458 gpio_direction_input(BFIN_NAND_PLAT_READY);
459}
460#else
461static void bfin_plat_nand_init(void) {}
462#endif
463
464#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
465static struct mtd_partition stamp_partitions[] = {
466 {
467 .name = "bootloader(nor)",
468 .size = 0x40000,
469 .offset = 0,
470 }, {
471 .name = "linux kernel(nor)",
472 .size = 0x180000,
473 .offset = MTDPART_OFS_APPEND,
474 }, {
475 .name = "file system(nor)",
476 .size = 0x400000 - 0x40000 - 0x180000 - 0x10000,
477 .offset = MTDPART_OFS_APPEND,
478 }, {
479 .name = "MAC Address(nor)",
480 .size = MTDPART_SIZ_FULL,
481 .offset = 0x3F0000,
482 .mask_flags = MTD_WRITEABLE,
483 }
484};
485
486static struct physmap_flash_data stamp_flash_data = {
487 .width = 2,
488 .parts = stamp_partitions,
489 .nr_parts = ARRAY_SIZE(stamp_partitions),
490#ifdef CONFIG_ROMKERNEL
491 .probe_type = "map_rom",
492#endif
493};
494
495static struct resource stamp_flash_resource = {
496 .start = 0x20000000,
497 .end = 0x203fffff,
498 .flags = IORESOURCE_MEM,
499};
500
501static struct platform_device stamp_flash_device = {
502 .name = "physmap-flash",
503 .id = 0,
504 .dev = {
505 .platform_data = &stamp_flash_data,
506 },
507 .num_resources = 1,
508 .resource = &stamp_flash_resource,
509};
510#endif
511
512#if IS_ENABLED(CONFIG_MTD_M25P80)
513static struct mtd_partition bfin_spi_flash_partitions[] = {
514 {
515 .name = "bootloader(spi)",
516 .size = 0x00040000,
517 .offset = 0,
518 .mask_flags = MTD_CAP_ROM
519 }, {
520 .name = "linux kernel(spi)",
521 .size = 0x180000,
522 .offset = MTDPART_OFS_APPEND,
523 }, {
524 .name = "file system(spi)",
525 .size = MTDPART_SIZ_FULL,
526 .offset = MTDPART_OFS_APPEND,
527 }
528};
529
530static struct flash_platform_data bfin_spi_flash_data = {
531 .name = "m25p80",
532 .parts = bfin_spi_flash_partitions,
533 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
534
535};
536
537
538static struct bfin5xx_spi_chip spi_flash_chip_info = {
539 .enable_dma = 0,
540};
541#endif
542
543#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI)
544#include <linux/input/ad714x.h>
545
546static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
547 {
548 .start_stage = 0,
549 .end_stage = 7,
550 .max_coord = 128,
551 },
552};
553
554static struct ad714x_button_plat ad7147_spi_button_plat[] = {
555 {
556 .keycode = BTN_FORWARD,
557 .l_mask = 0,
558 .h_mask = 0x600,
559 },
560 {
561 .keycode = BTN_LEFT,
562 .l_mask = 0,
563 .h_mask = 0x500,
564 },
565 {
566 .keycode = BTN_MIDDLE,
567 .l_mask = 0,
568 .h_mask = 0x800,
569 },
570 {
571 .keycode = BTN_RIGHT,
572 .l_mask = 0x100,
573 .h_mask = 0x400,
574 },
575 {
576 .keycode = BTN_BACK,
577 .l_mask = 0x200,
578 .h_mask = 0x400,
579 },
580};
581static struct ad714x_platform_data ad7147_spi_platform_data = {
582 .slider_num = 1,
583 .button_num = 5,
584 .slider = ad7147_spi_slider_plat,
585 .button = ad7147_spi_button_plat,
586 .stage_cfg_reg = {
587 {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600},
588 {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650},
589 {0xFFFF, 0x1FFE, 0, 0x2626, 1650, 1650, 1650, 1650},
590 {0xFFFF, 0x1FFB, 0, 0x2626, 1650, 1650, 1650, 1650},
591 {0xFFFF, 0x1FEF, 0, 0x2626, 1650, 1650, 1650, 1650},
592 {0xFFFF, 0x1FBF, 0, 0x2626, 1650, 1650, 1650, 1650},
593 {0xFFFF, 0x1EFF, 0, 0x2626, 1650, 1650, 1650, 1650},
594 {0xFFFF, 0x1BFF, 0, 0x2626, 1600, 1600, 1600, 1600},
595 {0xFF7B, 0x3FFF, 0x506, 0x2626, 1100, 1100, 1150, 1150},
596 {0xFDFE, 0x3FFF, 0x606, 0x2626, 1100, 1100, 1150, 1150},
597 {0xFEBA, 0x1FFF, 0x1400, 0x2626, 1200, 1200, 1300, 1300},
598 {0xFFEF, 0x1FFF, 0x0, 0x2626, 1100, 1100, 1150, 1150},
599 },
600 .sys_cfg_reg = {0x2B2, 0x0, 0x3233, 0x819, 0x832, 0xCFF, 0xCFF, 0x0},
601};
602#endif
603
604#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C)
605#include <linux/input/ad714x.h>
606static struct ad714x_button_plat ad7142_i2c_button_plat[] = {
607 {
608 .keycode = BTN_1,
609 .l_mask = 0,
610 .h_mask = 0x1,
611 },
612 {
613 .keycode = BTN_2,
614 .l_mask = 0,
615 .h_mask = 0x2,
616 },
617 {
618 .keycode = BTN_3,
619 .l_mask = 0,
620 .h_mask = 0x4,
621 },
622 {
623 .keycode = BTN_4,
624 .l_mask = 0x0,
625 .h_mask = 0x8,
626 },
627};
628static struct ad714x_platform_data ad7142_i2c_platform_data = {
629 .button_num = 4,
630 .button = ad7142_i2c_button_plat,
631 .stage_cfg_reg = {
632
633
634 {0xE7FF, 0x3FFF, 0x0005, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
635 {0xFDBF, 0x3FFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
636 {0xFFFF, 0x2DFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
637 {0xFFFF, 0x37BF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
638 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
639 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
640 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
641 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
642 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
643 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
644 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
645 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
646 },
647 .sys_cfg_reg = {0x0B2, 0x0, 0x690, 0x664, 0x290F, 0xF, 0xF, 0x0},
648};
649#endif
650
651#if IS_ENABLED(CONFIG_AD2S90)
652static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
653 .enable_dma = 0,
654};
655#endif
656
657#if IS_ENABLED(CONFIG_AD2S1200)
658static unsigned short ad2s1200_platform_data[] = {
659
660 GPIO_PF5, GPIO_PF6, 0
661};
662
663static struct bfin5xx_spi_chip ad2s1200_spi_chip_info = {
664 .enable_dma = 0,
665};
666#endif
667
668#if IS_ENABLED(CONFIG_AD2S1210)
669static unsigned short ad2s1210_platform_data[] = {
670
671 GPIO_PF7, GPIO_PF8, GPIO_PF9,
672# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT)
673
674 GPIO_PF4, GPIO_PF5,
675# endif
676 0,
677};
678
679static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = {
680 .enable_dma = 0,
681};
682#endif
683
684#if IS_ENABLED(CONFIG_SENSORS_AD7314)
685static struct bfin5xx_spi_chip ad7314_spi_chip_info = {
686 .enable_dma = 0,
687};
688#endif
689
690#if IS_ENABLED(CONFIG_AD7816)
691static unsigned short ad7816_platform_data[] = {
692 GPIO_PF4,
693 GPIO_PF5,
694 GPIO_PF7,
695 0,
696};
697
698static struct bfin5xx_spi_chip ad7816_spi_chip_info = {
699 .enable_dma = 0,
700};
701#endif
702
703#if IS_ENABLED(CONFIG_ADT7310)
704static unsigned long adt7310_platform_data[3] = {
705
706 IRQ_PG4, IRQF_TRIGGER_LOW,
707
708 IRQF_TRIGGER_LOW,
709};
710
711static struct bfin5xx_spi_chip adt7310_spi_chip_info = {
712 .enable_dma = 0,
713};
714#endif
715
716#if IS_ENABLED(CONFIG_AD7298)
717static unsigned short ad7298_platform_data[] = {
718 GPIO_PF7,
719 0,
720};
721#endif
722
723#if IS_ENABLED(CONFIG_ADT7316_SPI)
724static unsigned long adt7316_spi_data[2] = {
725 IRQF_TRIGGER_LOW,
726 GPIO_PF7,
727};
728
729static struct bfin5xx_spi_chip adt7316_spi_chip_info = {
730 .enable_dma = 0,
731};
732#endif
733
734#if IS_ENABLED(CONFIG_MMC_SPI)
735#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
736
737static int bfin_mmc_spi_init(struct device *dev,
738 irqreturn_t (*detect_int)(int, void *), void *data)
739{
740 return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
741 IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
742}
743
744static void bfin_mmc_spi_exit(struct device *dev, void *data)
745{
746 free_irq(MMC_SPI_CARD_DETECT_INT, data);
747}
748
749static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
750 .init = bfin_mmc_spi_init,
751 .exit = bfin_mmc_spi_exit,
752 .detect_delay = 100,
753};
754
755static struct bfin5xx_spi_chip mmc_spi_chip_info = {
756 .enable_dma = 0,
757 .pio_interrupt = 0,
758};
759#endif
760
761#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
762#include <linux/spi/ad7877.h>
763static const struct ad7877_platform_data bfin_ad7877_ts_info = {
764 .model = 7877,
765 .vref_delay_usecs = 50,
766 .x_plate_ohms = 419,
767 .y_plate_ohms = 486,
768 .pressure_max = 1000,
769 .pressure_min = 0,
770 .stopacq_polarity = 1,
771 .first_conversion_delay = 3,
772 .acquisition_time = 1,
773 .averaging = 1,
774 .pen_down_acc_interval = 1,
775};
776#endif
777
778#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
779#include <linux/spi/ad7879.h>
780static const struct ad7879_platform_data bfin_ad7879_ts_info = {
781 .model = 7879,
782 .x_plate_ohms = 620,
783 .pressure_max = 10000,
784 .pressure_min = 0,
785 .first_conversion_delay = 3,
786 .acquisition_time = 1,
787 .median = 2,
788 .averaging = 1,
789 .pen_down_acc_interval = 255,
790 .gpio_export = 1,
791 .gpio_base = -1,
792};
793#endif
794
795#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
796#include <linux/input/adxl34x.h>
797static const struct adxl34x_platform_data adxl34x_info = {
798 .x_axis_offset = 0,
799 .y_axis_offset = 0,
800 .z_axis_offset = 0,
801 .tap_threshold = 0x31,
802 .tap_duration = 0x10,
803 .tap_latency = 0x60,
804 .tap_window = 0xF0,
805 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
806 .act_axis_control = 0xFF,
807 .activity_threshold = 5,
808 .inactivity_threshold = 3,
809 .inactivity_time = 4,
810 .free_fall_threshold = 0x7,
811 .free_fall_time = 0x20,
812 .data_rate = 0x8,
813 .data_range = ADXL_FULL_RES,
814
815 .ev_type = EV_ABS,
816 .ev_code_x = ABS_X,
817 .ev_code_y = ABS_Y,
818 .ev_code_z = ABS_Z,
819
820 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH},
821
822
823
824 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
825 .fifo_mode = ADXL_FIFO_STREAM,
826 .orientation_enable = ADXL_EN_ORIENTATION_3D,
827 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
828 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
829
830 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
831};
832#endif
833
834#if IS_ENABLED(CONFIG_ENC28J60)
835static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
836 .enable_dma = 1,
837};
838#endif
839
840#if IS_ENABLED(CONFIG_ADF702X)
841#include <linux/spi/adf702x.h>
842#define TXREG 0x0160A470
843static const u32 adf7021_regs[] = {
844 0x09608FA0,
845 0x00575011,
846 0x00A7F092,
847 0x2B141563,
848 0x81F29E94,
849 0x00003155,
850 0x050A4F66,
851 0x00000007,
852 0x00000008,
853 0x000231E9,
854 0x3296354A,
855 0x891A2B3B,
856 0x00000D9C,
857 0x0000000D,
858 0x0000000E,
859 0x0000000F,
860};
861
862static struct adf702x_platform_data adf7021_platform_data = {
863 .regs_base = (void *)SPORT1_TCR1,
864 .dma_ch_rx = CH_SPORT1_RX,
865 .dma_ch_tx = CH_SPORT1_TX,
866 .irq_sport_err = IRQ_SPORT1_ERROR,
867 .gpio_int_rfs = GPIO_PF8,
868 .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI,
869 P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0},
870 .adf702x_model = MODEL_ADF7021,
871 .adf702x_regs = adf7021_regs,
872 .tx_reg = TXREG,
873};
874static inline void adf702x_mac_init(void)
875{
876 eth_random_addr(adf7021_platform_data.mac_addr);
877}
878#else
879static inline void adf702x_mac_init(void) {}
880#endif
881
882#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
883#include <linux/spi/ads7846.h>
884static int ads7873_get_pendown_state(void)
885{
886 return gpio_get_value(GPIO_PF6);
887}
888
889static struct ads7846_platform_data __initdata ad7873_pdata = {
890 .model = 7873,
891 .x_max = 0xfff,
892 .y_max = 0xfff,
893 .x_plate_ohms = 620,
894 .debounce_max = 1,
895 .debounce_rep = 0,
896 .debounce_tol = (~0),
897 .get_pendown_state = ads7873_get_pendown_state,
898};
899#endif
900
901#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
902
903static struct mtd_partition bfin_spi_dataflash_partitions[] = {
904 {
905 .name = "bootloader(spi)",
906 .size = 0x00040000,
907 .offset = 0,
908 .mask_flags = MTD_CAP_ROM
909 }, {
910 .name = "linux kernel(spi)",
911 .size = 0x180000,
912 .offset = MTDPART_OFS_APPEND,
913 }, {
914 .name = "file system(spi)",
915 .size = MTDPART_SIZ_FULL,
916 .offset = MTDPART_OFS_APPEND,
917 }
918};
919
920static struct flash_platform_data bfin_spi_dataflash_data = {
921 .name = "SPI Dataflash",
922 .parts = bfin_spi_dataflash_partitions,
923 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
924};
925
926
927static struct bfin5xx_spi_chip data_flash_chip_info = {
928 .enable_dma = 0,
929};
930#endif
931
932#if IS_ENABLED(CONFIG_AD7476)
933static struct bfin5xx_spi_chip spi_ad7476_chip_info = {
934 .enable_dma = 0,
935};
936#endif
937
938static struct spi_board_info bfin_spi_board_info[] __initdata = {
939#if IS_ENABLED(CONFIG_MTD_M25P80)
940 {
941
942 .modalias = "m25p80",
943 .max_speed_hz = 25000000,
944 .bus_num = 0,
945 .chip_select = 1,
946 .platform_data = &bfin_spi_flash_data,
947 .controller_data = &spi_flash_chip_info,
948 .mode = SPI_MODE_3,
949 },
950#endif
951#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
952 {
953 .modalias = "mtd_dataflash",
954 .max_speed_hz = 33250000,
955 .bus_num = 0,
956 .chip_select = 1,
957 .platform_data = &bfin_spi_dataflash_data,
958 .controller_data = &data_flash_chip_info,
959 .mode = SPI_MODE_3,
960 },
961#endif
962
963#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
964 {
965 .modalias = "ad1836",
966 .max_speed_hz = 3125000,
967 .bus_num = 0,
968 .chip_select = 4,
969 .platform_data = "ad1836",
970 .mode = SPI_MODE_3,
971 },
972#endif
973
974#ifdef CONFIG_SND_SOC_AD193X_SPI
975 {
976 .modalias = "ad193x",
977 .max_speed_hz = 3125000,
978 .bus_num = 0,
979 .chip_select = 5,
980 .mode = SPI_MODE_3,
981 },
982#endif
983
984#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X)
985 {
986 .modalias = "adav801",
987 .max_speed_hz = 3125000,
988 .bus_num = 0,
989 .chip_select = 1,
990 .mode = SPI_MODE_3,
991 },
992#endif
993
994#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI)
995 {
996 .modalias = "ad714x_captouch",
997 .max_speed_hz = 1000000,
998 .irq = IRQ_PF4,
999 .bus_num = 0,
1000 .chip_select = 5,
1001 .mode = SPI_MODE_3,
1002 .platform_data = &ad7147_spi_platform_data,
1003 },
1004#endif
1005
1006#if IS_ENABLED(CONFIG_AD2S90)
1007 {
1008 .modalias = "ad2s90",
1009 .bus_num = 0,
1010 .chip_select = 3,
1011 .mode = SPI_MODE_3,
1012 .platform_data = NULL,
1013 .controller_data = &ad2s90_spi_chip_info,
1014 },
1015#endif
1016
1017#if IS_ENABLED(CONFIG_AD2S1200)
1018 {
1019 .modalias = "ad2s1200",
1020 .bus_num = 0,
1021 .chip_select = 4,
1022 .platform_data = ad2s1200_platform_data,
1023 .controller_data = &ad2s1200_spi_chip_info,
1024 },
1025#endif
1026
1027#if IS_ENABLED(CONFIG_AD2S1210)
1028 {
1029 .modalias = "ad2s1210",
1030 .max_speed_hz = 8192000,
1031 .bus_num = 0,
1032 .chip_select = 4,
1033 .platform_data = ad2s1210_platform_data,
1034 .controller_data = &ad2s1210_spi_chip_info,
1035 },
1036#endif
1037
1038#if IS_ENABLED(CONFIG_SENSORS_AD7314)
1039 {
1040 .modalias = "ad7314",
1041 .max_speed_hz = 1000000,
1042 .bus_num = 0,
1043 .chip_select = 4,
1044 .controller_data = &ad7314_spi_chip_info,
1045 .mode = SPI_MODE_1,
1046 },
1047#endif
1048
1049#if IS_ENABLED(CONFIG_AD7816)
1050 {
1051 .modalias = "ad7818",
1052 .max_speed_hz = 1000000,
1053 .bus_num = 0,
1054 .chip_select = 4,
1055 .platform_data = ad7816_platform_data,
1056 .controller_data = &ad7816_spi_chip_info,
1057 .mode = SPI_MODE_3,
1058 },
1059#endif
1060
1061#if IS_ENABLED(CONFIG_ADT7310)
1062 {
1063 .modalias = "adt7310",
1064 .max_speed_hz = 1000000,
1065 .irq = IRQ_PG5,
1066 .bus_num = 0,
1067 .chip_select = 4,
1068 .platform_data = adt7310_platform_data,
1069 .controller_data = &adt7310_spi_chip_info,
1070 .mode = SPI_MODE_3,
1071 },
1072#endif
1073
1074#if IS_ENABLED(CONFIG_AD7298)
1075 {
1076 .modalias = "ad7298",
1077 .max_speed_hz = 1000000,
1078 .bus_num = 0,
1079 .chip_select = 4,
1080 .platform_data = ad7298_platform_data,
1081 .mode = SPI_MODE_3,
1082 },
1083#endif
1084
1085#if IS_ENABLED(CONFIG_ADT7316_SPI)
1086 {
1087 .modalias = "adt7316",
1088 .max_speed_hz = 1000000,
1089 .irq = IRQ_PG5,
1090 .bus_num = 0,
1091 .chip_select = 4,
1092 .platform_data = adt7316_spi_data,
1093 .controller_data = &adt7316_spi_chip_info,
1094 .mode = SPI_MODE_3,
1095 },
1096#endif
1097
1098#if IS_ENABLED(CONFIG_MMC_SPI)
1099 {
1100 .modalias = "mmc_spi",
1101 .max_speed_hz = 20000000,
1102 .bus_num = 0,
1103 .chip_select = 4,
1104 .platform_data = &bfin_mmc_spi_pdata,
1105 .controller_data = &mmc_spi_chip_info,
1106 .mode = SPI_MODE_3,
1107 },
1108#endif
1109#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1110 {
1111 .modalias = "ad7877",
1112 .platform_data = &bfin_ad7877_ts_info,
1113 .irq = IRQ_PF6,
1114 .max_speed_hz = 12500000,
1115 .bus_num = 0,
1116 .chip_select = 1,
1117 },
1118#endif
1119#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
1120 {
1121 .modalias = "ad7879",
1122 .platform_data = &bfin_ad7879_ts_info,
1123 .irq = IRQ_PF7,
1124 .max_speed_hz = 5000000,
1125 .bus_num = 0,
1126 .chip_select = 1,
1127 .mode = SPI_CPHA | SPI_CPOL,
1128 },
1129#endif
1130#if IS_ENABLED(CONFIG_SPI_SPIDEV)
1131 {
1132 .modalias = "spidev",
1133 .max_speed_hz = 3125000,
1134 .bus_num = 0,
1135 .chip_select = 1,
1136 },
1137#endif
1138#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
1139 {
1140 .modalias = "bfin-lq035q1-spi",
1141 .max_speed_hz = 20000000,
1142 .bus_num = 0,
1143 .chip_select = 2,
1144 .mode = SPI_CPHA | SPI_CPOL,
1145 },
1146#endif
1147#if IS_ENABLED(CONFIG_ENC28J60)
1148 {
1149 .modalias = "enc28j60",
1150 .max_speed_hz = 20000000,
1151 .irq = IRQ_PF6,
1152 .bus_num = 0,
1153 .chip_select = GPIO_PF10 + MAX_CTRL_CS,
1154 .controller_data = &enc28j60_spi_chip_info,
1155 .mode = SPI_MODE_0,
1156 },
1157#endif
1158#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
1159 {
1160 .modalias = "adxl34x",
1161 .platform_data = &adxl34x_info,
1162 .irq = IRQ_PF6,
1163 .max_speed_hz = 5000000,
1164 .bus_num = 0,
1165 .chip_select = 2,
1166 .mode = SPI_MODE_3,
1167 },
1168#endif
1169#if IS_ENABLED(CONFIG_ADF702X)
1170 {
1171 .modalias = "adf702x",
1172 .max_speed_hz = 16000000,
1173 .bus_num = 0,
1174 .chip_select = GPIO_PF10 + MAX_CTRL_CS,
1175 .platform_data = &adf7021_platform_data,
1176 .mode = SPI_MODE_0,
1177 },
1178#endif
1179#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
1180 {
1181 .modalias = "ads7846",
1182 .max_speed_hz = 2000000,
1183 .bus_num = 0,
1184 .irq = IRQ_PF6,
1185 .chip_select = GPIO_PF10 + MAX_CTRL_CS,
1186 .platform_data = &ad7873_pdata,
1187 .mode = SPI_MODE_0,
1188 },
1189#endif
1190#if IS_ENABLED(CONFIG_AD7476)
1191 {
1192 .modalias = "ad7476",
1193 .max_speed_hz = 6250000,
1194 .bus_num = 0,
1195 .chip_select = 1,
1196 .platform_data = NULL,
1197 .controller_data = &spi_ad7476_chip_info,
1198 .mode = SPI_MODE_3,
1199 },
1200#endif
1201#if IS_ENABLED(CONFIG_ADE7753)
1202 {
1203 .modalias = "ade7753",
1204 .max_speed_hz = 1000000,
1205 .bus_num = 0,
1206 .chip_select = 1,
1207 .platform_data = NULL,
1208 .mode = SPI_MODE_1,
1209 },
1210#endif
1211#if IS_ENABLED(CONFIG_ADE7754)
1212 {
1213 .modalias = "ade7754",
1214 .max_speed_hz = 1000000,
1215 .bus_num = 0,
1216 .chip_select = 1,
1217 .platform_data = NULL,
1218 .mode = SPI_MODE_1,
1219 },
1220#endif
1221#if IS_ENABLED(CONFIG_ADE7758)
1222 {
1223 .modalias = "ade7758",
1224 .max_speed_hz = 1000000,
1225 .bus_num = 0,
1226 .chip_select = 1,
1227 .platform_data = NULL,
1228 .mode = SPI_MODE_1,
1229 },
1230#endif
1231#if IS_ENABLED(CONFIG_ADE7759)
1232 {
1233 .modalias = "ade7759",
1234 .max_speed_hz = 1000000,
1235 .bus_num = 0,
1236 .chip_select = 1,
1237 .platform_data = NULL,
1238 .mode = SPI_MODE_1,
1239 },
1240#endif
1241#if IS_ENABLED(CONFIG_ADE7854_SPI)
1242 {
1243 .modalias = "ade7854",
1244 .max_speed_hz = 1000000,
1245 .bus_num = 0,
1246 .chip_select = 1,
1247 .platform_data = NULL,
1248 .mode = SPI_MODE_3,
1249 },
1250#endif
1251#if IS_ENABLED(CONFIG_ADIS16060)
1252 {
1253 .modalias = "adis16060_r",
1254 .max_speed_hz = 2900000,
1255 .bus_num = 0,
1256 .chip_select = MAX_CTRL_CS + 1,
1257 .platform_data = NULL,
1258 .mode = SPI_MODE_0,
1259 },
1260 {
1261 .modalias = "adis16060_w",
1262 .max_speed_hz = 2900000,
1263 .bus_num = 0,
1264 .chip_select = 2,
1265 .platform_data = NULL,
1266 .mode = SPI_MODE_1,
1267 },
1268#endif
1269#if IS_ENABLED(CONFIG_ADIS16130)
1270 {
1271 .modalias = "adis16130",
1272 .max_speed_hz = 1000000,
1273 .bus_num = 0,
1274 .chip_select = 1,
1275 .platform_data = NULL,
1276 .mode = SPI_MODE_3,
1277 },
1278#endif
1279#if IS_ENABLED(CONFIG_ADIS16201)
1280 {
1281 .modalias = "adis16201",
1282 .max_speed_hz = 1000000,
1283 .bus_num = 0,
1284 .chip_select = 5,
1285 .platform_data = NULL,
1286 .mode = SPI_MODE_3,
1287 .irq = IRQ_PF4,
1288 },
1289#endif
1290#if IS_ENABLED(CONFIG_ADIS16203)
1291 {
1292 .modalias = "adis16203",
1293 .max_speed_hz = 1000000,
1294 .bus_num = 0,
1295 .chip_select = 5,
1296 .platform_data = NULL,
1297 .mode = SPI_MODE_3,
1298 .irq = IRQ_PF4,
1299 },
1300#endif
1301#if IS_ENABLED(CONFIG_ADIS16204)
1302 {
1303 .modalias = "adis16204",
1304 .max_speed_hz = 1000000,
1305 .bus_num = 0,
1306 .chip_select = 5,
1307 .platform_data = NULL,
1308 .mode = SPI_MODE_3,
1309 .irq = IRQ_PF4,
1310 },
1311#endif
1312#if IS_ENABLED(CONFIG_ADIS16209)
1313 {
1314 .modalias = "adis16209",
1315 .max_speed_hz = 1000000,
1316 .bus_num = 0,
1317 .chip_select = 5,
1318 .platform_data = NULL,
1319 .mode = SPI_MODE_3,
1320 .irq = IRQ_PF4,
1321 },
1322#endif
1323#if IS_ENABLED(CONFIG_ADIS16220)
1324 {
1325 .modalias = "adis16220",
1326 .max_speed_hz = 2000000,
1327 .bus_num = 0,
1328 .chip_select = 5,
1329 .platform_data = NULL,
1330 .mode = SPI_MODE_3,
1331 .irq = IRQ_PF4,
1332 },
1333#endif
1334#if IS_ENABLED(CONFIG_ADIS16240)
1335 {
1336 .modalias = "adis16240",
1337 .max_speed_hz = 1500000,
1338 .bus_num = 0,
1339 .chip_select = 5,
1340 .platform_data = NULL,
1341 .mode = SPI_MODE_3,
1342 .irq = IRQ_PF4,
1343 },
1344#endif
1345#if IS_ENABLED(CONFIG_ADIS16260)
1346 {
1347 .modalias = "adis16260",
1348 .max_speed_hz = 1500000,
1349 .bus_num = 0,
1350 .chip_select = 5,
1351 .platform_data = NULL,
1352 .mode = SPI_MODE_3,
1353 .irq = IRQ_PF4,
1354 },
1355#endif
1356#if IS_ENABLED(CONFIG_ADIS16261)
1357 {
1358 .modalias = "adis16261",
1359 .max_speed_hz = 2500000,
1360 .bus_num = 0,
1361 .chip_select = 1,
1362 .platform_data = NULL,
1363 .mode = SPI_MODE_3,
1364 },
1365#endif
1366#if IS_ENABLED(CONFIG_ADIS16300)
1367 {
1368 .modalias = "adis16300",
1369 .max_speed_hz = 1000000,
1370 .bus_num = 0,
1371 .chip_select = 5,
1372 .platform_data = NULL,
1373 .mode = SPI_MODE_3,
1374 .irq = IRQ_PF4,
1375 },
1376#endif
1377#if IS_ENABLED(CONFIG_ADIS16350)
1378 {
1379 .modalias = "adis16364",
1380 .max_speed_hz = 1000000,
1381 .bus_num = 0,
1382 .chip_select = 5,
1383 .platform_data = NULL,
1384 .mode = SPI_MODE_3,
1385 .irq = IRQ_PF4,
1386 },
1387#endif
1388#if IS_ENABLED(CONFIG_ADIS16400)
1389 {
1390 .modalias = "adis16400",
1391 .max_speed_hz = 1000000,
1392 .bus_num = 0,
1393 .chip_select = 1,
1394 .platform_data = NULL,
1395 .mode = SPI_MODE_3,
1396 },
1397#endif
1398};
1399
1400#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
1401
1402static struct bfin5xx_spi_master bfin_spi0_info = {
1403 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1404 .enable_dma = 1,
1405 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1406};
1407
1408
1409static struct resource bfin_spi0_resource[] = {
1410 [0] = {
1411 .start = SPI0_REGBASE,
1412 .end = SPI0_REGBASE + 0xFF,
1413 .flags = IORESOURCE_MEM,
1414 },
1415 [1] = {
1416 .start = CH_SPI,
1417 .end = CH_SPI,
1418 .flags = IORESOURCE_DMA,
1419 },
1420 [2] = {
1421 .start = IRQ_SPI,
1422 .end = IRQ_SPI,
1423 .flags = IORESOURCE_IRQ,
1424 },
1425};
1426
1427static struct platform_device bfin_spi0_device = {
1428 .name = "bfin-spi",
1429 .id = 0,
1430 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1431 .resource = bfin_spi0_resource,
1432 .dev = {
1433 .platform_data = &bfin_spi0_info,
1434 },
1435};
1436#endif
1437
1438#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
1439
1440
1441static struct bfin5xx_spi_master bfin_sport_spi0_info = {
1442 .num_chipselect = MAX_BLACKFIN_GPIOS,
1443 .enable_dma = 0,
1444 .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
1445 P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
1446};
1447
1448static struct resource bfin_sport_spi0_resource[] = {
1449 [0] = {
1450 .start = SPORT0_TCR1,
1451 .end = SPORT0_TCR1 + 0xFF,
1452 .flags = IORESOURCE_MEM,
1453 },
1454 [1] = {
1455 .start = IRQ_SPORT0_ERROR,
1456 .end = IRQ_SPORT0_ERROR,
1457 .flags = IORESOURCE_IRQ,
1458 },
1459};
1460
1461static struct platform_device bfin_sport_spi0_device = {
1462 .name = "bfin-sport-spi",
1463 .id = 1,
1464 .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
1465 .resource = bfin_sport_spi0_resource,
1466 .dev = {
1467 .platform_data = &bfin_sport_spi0_info,
1468 },
1469};
1470
1471static struct bfin5xx_spi_master bfin_sport_spi1_info = {
1472 .num_chipselect = MAX_BLACKFIN_GPIOS,
1473 .enable_dma = 0,
1474 .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
1475 P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
1476};
1477
1478static struct resource bfin_sport_spi1_resource[] = {
1479 [0] = {
1480 .start = SPORT1_TCR1,
1481 .end = SPORT1_TCR1 + 0xFF,
1482 .flags = IORESOURCE_MEM,
1483 },
1484 [1] = {
1485 .start = IRQ_SPORT1_ERROR,
1486 .end = IRQ_SPORT1_ERROR,
1487 .flags = IORESOURCE_IRQ,
1488 },
1489};
1490
1491static struct platform_device bfin_sport_spi1_device = {
1492 .name = "bfin-sport-spi",
1493 .id = 2,
1494 .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
1495 .resource = bfin_sport_spi1_resource,
1496 .dev = {
1497 .platform_data = &bfin_sport_spi1_info,
1498 },
1499};
1500
1501#endif
1502
1503#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
1504static struct platform_device bfin_fb_device = {
1505 .name = "bf537_lq035",
1506};
1507#endif
1508
1509#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
1510#include <asm/bfin-lq035q1.h>
1511
1512static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
1513 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
1514 .ppi_mode = USE_RGB565_16_BIT_PPI,
1515 .use_bl = 0,
1516 .gpio_bl = GPIO_PF7,
1517};
1518
1519static struct resource bfin_lq035q1_resources[] = {
1520 {
1521 .start = IRQ_PPI_ERROR,
1522 .end = IRQ_PPI_ERROR,
1523 .flags = IORESOURCE_IRQ,
1524 },
1525};
1526
1527static struct platform_device bfin_lq035q1_device = {
1528 .name = "bfin-lq035q1",
1529 .id = -1,
1530 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
1531 .resource = bfin_lq035q1_resources,
1532 .dev = {
1533 .platform_data = &bfin_lq035q1_data,
1534 },
1535};
1536#endif
1537
1538#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
1539#include <linux/videodev2.h>
1540#include <media/blackfin/bfin_capture.h>
1541#include <media/blackfin/ppi.h>
1542
1543static const unsigned short ppi_req[] = {
1544 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
1545 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
1546 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
1547 0,
1548};
1549
1550static const struct ppi_info ppi_info = {
1551 .type = PPI_TYPE_PPI,
1552 .dma_ch = CH_PPI,
1553 .irq_err = IRQ_PPI_ERROR,
1554 .base = (void __iomem *)PPI_CONTROL,
1555 .pin_req = ppi_req,
1556};
1557
1558#if IS_ENABLED(CONFIG_VIDEO_VS6624)
1559static struct v4l2_input vs6624_inputs[] = {
1560 {
1561 .index = 0,
1562 .name = "Camera",
1563 .type = V4L2_INPUT_TYPE_CAMERA,
1564 .std = V4L2_STD_UNKNOWN,
1565 },
1566};
1567
1568static struct bcap_route vs6624_routes[] = {
1569 {
1570 .input = 0,
1571 .output = 0,
1572 },
1573};
1574
1575static const unsigned vs6624_ce_pin = GPIO_PF10;
1576
1577static struct bfin_capture_config bfin_capture_data = {
1578 .card_name = "BF537",
1579 .inputs = vs6624_inputs,
1580 .num_inputs = ARRAY_SIZE(vs6624_inputs),
1581 .routes = vs6624_routes,
1582 .i2c_adapter_id = 0,
1583 .board_info = {
1584 .type = "vs6624",
1585 .addr = 0x10,
1586 .platform_data = (void *)&vs6624_ce_pin,
1587 },
1588 .ppi_info = &ppi_info,
1589 .ppi_control = (PACK_EN | DLEN_8 | XFR_TYPE | 0x0020),
1590};
1591#endif
1592
1593static struct platform_device bfin_capture_device = {
1594 .name = "bfin_capture",
1595 .dev = {
1596 .platform_data = &bfin_capture_data,
1597 },
1598};
1599#endif
1600
1601#if IS_ENABLED(CONFIG_SERIAL_BFIN)
1602#ifdef CONFIG_SERIAL_BFIN_UART0
1603static struct resource bfin_uart0_resources[] = {
1604 {
1605 .start = UART0_THR,
1606 .end = UART0_GCTL+2,
1607 .flags = IORESOURCE_MEM,
1608 },
1609 {
1610 .start = IRQ_UART0_TX,
1611 .end = IRQ_UART0_TX,
1612 .flags = IORESOURCE_IRQ,
1613 },
1614 {
1615 .start = IRQ_UART0_RX,
1616 .end = IRQ_UART0_RX,
1617 .flags = IORESOURCE_IRQ,
1618 },
1619 {
1620 .start = IRQ_UART0_ERROR,
1621 .end = IRQ_UART0_ERROR,
1622 .flags = IORESOURCE_IRQ,
1623 },
1624 {
1625 .start = CH_UART0_TX,
1626 .end = CH_UART0_TX,
1627 .flags = IORESOURCE_DMA,
1628 },
1629 {
1630 .start = CH_UART0_RX,
1631 .end = CH_UART0_RX,
1632 .flags = IORESOURCE_DMA,
1633 },
1634#ifdef CONFIG_BFIN_UART0_CTSRTS
1635 {
1636 .start = GPIO_PG7,
1637 .end = GPIO_PG7,
1638 .flags = IORESOURCE_IO,
1639 },
1640 {
1641 .start = GPIO_PG6,
1642 .end = GPIO_PG6,
1643 .flags = IORESOURCE_IO,
1644 },
1645#endif
1646};
1647
1648static unsigned short bfin_uart0_peripherals[] = {
1649 P_UART0_TX, P_UART0_RX, 0
1650};
1651
1652static struct platform_device bfin_uart0_device = {
1653 .name = "bfin-uart",
1654 .id = 0,
1655 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
1656 .resource = bfin_uart0_resources,
1657 .dev = {
1658 .platform_data = &bfin_uart0_peripherals,
1659 },
1660};
1661#endif
1662#ifdef CONFIG_SERIAL_BFIN_UART1
1663static struct resource bfin_uart1_resources[] = {
1664 {
1665 .start = UART1_THR,
1666 .end = UART1_GCTL+2,
1667 .flags = IORESOURCE_MEM,
1668 },
1669 {
1670 .start = IRQ_UART1_TX,
1671 .end = IRQ_UART1_TX,
1672 .flags = IORESOURCE_IRQ,
1673 },
1674 {
1675 .start = IRQ_UART1_RX,
1676 .end = IRQ_UART1_RX,
1677 .flags = IORESOURCE_IRQ,
1678 },
1679 {
1680 .start = IRQ_UART1_ERROR,
1681 .end = IRQ_UART1_ERROR,
1682 .flags = IORESOURCE_IRQ,
1683 },
1684 {
1685 .start = CH_UART1_TX,
1686 .end = CH_UART1_TX,
1687 .flags = IORESOURCE_DMA,
1688 },
1689 {
1690 .start = CH_UART1_RX,
1691 .end = CH_UART1_RX,
1692 .flags = IORESOURCE_DMA,
1693 },
1694};
1695
1696static unsigned short bfin_uart1_peripherals[] = {
1697 P_UART1_TX, P_UART1_RX, 0
1698};
1699
1700static struct platform_device bfin_uart1_device = {
1701 .name = "bfin-uart",
1702 .id = 1,
1703 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
1704 .resource = bfin_uart1_resources,
1705 .dev = {
1706 .platform_data = &bfin_uart1_peripherals,
1707 },
1708};
1709#endif
1710#endif
1711
1712#if IS_ENABLED(CONFIG_BFIN_SIR)
1713#ifdef CONFIG_BFIN_SIR0
1714static struct resource bfin_sir0_resources[] = {
1715 {
1716 .start = 0xFFC00400,
1717 .end = 0xFFC004FF,
1718 .flags = IORESOURCE_MEM,
1719 },
1720 {
1721 .start = IRQ_UART0_RX,
1722 .end = IRQ_UART0_RX+1,
1723 .flags = IORESOURCE_IRQ,
1724 },
1725 {
1726 .start = CH_UART0_RX,
1727 .end = CH_UART0_RX+1,
1728 .flags = IORESOURCE_DMA,
1729 },
1730};
1731
1732static struct platform_device bfin_sir0_device = {
1733 .name = "bfin_sir",
1734 .id = 0,
1735 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
1736 .resource = bfin_sir0_resources,
1737};
1738#endif
1739#ifdef CONFIG_BFIN_SIR1
1740static struct resource bfin_sir1_resources[] = {
1741 {
1742 .start = 0xFFC02000,
1743 .end = 0xFFC020FF,
1744 .flags = IORESOURCE_MEM,
1745 },
1746 {
1747 .start = IRQ_UART1_RX,
1748 .end = IRQ_UART1_RX+1,
1749 .flags = IORESOURCE_IRQ,
1750 },
1751 {
1752 .start = CH_UART1_RX,
1753 .end = CH_UART1_RX+1,
1754 .flags = IORESOURCE_DMA,
1755 },
1756};
1757
1758static struct platform_device bfin_sir1_device = {
1759 .name = "bfin_sir",
1760 .id = 1,
1761 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
1762 .resource = bfin_sir1_resources,
1763};
1764#endif
1765#endif
1766
1767#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
1768static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1769
1770static struct resource bfin_twi0_resource[] = {
1771 [0] = {
1772 .start = TWI0_REGBASE,
1773 .end = TWI0_REGBASE,
1774 .flags = IORESOURCE_MEM,
1775 },
1776 [1] = {
1777 .start = IRQ_TWI,
1778 .end = IRQ_TWI,
1779 .flags = IORESOURCE_IRQ,
1780 },
1781};
1782
1783static struct platform_device i2c_bfin_twi_device = {
1784 .name = "i2c-bfin-twi",
1785 .id = 0,
1786 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1787 .resource = bfin_twi0_resource,
1788 .dev = {
1789 .platform_data = &bfin_twi0_pins,
1790 },
1791};
1792#endif
1793
1794#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588)
1795static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
1796 [0] = KEY_GRAVE,
1797 [1] = KEY_1,
1798 [2] = KEY_2,
1799 [3] = KEY_3,
1800 [4] = KEY_4,
1801 [5] = KEY_5,
1802 [6] = KEY_6,
1803 [7] = KEY_7,
1804 [8] = KEY_8,
1805 [9] = KEY_9,
1806 [10] = KEY_0,
1807 [11] = KEY_MINUS,
1808 [12] = KEY_EQUAL,
1809 [13] = KEY_BACKSLASH,
1810 [15] = KEY_KP0,
1811 [16] = KEY_Q,
1812 [17] = KEY_W,
1813 [18] = KEY_E,
1814 [19] = KEY_R,
1815 [20] = KEY_T,
1816 [21] = KEY_Y,
1817 [22] = KEY_U,
1818 [23] = KEY_I,
1819 [24] = KEY_O,
1820 [25] = KEY_P,
1821 [26] = KEY_LEFTBRACE,
1822 [27] = KEY_RIGHTBRACE,
1823 [29] = KEY_KP1,
1824 [30] = KEY_KP2,
1825 [31] = KEY_KP3,
1826 [32] = KEY_A,
1827 [33] = KEY_S,
1828 [34] = KEY_D,
1829 [35] = KEY_F,
1830 [36] = KEY_G,
1831 [37] = KEY_H,
1832 [38] = KEY_J,
1833 [39] = KEY_K,
1834 [40] = KEY_L,
1835 [41] = KEY_SEMICOLON,
1836 [42] = KEY_APOSTROPHE,
1837 [43] = KEY_BACKSLASH,
1838 [45] = KEY_KP4,
1839 [46] = KEY_KP5,
1840 [47] = KEY_KP6,
1841 [48] = KEY_102ND,
1842 [49] = KEY_Z,
1843 [50] = KEY_X,
1844 [51] = KEY_C,
1845 [52] = KEY_V,
1846 [53] = KEY_B,
1847 [54] = KEY_N,
1848 [55] = KEY_M,
1849 [56] = KEY_COMMA,
1850 [57] = KEY_DOT,
1851 [58] = KEY_SLASH,
1852 [60] = KEY_KPDOT,
1853 [61] = KEY_KP7,
1854 [62] = KEY_KP8,
1855 [63] = KEY_KP9,
1856 [64] = KEY_SPACE,
1857 [65] = KEY_BACKSPACE,
1858 [66] = KEY_TAB,
1859 [67] = KEY_KPENTER,
1860 [68] = KEY_ENTER,
1861 [69] = KEY_ESC,
1862 [70] = KEY_DELETE,
1863 [74] = KEY_KPMINUS,
1864 [76] = KEY_UP,
1865 [77] = KEY_DOWN,
1866 [78] = KEY_RIGHT,
1867 [79] = KEY_LEFT,
1868};
1869
1870static struct adp5588_kpad_platform_data adp5588_kpad_data = {
1871 .rows = 8,
1872 .cols = 10,
1873 .keymap = adp5588_keymap,
1874 .keymapsize = ARRAY_SIZE(adp5588_keymap),
1875 .repeat = 0,
1876};
1877#endif
1878
1879#if IS_ENABLED(CONFIG_PMIC_ADP5520)
1880#include <linux/mfd/adp5520.h>
1881
1882
1883
1884
1885
1886static struct adp5520_backlight_platform_data adp5520_backlight_data = {
1887 .fade_in = ADP5520_FADE_T_1200ms,
1888 .fade_out = ADP5520_FADE_T_1200ms,
1889 .fade_led_law = ADP5520_BL_LAW_LINEAR,
1890 .en_ambl_sens = 1,
1891 .abml_filt = ADP5520_BL_AMBL_FILT_640ms,
1892 .l1_daylight_max = ADP5520_BL_CUR_mA(15),
1893 .l1_daylight_dim = ADP5520_BL_CUR_mA(0),
1894 .l2_office_max = ADP5520_BL_CUR_mA(7),
1895 .l2_office_dim = ADP5520_BL_CUR_mA(0),
1896 .l3_dark_max = ADP5520_BL_CUR_mA(3),
1897 .l3_dark_dim = ADP5520_BL_CUR_mA(0),
1898 .l2_trip = ADP5520_L2_COMP_CURR_uA(700),
1899 .l2_hyst = ADP5520_L2_COMP_CURR_uA(50),
1900 .l3_trip = ADP5520_L3_COMP_CURR_uA(80),
1901 .l3_hyst = ADP5520_L3_COMP_CURR_uA(20),
1902};
1903
1904
1905
1906
1907
1908static struct led_info adp5520_leds[] = {
1909 {
1910 .name = "adp5520-led1",
1911 .default_trigger = "none",
1912 .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
1913 },
1914#ifdef ADP5520_EN_ALL_LEDS
1915 {
1916 .name = "adp5520-led2",
1917 .default_trigger = "none",
1918 .flags = FLAG_ID_ADP5520_LED2_ADP5501_LED1,
1919 },
1920 {
1921 .name = "adp5520-led3",
1922 .default_trigger = "none",
1923 .flags = FLAG_ID_ADP5520_LED3_ADP5501_LED2,
1924 },
1925#endif
1926};
1927
1928static struct adp5520_leds_platform_data adp5520_leds_data = {
1929 .num_leds = ARRAY_SIZE(adp5520_leds),
1930 .leds = adp5520_leds,
1931 .fade_in = ADP5520_FADE_T_600ms,
1932 .fade_out = ADP5520_FADE_T_600ms,
1933 .led_on_time = ADP5520_LED_ONT_600ms,
1934};
1935
1936
1937
1938
1939
1940static struct adp5520_gpio_platform_data adp5520_gpio_data = {
1941 .gpio_start = 50,
1942 .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
1943 .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
1944};
1945
1946
1947
1948
1949
1950static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
1951 [ADP5520_KEY(0, 0)] = KEY_GRAVE,
1952 [ADP5520_KEY(0, 1)] = KEY_1,
1953 [ADP5520_KEY(0, 2)] = KEY_2,
1954 [ADP5520_KEY(0, 3)] = KEY_3,
1955 [ADP5520_KEY(1, 0)] = KEY_4,
1956 [ADP5520_KEY(1, 1)] = KEY_5,
1957 [ADP5520_KEY(1, 2)] = KEY_6,
1958 [ADP5520_KEY(1, 3)] = KEY_7,
1959 [ADP5520_KEY(2, 0)] = KEY_8,
1960 [ADP5520_KEY(2, 1)] = KEY_9,
1961 [ADP5520_KEY(2, 2)] = KEY_0,
1962 [ADP5520_KEY(2, 3)] = KEY_MINUS,
1963 [ADP5520_KEY(3, 0)] = KEY_EQUAL,
1964 [ADP5520_KEY(3, 1)] = KEY_BACKSLASH,
1965 [ADP5520_KEY(3, 2)] = KEY_BACKSPACE,
1966 [ADP5520_KEY(3, 3)] = KEY_ENTER,
1967};
1968
1969static struct adp5520_keys_platform_data adp5520_keys_data = {
1970 .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
1971 .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
1972 .keymap = adp5520_keymap,
1973 .keymapsize = ARRAY_SIZE(adp5520_keymap),
1974 .repeat = 0,
1975};
1976
1977
1978
1979
1980
1981static struct adp5520_platform_data adp5520_pdev_data = {
1982 .backlight = &adp5520_backlight_data,
1983 .leds = &adp5520_leds_data,
1984 .gpio = &adp5520_gpio_data,
1985 .keys = &adp5520_keys_data,
1986};
1987
1988#endif
1989
1990#if IS_ENABLED(CONFIG_GPIO_ADP5588)
1991static struct adp5588_gpio_platform_data adp5588_gpio_data = {
1992 .gpio_start = 50,
1993 .pullup_dis_mask = 0,
1994};
1995#endif
1996
1997#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870)
1998#include <linux/i2c/adp8870.h>
1999static struct led_info adp8870_leds[] = {
2000 {
2001 .name = "adp8870-led7",
2002 .default_trigger = "none",
2003 .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms,
2004 },
2005};
2006
2007
2008static struct adp8870_backlight_platform_data adp8870_pdata = {
2009 .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 |
2010 ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6,
2011 .pwm_assign = 0,
2012
2013 .bl_fade_in = ADP8870_FADE_T_1200ms,
2014 .bl_fade_out = ADP8870_FADE_T_1200ms,
2015 .bl_fade_law = ADP8870_FADE_LAW_CUBIC1,
2016
2017 .en_ambl_sens = 1,
2018 .abml_filt = ADP8870_BL_AMBL_FILT_320ms,
2019
2020 .l1_daylight_max = ADP8870_BL_CUR_mA(20),
2021 .l1_daylight_dim = ADP8870_BL_CUR_mA(0),
2022 .l2_bright_max = ADP8870_BL_CUR_mA(14),
2023 .l2_bright_dim = ADP8870_BL_CUR_mA(0),
2024 .l3_office_max = ADP8870_BL_CUR_mA(6),
2025 .l3_office_dim = ADP8870_BL_CUR_mA(0),
2026 .l4_indoor_max = ADP8870_BL_CUR_mA(3),
2027 .l4_indor_dim = ADP8870_BL_CUR_mA(0),
2028 .l5_dark_max = ADP8870_BL_CUR_mA(2),
2029 .l5_dark_dim = ADP8870_BL_CUR_mA(0),
2030
2031 .l2_trip = ADP8870_L2_COMP_CURR_uA(710),
2032 .l2_hyst = ADP8870_L2_COMP_CURR_uA(73),
2033 .l3_trip = ADP8870_L3_COMP_CURR_uA(389),
2034 .l3_hyst = ADP8870_L3_COMP_CURR_uA(54),
2035 .l4_trip = ADP8870_L4_COMP_CURR_uA(167),
2036 .l4_hyst = ADP8870_L4_COMP_CURR_uA(16),
2037 .l5_trip = ADP8870_L5_COMP_CURR_uA(43),
2038 .l5_hyst = ADP8870_L5_COMP_CURR_uA(11),
2039
2040 .leds = adp8870_leds,
2041 .num_leds = ARRAY_SIZE(adp8870_leds),
2042 .led_fade_law = ADP8870_FADE_LAW_SQUARE,
2043 .led_fade_in = ADP8870_FADE_T_600ms,
2044 .led_fade_out = ADP8870_FADE_T_600ms,
2045 .led_on_time = ADP8870_LED_ONT_200ms,
2046};
2047#endif
2048
2049#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860)
2050#include <linux/i2c/adp8860.h>
2051static struct led_info adp8860_leds[] = {
2052 {
2053 .name = "adp8860-led7",
2054 .default_trigger = "none",
2055 .flags = ADP8860_LED_D7 | ADP8860_LED_OFFT_600ms,
2056 },
2057};
2058
2059static struct adp8860_backlight_platform_data adp8860_pdata = {
2060 .bl_led_assign = ADP8860_BL_D1 | ADP8860_BL_D2 | ADP8860_BL_D3 |
2061 ADP8860_BL_D4 | ADP8860_BL_D5 | ADP8860_BL_D6,
2062
2063 .bl_fade_in = ADP8860_FADE_T_1200ms,
2064 .bl_fade_out = ADP8860_FADE_T_1200ms,
2065 .bl_fade_law = ADP8860_FADE_LAW_CUBIC1,
2066
2067 .en_ambl_sens = 1,
2068 .abml_filt = ADP8860_BL_AMBL_FILT_320ms,
2069
2070 .l1_daylight_max = ADP8860_BL_CUR_mA(20),
2071 .l1_daylight_dim = ADP8860_BL_CUR_mA(0),
2072 .l2_office_max = ADP8860_BL_CUR_mA(6),
2073 .l2_office_dim = ADP8860_BL_CUR_mA(0),
2074 .l3_dark_max = ADP8860_BL_CUR_mA(2),
2075 .l3_dark_dim = ADP8860_BL_CUR_mA(0),
2076
2077 .l2_trip = ADP8860_L2_COMP_CURR_uA(710),
2078 .l2_hyst = ADP8860_L2_COMP_CURR_uA(73),
2079 .l3_trip = ADP8860_L3_COMP_CURR_uA(43),
2080 .l3_hyst = ADP8860_L3_COMP_CURR_uA(11),
2081
2082 .leds = adp8860_leds,
2083 .num_leds = ARRAY_SIZE(adp8860_leds),
2084 .led_fade_law = ADP8860_FADE_LAW_SQUARE,
2085 .led_fade_in = ADP8860_FADE_T_600ms,
2086 .led_fade_out = ADP8860_FADE_T_600ms,
2087 .led_on_time = ADP8860_LED_ONT_200ms,
2088};
2089#endif
2090
2091#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
2092static struct regulator_consumer_supply ad5398_consumer = {
2093 .supply = "current",
2094};
2095
2096static struct regulator_init_data ad5398_regulator_data = {
2097 .constraints = {
2098 .name = "current range",
2099 .max_uA = 120000,
2100 .valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS,
2101 },
2102 .num_consumer_supplies = 1,
2103 .consumer_supplies = &ad5398_consumer,
2104};
2105
2106#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER)
2107static struct platform_device ad5398_virt_consumer_device = {
2108 .name = "reg-virt-consumer",
2109 .id = 0,
2110 .dev = {
2111 .platform_data = "current",
2112 },
2113};
2114#endif
2115#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
2116static struct regulator_bulk_data ad5398_bulk_data = {
2117 .supply = "current",
2118};
2119
2120static struct regulator_userspace_consumer_data ad5398_userspace_comsumer_data = {
2121 .name = "ad5398",
2122 .num_supplies = 1,
2123 .supplies = &ad5398_bulk_data,
2124};
2125
2126static struct platform_device ad5398_userspace_consumer_device = {
2127 .name = "reg-userspace-consumer",
2128 .id = 0,
2129 .dev = {
2130 .platform_data = &ad5398_userspace_comsumer_data,
2131 },
2132};
2133#endif
2134#endif
2135
2136#if IS_ENABLED(CONFIG_ADT7410)
2137
2138static unsigned long adt7410_platform_data[2] = {
2139 IRQ_PG4, IRQF_TRIGGER_LOW,
2140};
2141#endif
2142
2143#if IS_ENABLED(CONFIG_ADT7316_I2C)
2144
2145static unsigned long adt7316_i2c_data[2] = {
2146 IRQF_TRIGGER_LOW,
2147 GPIO_PF4,
2148};
2149#endif
2150
2151static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
2152#ifdef CONFIG_SND_SOC_AD193X_I2C
2153 {
2154 I2C_BOARD_INFO("ad1937", 0x04),
2155 },
2156#endif
2157
2158#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X)
2159 {
2160 I2C_BOARD_INFO("adav803", 0x10),
2161 },
2162#endif
2163
2164#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C)
2165 {
2166 I2C_BOARD_INFO("ad7142_captouch", 0x2C),
2167 .irq = IRQ_PG5,
2168 .platform_data = (void *)&ad7142_i2c_platform_data,
2169 },
2170#endif
2171
2172#if IS_ENABLED(CONFIG_AD7150)
2173 {
2174 I2C_BOARD_INFO("ad7150", 0x48),
2175 .irq = IRQ_PG5,
2176 },
2177#endif
2178
2179#if IS_ENABLED(CONFIG_AD7152)
2180 {
2181 I2C_BOARD_INFO("ad7152", 0x48),
2182 },
2183#endif
2184
2185#if IS_ENABLED(CONFIG_AD774X)
2186 {
2187 I2C_BOARD_INFO("ad774x", 0x48),
2188 },
2189#endif
2190
2191#if IS_ENABLED(CONFIG_ADE7854_I2C)
2192 {
2193 I2C_BOARD_INFO("ade7854", 0x38),
2194 },
2195#endif
2196
2197#if IS_ENABLED(CONFIG_SENSORS_LM75)
2198 {
2199 I2C_BOARD_INFO("adt75", 0x9),
2200 .irq = IRQ_PG5,
2201 },
2202#endif
2203
2204#if IS_ENABLED(CONFIG_ADT7410)
2205 {
2206 I2C_BOARD_INFO("adt7410", 0x48),
2207
2208 .irq = IRQ_PG5,
2209 .platform_data = (void *)&adt7410_platform_data,
2210 },
2211#endif
2212
2213#if IS_ENABLED(CONFIG_AD7291)
2214 {
2215 I2C_BOARD_INFO("ad7291", 0x20),
2216 .irq = IRQ_PG5,
2217 },
2218#endif
2219
2220#if IS_ENABLED(CONFIG_ADT7316_I2C)
2221 {
2222 I2C_BOARD_INFO("adt7316", 0x48),
2223 .irq = IRQ_PG6,
2224 .platform_data = (void *)&adt7316_i2c_data,
2225 },
2226#endif
2227
2228#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
2229 {
2230 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
2231 },
2232#endif
2233#if IS_ENABLED(CONFIG_INPUT_PCF8574)
2234 {
2235 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
2236 .irq = IRQ_PG6,
2237 },
2238#endif
2239#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
2240 {
2241 I2C_BOARD_INFO("ad7879", 0x2F),
2242 .irq = IRQ_PG5,
2243 .platform_data = (void *)&bfin_ad7879_ts_info,
2244 },
2245#endif
2246#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588)
2247 {
2248 I2C_BOARD_INFO("adp5588-keys", 0x34),
2249 .irq = IRQ_PG0,
2250 .platform_data = (void *)&adp5588_kpad_data,
2251 },
2252#endif
2253#if IS_ENABLED(CONFIG_PMIC_ADP5520)
2254 {
2255 I2C_BOARD_INFO("pmic-adp5520", 0x32),
2256 .irq = IRQ_PG0,
2257 .platform_data = (void *)&adp5520_pdev_data,
2258 },
2259#endif
2260#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
2261 {
2262 I2C_BOARD_INFO("adxl34x", 0x53),
2263 .irq = IRQ_PG3,
2264 .platform_data = (void *)&adxl34x_info,
2265 },
2266#endif
2267#if IS_ENABLED(CONFIG_GPIO_ADP5588)
2268 {
2269 I2C_BOARD_INFO("adp5588-gpio", 0x34),
2270 .platform_data = (void *)&adp5588_gpio_data,
2271 },
2272#endif
2273#if IS_ENABLED(CONFIG_FB_BFIN_7393)
2274 {
2275 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
2276 },
2277#endif
2278#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
2279 {
2280 I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F),
2281 },
2282#endif
2283#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870)
2284 {
2285 I2C_BOARD_INFO("adp8870", 0x2B),
2286 .platform_data = (void *)&adp8870_pdata,
2287 },
2288#endif
2289#if IS_ENABLED(CONFIG_SND_SOC_ADAU1371)
2290 {
2291 I2C_BOARD_INFO("adau1371", 0x1A),
2292 },
2293#endif
2294#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
2295 {
2296 I2C_BOARD_INFO("adau1761", 0x38),
2297 },
2298#endif
2299#if IS_ENABLED(CONFIG_SND_SOC_ADAU1361)
2300 {
2301 I2C_BOARD_INFO("adau1361", 0x38),
2302 },
2303#endif
2304#if IS_ENABLED(CONFIG_SND_SOC_ADAU1701)
2305 {
2306 I2C_BOARD_INFO("adau1701", 0x34),
2307 },
2308#endif
2309#if IS_ENABLED(CONFIG_AD525X_DPOT)
2310 {
2311 I2C_BOARD_INFO("ad5258", 0x18),
2312 },
2313#endif
2314#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
2315 {
2316 I2C_BOARD_INFO("ssm2602", 0x1b),
2317 },
2318#endif
2319#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
2320 {
2321 I2C_BOARD_INFO("ad5398", 0xC),
2322 .platform_data = (void *)&ad5398_regulator_data,
2323 },
2324#endif
2325#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860)
2326 {
2327 I2C_BOARD_INFO("adp8860", 0x2A),
2328 .platform_data = (void *)&adp8860_pdata,
2329 },
2330#endif
2331#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373)
2332 {
2333 I2C_BOARD_INFO("adau1373", 0x1A),
2334 },
2335#endif
2336#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
2337 {
2338 I2C_BOARD_INFO("ad5252", 0x2e),
2339 },
2340#endif
2341};
2342#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \
2343|| IS_ENABLED(CONFIG_BFIN_SPORT)
2344unsigned short bfin_sport0_peripherals[] = {
2345 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
2346 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
2347};
2348#endif
2349#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
2350#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2351static struct resource bfin_sport0_uart_resources[] = {
2352 {
2353 .start = SPORT0_TCR1,
2354 .end = SPORT0_MRCS3+4,
2355 .flags = IORESOURCE_MEM,
2356 },
2357 {
2358 .start = IRQ_SPORT0_RX,
2359 .end = IRQ_SPORT0_RX+1,
2360 .flags = IORESOURCE_IRQ,
2361 },
2362 {
2363 .start = IRQ_SPORT0_ERROR,
2364 .end = IRQ_SPORT0_ERROR,
2365 .flags = IORESOURCE_IRQ,
2366 },
2367};
2368
2369static struct platform_device bfin_sport0_uart_device = {
2370 .name = "bfin-sport-uart",
2371 .id = 0,
2372 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
2373 .resource = bfin_sport0_uart_resources,
2374 .dev = {
2375 .platform_data = &bfin_sport0_peripherals,
2376 },
2377};
2378#endif
2379#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2380static struct resource bfin_sport1_uart_resources[] = {
2381 {
2382 .start = SPORT1_TCR1,
2383 .end = SPORT1_MRCS3+4,
2384 .flags = IORESOURCE_MEM,
2385 },
2386 {
2387 .start = IRQ_SPORT1_RX,
2388 .end = IRQ_SPORT1_RX+1,
2389 .flags = IORESOURCE_IRQ,
2390 },
2391 {
2392 .start = IRQ_SPORT1_ERROR,
2393 .end = IRQ_SPORT1_ERROR,
2394 .flags = IORESOURCE_IRQ,
2395 },
2396};
2397
2398static unsigned short bfin_sport1_peripherals[] = {
2399 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
2400 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
2401};
2402
2403static struct platform_device bfin_sport1_uart_device = {
2404 .name = "bfin-sport-uart",
2405 .id = 1,
2406 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
2407 .resource = bfin_sport1_uart_resources,
2408 .dev = {
2409 .platform_data = &bfin_sport1_peripherals,
2410 },
2411};
2412#endif
2413#endif
2414#if IS_ENABLED(CONFIG_BFIN_SPORT)
2415static struct resource bfin_sport0_resources[] = {
2416 {
2417 .start = SPORT0_TCR1,
2418 .end = SPORT0_MRCS3+4,
2419 .flags = IORESOURCE_MEM,
2420 },
2421 {
2422 .start = IRQ_SPORT0_RX,
2423 .end = IRQ_SPORT0_RX+1,
2424 .flags = IORESOURCE_IRQ,
2425 },
2426 {
2427 .start = IRQ_SPORT0_TX,
2428 .end = IRQ_SPORT0_TX+1,
2429 .flags = IORESOURCE_IRQ,
2430 },
2431 {
2432 .start = IRQ_SPORT0_ERROR,
2433 .end = IRQ_SPORT0_ERROR,
2434 .flags = IORESOURCE_IRQ,
2435 },
2436 {
2437 .start = CH_SPORT0_TX,
2438 .end = CH_SPORT0_TX,
2439 .flags = IORESOURCE_DMA,
2440 },
2441 {
2442 .start = CH_SPORT0_RX,
2443 .end = CH_SPORT0_RX,
2444 .flags = IORESOURCE_DMA,
2445 },
2446};
2447static struct platform_device bfin_sport0_device = {
2448 .name = "bfin_sport_raw",
2449 .id = 0,
2450 .num_resources = ARRAY_SIZE(bfin_sport0_resources),
2451 .resource = bfin_sport0_resources,
2452 .dev = {
2453 .platform_data = &bfin_sport0_peripherals,
2454 },
2455};
2456#endif
2457#if IS_ENABLED(CONFIG_PATA_PLATFORM)
2458#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
2459
2460
2461#ifdef CF_IDE_NAND_CARD_USE_HDD_INTERFACE
2462#define PATA_INT IRQ_PF5
2463static struct pata_platform_info bfin_pata_platform_data = {
2464 .ioport_shift = 1,
2465};
2466
2467static struct resource bfin_pata_resources[] = {
2468 {
2469 .start = 0x20314020,
2470 .end = 0x2031403F,
2471 .flags = IORESOURCE_MEM,
2472 },
2473 {
2474 .start = 0x2031401C,
2475 .end = 0x2031401F,
2476 .flags = IORESOURCE_MEM,
2477 },
2478 {
2479 .start = PATA_INT,
2480 .end = PATA_INT,
2481 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
2482 },
2483};
2484#elif defined(CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE)
2485static struct pata_platform_info bfin_pata_platform_data = {
2486 .ioport_shift = 0,
2487};
2488
2489
2490
2491static struct resource bfin_pata_resources[] = {
2492 {
2493 .start = 0x20211800,
2494 .end = 0x20211807,
2495 .flags = IORESOURCE_MEM,
2496 },
2497 {
2498 .start = 0x2021180E,
2499 .end = 0x2021180E,
2500 .flags = IORESOURCE_MEM,
2501 },
2502};
2503#endif
2504
2505static struct platform_device bfin_pata_device = {
2506 .name = "pata_platform",
2507 .id = -1,
2508 .num_resources = ARRAY_SIZE(bfin_pata_resources),
2509 .resource = bfin_pata_resources,
2510 .dev = {
2511 .platform_data = &bfin_pata_platform_data,
2512 }
2513};
2514#endif
2515
2516static const unsigned int cclk_vlev_datasheet[] =
2517{
2518 VRPAIR(VLEV_085, 250000000),
2519 VRPAIR(VLEV_090, 376000000),
2520 VRPAIR(VLEV_095, 426000000),
2521 VRPAIR(VLEV_100, 426000000),
2522 VRPAIR(VLEV_105, 476000000),
2523 VRPAIR(VLEV_110, 476000000),
2524 VRPAIR(VLEV_115, 476000000),
2525 VRPAIR(VLEV_120, 500000000),
2526 VRPAIR(VLEV_125, 533000000),
2527 VRPAIR(VLEV_130, 600000000),
2528};
2529
2530static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
2531 .tuple_tab = cclk_vlev_datasheet,
2532 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
2533 .vr_settling_time = 25 ,
2534};
2535
2536static struct platform_device bfin_dpmc = {
2537 .name = "bfin dpmc",
2538 .dev = {
2539 .platform_data = &bfin_dmpc_vreg_data,
2540 },
2541};
2542
2543#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
2544 IS_ENABLED(CONFIG_SND_BF5XX_AC97)
2545
2546#define SPORT_REQ(x) \
2547 [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
2548 P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
2549
2550static const u16 bfin_snd_pin[][7] = {
2551 SPORT_REQ(0),
2552 SPORT_REQ(1),
2553};
2554
2555static struct bfin_snd_platform_data bfin_snd_data[] = {
2556 {
2557 .pin_req = &bfin_snd_pin[0][0],
2558 },
2559 {
2560 .pin_req = &bfin_snd_pin[1][0],
2561 },
2562};
2563
2564#define BFIN_SND_RES(x) \
2565 [x] = { \
2566 { \
2567 .start = SPORT##x##_TCR1, \
2568 .end = SPORT##x##_TCR1, \
2569 .flags = IORESOURCE_MEM \
2570 }, \
2571 { \
2572 .start = CH_SPORT##x##_RX, \
2573 .end = CH_SPORT##x##_RX, \
2574 .flags = IORESOURCE_DMA, \
2575 }, \
2576 { \
2577 .start = CH_SPORT##x##_TX, \
2578 .end = CH_SPORT##x##_TX, \
2579 .flags = IORESOURCE_DMA, \
2580 }, \
2581 { \
2582 .start = IRQ_SPORT##x##_ERROR, \
2583 .end = IRQ_SPORT##x##_ERROR, \
2584 .flags = IORESOURCE_IRQ, \
2585 } \
2586 }
2587
2588static struct resource bfin_snd_resources[][4] = {
2589 BFIN_SND_RES(0),
2590 BFIN_SND_RES(1),
2591};
2592#endif
2593
2594#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
2595static struct platform_device bfin_i2s_pcm = {
2596 .name = "bfin-i2s-pcm-audio",
2597 .id = -1,
2598};
2599#endif
2600
2601#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
2602static struct platform_device bfin_ac97_pcm = {
2603 .name = "bfin-ac97-pcm-audio",
2604 .id = -1,
2605};
2606#endif
2607
2608#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
2609static const char * const ad1836_link[] = {
2610 "bfin-i2s.0",
2611 "spi0.4",
2612};
2613static struct platform_device bfin_ad1836_machine = {
2614 .name = "bfin-snd-ad1836",
2615 .id = -1,
2616 .dev = {
2617 .platform_data = (void *)ad1836_link,
2618 },
2619};
2620#endif
2621
2622#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
2623static const unsigned ad73311_gpio[] = {
2624 GPIO_PF4,
2625};
2626
2627static struct platform_device bfin_ad73311_machine = {
2628 .name = "bfin-snd-ad73311",
2629 .id = 1,
2630 .dev = {
2631 .platform_data = (void *)ad73311_gpio,
2632 },
2633};
2634#endif
2635
2636#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
2637static struct platform_device bfin_ad73311_codec_device = {
2638 .name = "ad73311",
2639 .id = -1,
2640};
2641#endif
2642
2643#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X)
2644static struct platform_device bfin_eval_adav801_device = {
2645 .name = "bfin-eval-adav801",
2646 .id = -1,
2647};
2648#endif
2649
2650#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
2651static struct platform_device bfin_i2s = {
2652 .name = "bfin-i2s",
2653 .id = CONFIG_SND_BF5XX_SPORT_NUM,
2654 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
2655 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
2656 .dev = {
2657 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
2658 },
2659};
2660#endif
2661
2662#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
2663static struct platform_device bfin_ac97 = {
2664 .name = "bfin-ac97",
2665 .id = CONFIG_SND_BF5XX_SPORT_NUM,
2666 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
2667 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
2668 .dev = {
2669 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
2670 },
2671};
2672#endif
2673
2674#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
2675#define REGULATOR_ADP122 "adp122"
2676#define REGULATOR_ADP122_UV 2500000
2677
2678static struct regulator_consumer_supply adp122_consumers = {
2679 .supply = REGULATOR_ADP122,
2680};
2681
2682static struct regulator_init_data adp_switch_regulator_data = {
2683 .constraints = {
2684 .name = REGULATOR_ADP122,
2685 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2686 .min_uV = REGULATOR_ADP122_UV,
2687 .max_uV = REGULATOR_ADP122_UV,
2688 .min_uA = 0,
2689 .max_uA = 300000,
2690 },
2691 .num_consumer_supplies = 1,
2692 .consumer_supplies = &adp122_consumers,
2693};
2694
2695static struct fixed_voltage_config adp_switch_pdata = {
2696 .supply_name = REGULATOR_ADP122,
2697 .microvolts = REGULATOR_ADP122_UV,
2698 .gpio = GPIO_PF2,
2699 .enable_high = 1,
2700 .enabled_at_boot = 0,
2701 .init_data = &adp_switch_regulator_data,
2702};
2703
2704static struct platform_device adp_switch_device = {
2705 .name = "reg-fixed-voltage",
2706 .id = 0,
2707 .dev = {
2708 .platform_data = &adp_switch_pdata,
2709 },
2710};
2711
2712#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
2713static struct regulator_bulk_data adp122_bulk_data = {
2714 .supply = REGULATOR_ADP122,
2715};
2716
2717static struct regulator_userspace_consumer_data adp122_userspace_comsumer_data = {
2718 .name = REGULATOR_ADP122,
2719 .num_supplies = 1,
2720 .supplies = &adp122_bulk_data,
2721};
2722
2723static struct platform_device adp122_userspace_consumer_device = {
2724 .name = "reg-userspace-consumer",
2725 .id = 0,
2726 .dev = {
2727 .platform_data = &adp122_userspace_comsumer_data,
2728 },
2729};
2730#endif
2731#endif
2732
2733#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER)
2734
2735static struct resource iio_gpio_trigger_resources[] = {
2736 [0] = {
2737 .start = IRQ_PF5,
2738 .end = IRQ_PF5,
2739 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
2740 },
2741};
2742
2743static struct platform_device iio_gpio_trigger = {
2744 .name = "iio_gpio_trigger",
2745 .num_resources = ARRAY_SIZE(iio_gpio_trigger_resources),
2746 .resource = iio_gpio_trigger_resources,
2747};
2748#endif
2749
2750#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373)
2751static struct platform_device bf5xx_adau1373_device = {
2752 .name = "bfin-eval-adau1373",
2753};
2754#endif
2755
2756#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701)
2757static struct platform_device bf5xx_adau1701_device = {
2758 .name = "bfin-eval-adau1701",
2759};
2760#endif
2761
2762static struct platform_device *stamp_devices[] __initdata = {
2763
2764 &bfin_dpmc,
2765#if IS_ENABLED(CONFIG_BFIN_SPORT)
2766 &bfin_sport0_device,
2767#endif
2768#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
2769 &bfin_pcmcia_cf_device,
2770#endif
2771
2772#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
2773 &rtc_device,
2774#endif
2775
2776#if IS_ENABLED(CONFIG_USB_SL811_HCD)
2777 &sl811_hcd_device,
2778#endif
2779
2780#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
2781 &isp1362_hcd_device,
2782#endif
2783
2784#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
2785 &bfin_isp1760_device,
2786#endif
2787
2788#if IS_ENABLED(CONFIG_SMC91X)
2789 &smc91x_device,
2790#endif
2791
2792#if IS_ENABLED(CONFIG_DM9000)
2793 &dm9000_device,
2794#endif
2795
2796#if IS_ENABLED(CONFIG_CAN_BFIN)
2797 &bfin_can_device,
2798#endif
2799
2800#if IS_ENABLED(CONFIG_BFIN_MAC)
2801 &bfin_mii_bus,
2802 &bfin_mac_device,
2803#endif
2804
2805#if IS_ENABLED(CONFIG_USB_NET2272)
2806 &net2272_bfin_device,
2807#endif
2808
2809#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
2810 &bfin_spi0_device,
2811#endif
2812
2813#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
2814 &bfin_sport_spi0_device,
2815 &bfin_sport_spi1_device,
2816#endif
2817
2818#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
2819 &bfin_fb_device,
2820#endif
2821
2822#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
2823 &bfin_lq035q1_device,
2824#endif
2825
2826#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
2827 &bfin_capture_device,
2828#endif
2829
2830#if IS_ENABLED(CONFIG_SERIAL_BFIN)
2831#ifdef CONFIG_SERIAL_BFIN_UART0
2832 &bfin_uart0_device,
2833#endif
2834#ifdef CONFIG_SERIAL_BFIN_UART1
2835 &bfin_uart1_device,
2836#endif
2837#endif
2838
2839#if IS_ENABLED(CONFIG_BFIN_SIR)
2840#ifdef CONFIG_BFIN_SIR0
2841 &bfin_sir0_device,
2842#endif
2843#ifdef CONFIG_BFIN_SIR1
2844 &bfin_sir1_device,
2845#endif
2846#endif
2847
2848#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
2849 &i2c_bfin_twi_device,
2850#endif
2851
2852#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
2853#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2854 &bfin_sport0_uart_device,
2855#endif
2856#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2857 &bfin_sport1_uart_device,
2858#endif
2859#endif
2860
2861#if IS_ENABLED(CONFIG_PATA_PLATFORM)
2862 &bfin_pata_device,
2863#endif
2864
2865#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
2866 &bfin_device_gpiokeys,
2867#endif
2868
2869#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
2870 &bfin_async_nand_device,
2871#endif
2872
2873#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
2874 &stamp_flash_device,
2875#endif
2876
2877#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
2878 &bfin_i2s_pcm,
2879#endif
2880
2881#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
2882 &bfin_ac97_pcm,
2883#endif
2884
2885#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
2886 &bfin_ad1836_machine,
2887#endif
2888
2889#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
2890 &bfin_ad73311_machine,
2891#endif
2892
2893#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
2894 &bfin_ad73311_codec_device,
2895#endif
2896
2897#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
2898 &bfin_i2s,
2899#endif
2900
2901#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
2902 &bfin_ac97,
2903#endif
2904
2905#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
2906#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER)
2907 &ad5398_virt_consumer_device,
2908#endif
2909#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
2910 &ad5398_userspace_consumer_device,
2911#endif
2912#endif
2913
2914#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
2915 &adp_switch_device,
2916#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
2917 &adp122_userspace_consumer_device,
2918#endif
2919#endif
2920
2921#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER)
2922 &iio_gpio_trigger,
2923#endif
2924
2925#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373)
2926 &bf5xx_adau1373_device,
2927#endif
2928
2929#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701)
2930 &bf5xx_adau1701_device,
2931#endif
2932
2933#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X)
2934 &bfin_eval_adav801_device,
2935#endif
2936};
2937
2938static int __init net2272_init(void)
2939{
2940#if IS_ENABLED(CONFIG_USB_NET2272)
2941 int ret;
2942
2943 ret = gpio_request(GPIO_PF6, "net2272");
2944 if (ret)
2945 return ret;
2946
2947
2948 gpio_direction_output(GPIO_PF6, 0);
2949 mdelay(2);
2950 gpio_set_value(GPIO_PF6, 1);
2951#endif
2952
2953 return 0;
2954}
2955
2956static int __init stamp_init(void)
2957{
2958 printk(KERN_INFO "%s(): registering device resources\n", __func__);
2959 bfin_plat_nand_init();
2960 adf702x_mac_init();
2961 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
2962 i2c_register_board_info(0, bfin_i2c_board_info,
2963 ARRAY_SIZE(bfin_i2c_board_info));
2964 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
2965
2966 if (net2272_init())
2967 pr_warning("unable to configure net2272; it probably won't work\n");
2968
2969 return 0;
2970}
2971
2972arch_initcall(stamp_init);
2973
2974
2975static struct platform_device *stamp_early_devices[] __initdata = {
2976#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
2977#ifdef CONFIG_SERIAL_BFIN_UART0
2978 &bfin_uart0_device,
2979#endif
2980#ifdef CONFIG_SERIAL_BFIN_UART1
2981 &bfin_uart1_device,
2982#endif
2983#endif
2984
2985#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
2986#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2987 &bfin_sport0_uart_device,
2988#endif
2989#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2990 &bfin_sport1_uart_device,
2991#endif
2992#endif
2993};
2994
2995void __init native_machine_early_platform_add_devices(void)
2996{
2997 printk(KERN_INFO "register early platform devices\n");
2998 early_platform_add_devices(stamp_early_devices,
2999 ARRAY_SIZE(stamp_early_devices));
3000}
3001
3002void native_machine_restart(char *cmd)
3003{
3004
3005 if ((bfin_read_SYSCR() & 0x7) == 0x3)
3006 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
3007}
3008
3009
3010
3011
3012#define FLASH_MAC 0x203f0000
3013int bfin_get_ether_addr(char *addr)
3014{
3015 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
3016 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
3017 return 0;
3018}
3019EXPORT_SYMBOL(bfin_get_ether_addr);
3020
