LXR linux/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio

   1#ifndef __gio_defs_h
   2#define __gio_defs_h
   3
   4/*
   5 * This file is autogenerated from
   6 *   file:           ../../inst/gio/rtl/gio_regs.r
   7 *     id:           gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp 
   8 *     last modfied: Mon Apr 11 16:07:47 2005
   9 * 
  10 *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
  11 *      id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
  12 * Any changes here will be lost.
  13 *
  14 * -*- buffer-read-only: t -*-
  15 */
  16/* Main access macros */
  17#ifndef REG_RD
  18#define REG_RD( scope, inst, reg ) \
  19  REG_READ( reg_##scope##_##reg, \
  20            (inst) + REG_RD_ADDR_##scope##_##reg )
  21#endif
  22
  23#ifndef REG_WR
  24#define REG_WR( scope, inst, reg, val ) \
  25  REG_WRITE( reg_##scope##_##reg, \
  26             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  27#endif
  28
  29#ifndef REG_RD_VECT
  30#define REG_RD_VECT( scope, inst, reg, index ) \
  31  REG_READ( reg_##scope##_##reg, \
  32            (inst) + REG_RD_ADDR_##scope##_##reg + \
  33            (index) * STRIDE_##scope##_##reg )
  34#endif
  35
  36#ifndef REG_WR_VECT
  37#define REG_WR_VECT( scope, inst, reg, index, val ) \
  38  REG_WRITE( reg_##scope##_##reg, \
  39             (inst) + REG_WR_ADDR_##scope##_##reg + \
  40             (index) * STRIDE_##scope##_##reg, (val) )
  41#endif
  42
  43#ifndef REG_RD_INT
  44#define REG_RD_INT( scope, inst, reg ) \
  45  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  46#endif
  47
  48#ifndef REG_WR_INT
  49#define REG_WR_INT( scope, inst, reg, val ) \
  50  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  51#endif
  52
  53#ifndef REG_RD_INT_VECT
  54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  55  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  56            (index) * STRIDE_##scope##_##reg )
  57#endif
  58
  59#ifndef REG_WR_INT_VECT
  60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  61  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  62             (index) * STRIDE_##scope##_##reg, (val) )
  63#endif
  64
  65#ifndef REG_TYPE_CONV
  66#define REG_TYPE_CONV( type, orgtype, val ) \
  67  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  68#endif
  69
  70#ifndef reg_page_size
  71#define reg_page_size 8192
  72#endif
  73
  74#ifndef REG_ADDR
  75#define REG_ADDR( scope, inst, reg ) \
  76  ( (inst) + REG_RD_ADDR_##scope##_##reg )
  77#endif
  78
  79#ifndef REG_ADDR_VECT
  80#define REG_ADDR_VECT( scope, inst, reg, index ) \
  81  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  82    (index) * STRIDE_##scope##_##reg )
  83#endif
  84
  85/* C-code for register scope gio */
  86
  87/* Register rw_pa_dout, scope gio, type rw */
  88typedef struct {
  89  unsigned int data : 8;
  90  unsigned int dummy1 : 24;
  91} reg_gio_rw_pa_dout;
  92#define REG_RD_ADDR_gio_rw_pa_dout 0
  93#define REG_WR_ADDR_gio_rw_pa_dout 0
  94
  95/* Register r_pa_din, scope gio, type r */
  96typedef struct {
  97  unsigned int data : 8;
  98  unsigned int dummy1 : 24;
  99} reg_gio_r_pa_din;
 100#define REG_RD_ADDR_gio_r_pa_din 4
 101
 102/* Register rw_pa_oe, scope gio, type rw */
 103typedef struct {
 104  unsigned int oe : 8;
 105  unsigned int dummy1 : 24;
 106} reg_gio_rw_pa_oe;
 107#define REG_RD_ADDR_gio_rw_pa_oe 8
 108#define REG_WR_ADDR_gio_rw_pa_oe 8
 109
 110/* Register rw_intr_cfg, scope gio, type rw */
 111typedef struct {
 112  unsigned int pa0 : 3;
 113  unsigned int pa1 : 3;
 114  unsigned int pa2 : 3;
 115  unsigned int pa3 : 3;
 116  unsigned int pa4 : 3;
 117  unsigned int pa5 : 3;
 118  unsigned int pa6 : 3;
 119  unsigned int pa7 : 3;
 120  unsigned int dummy1 : 8;
 121} reg_gio_rw_intr_cfg;
 122#define REG_RD_ADDR_gio_rw_intr_cfg 12
 123#define REG_WR_ADDR_gio_rw_intr_cfg 12
 124
 125/* Register rw_intr_mask, scope gio, type rw */
 126typedef struct {
 127  unsigned int pa0 : 1;
 128  unsigned int pa1 : 1;
 129  unsigned int pa2 : 1;
 130  unsigned int pa3 : 1;
 131  unsigned int pa4 : 1;
 132  unsigned int pa5 : 1;
 133  unsigned int pa6 : 1;
 134  unsigned int pa7 : 1;
 135  unsigned int dummy1 : 24;
 136} reg_gio_rw_intr_mask;
 137#define REG_RD_ADDR_gio_rw_intr_mask 16
 138#define REG_WR_ADDR_gio_rw_intr_mask 16
 139
 140/* Register rw_ack_intr, scope gio, type rw */
 141typedef struct {
 142  unsigned int pa0 : 1;
 143  unsigned int pa1 : 1;
 144  unsigned int pa2 : 1;
 145  unsigned int pa3 : 1;
 146  unsigned int pa4 : 1;
 147  unsigned int pa5 : 1;
 148  unsigned int pa6 : 1;
 149  unsigned int pa7 : 1;
 150  unsigned int dummy1 : 24;
 151} reg_gio_rw_ack_intr;
 152#define REG_RD_ADDR_gio_rw_ack_intr 20
 153#define REG_WR_ADDR_gio_rw_ack_intr 20
 154
 155/* Register r_intr, scope gio, type r */
 156typedef struct {
 157  unsigned int pa0 : 1;
 158  unsigned int pa1 : 1;
 159  unsigned int pa2 : 1;
 160  unsigned int pa3 : 1;
 161  unsigned int pa4 : 1;
 162  unsigned int pa5 : 1;
 163  unsigned int pa6 : 1;
 164  unsigned int pa7 : 1;
 165  unsigned int dummy1 : 24;
 166} reg_gio_r_intr;
 167#define REG_RD_ADDR_gio_r_intr 24
 168
 169/* Register r_masked_intr, scope gio, type r */
 170typedef struct {
 171  unsigned int pa0 : 1;
 172  unsigned int pa1 : 1;
 173  unsigned int pa2 : 1;
 174  unsigned int pa3 : 1;
 175  unsigned int pa4 : 1;
 176  unsigned int pa5 : 1;
 177  unsigned int pa6 : 1;
 178  unsigned int pa7 : 1;
 179  unsigned int dummy1 : 24;
 180} reg_gio_r_masked_intr;
 181#define REG_RD_ADDR_gio_r_masked_intr 28
 182
 183/* Register rw_pb_dout, scope gio, type rw */
 184typedef struct {
 185  unsigned int data : 18;
 186  unsigned int dummy1 : 14;
 187} reg_gio_rw_pb_dout;
 188#define REG_RD_ADDR_gio_rw_pb_dout 32
 189#define REG_WR_ADDR_gio_rw_pb_dout 32
 190
 191/* Register r_pb_din, scope gio, type r */
 192typedef struct {
 193  unsigned int data : 18;
 194  unsigned int dummy1 : 14;
 195} reg_gio_r_pb_din;
 196#define REG_RD_ADDR_gio_r_pb_din 36
 197
 198/* Register rw_pb_oe, scope gio, type rw */
 199typedef struct {
 200  unsigned int oe : 18;
 201  unsigned int dummy1 : 14;
 202} reg_gio_rw_pb_oe;
 203#define REG_RD_ADDR_gio_rw_pb_oe 40
 204#define REG_WR_ADDR_gio_rw_pb_oe 40
 205
 206/* Register rw_pc_dout, scope gio, type rw */
 207typedef struct {
 208  unsigned int data : 18;
 209  unsigned int dummy1 : 14;
 210} reg_gio_rw_pc_dout;
 211#define REG_RD_ADDR_gio_rw_pc_dout 48
 212#define REG_WR_ADDR_gio_rw_pc_dout 48
 213
 214/* Register r_pc_din, scope gio, type r */
 215typedef struct {
 216  unsigned int data : 18;
 217  unsigned int dummy1 : 14;
 218} reg_gio_r_pc_din;
 219#define REG_RD_ADDR_gio_r_pc_din 52
 220
 221/* Register rw_pc_oe, scope gio, type rw */
 222typedef struct {
 223  unsigned int oe : 18;
 224  unsigned int dummy1 : 14;
 225} reg_gio_rw_pc_oe;
 226#define REG_RD_ADDR_gio_rw_pc_oe 56
 227#define REG_WR_ADDR_gio_rw_pc_oe 56
 228
 229/* Register rw_pd_dout, scope gio, type rw */
 230typedef struct {
 231  unsigned int data : 18;
 232  unsigned int dummy1 : 14;
 233} reg_gio_rw_pd_dout;
 234#define REG_RD_ADDR_gio_rw_pd_dout 64
 235#define REG_WR_ADDR_gio_rw_pd_dout 64
 236
 237/* Register r_pd_din, scope gio, type r */
 238typedef struct {
 239  unsigned int data : 18;
 240  unsigned int dummy1 : 14;
 241} reg_gio_r_pd_din;
 242#define REG_RD_ADDR_gio_r_pd_din 68
 243
 244/* Register rw_pd_oe, scope gio, type rw */
 245typedef struct {
 246  unsigned int oe : 18;
 247  unsigned int dummy1 : 14;
 248} reg_gio_rw_pd_oe;
 249#define REG_RD_ADDR_gio_rw_pd_oe 72
 250#define REG_WR_ADDR_gio_rw_pd_oe 72
 251
 252/* Register rw_pe_dout, scope gio, type rw */
 253typedef struct {
 254  unsigned int data : 18;
 255  unsigned int dummy1 : 14;
 256} reg_gio_rw_pe_dout;
 257#define REG_RD_ADDR_gio_rw_pe_dout 80
 258#define REG_WR_ADDR_gio_rw_pe_dout 80
 259
 260/* Register r_pe_din, scope gio, type r */
 261typedef struct {
 262  unsigned int data : 18;
 263  unsigned int dummy1 : 14;
 264} reg_gio_r_pe_din;
 265#define REG_RD_ADDR_gio_r_pe_din 84
 266
 267/* Register rw_pe_oe, scope gio, type rw */
 268typedef struct {
 269  unsigned int oe : 18;
 270  unsigned int dummy1 : 14;
 271} reg_gio_rw_pe_oe;
 272#define REG_RD_ADDR_gio_rw_pe_oe 88
 273#define REG_WR_ADDR_gio_rw_pe_oe 88
 274
 275
 276/* Constants */
 277enum {
 278  regk_gio_anyedge                         = 0x00000007,
 279  regk_gio_hi                              = 0x00000001,
 280  regk_gio_lo                              = 0x00000002,
 281  regk_gio_negedge                         = 0x00000006,
 282  regk_gio_no                              = 0x00000000,
 283  regk_gio_off                             = 0x00000000,
 284  regk_gio_posedge                         = 0x00000005,
 285  regk_gio_rw_intr_cfg_default             = 0x00000000,
 286  regk_gio_rw_intr_mask_default            = 0x00000000,
 287  regk_gio_rw_pa_oe_default                = 0x00000000,
 288  regk_gio_rw_pb_oe_default                = 0x00000000,
 289  regk_gio_rw_pc_oe_default                = 0x00000000,
 290  regk_gio_rw_pd_oe_default                = 0x00000000,
 291  regk_gio_rw_pe_oe_default                = 0x00000000,
 292  regk_gio_set                             = 0x00000003,
 293  regk_gio_yes                             = 0x00000001
 294};
 295#endif /* __gio_defs_h */
 296