LXR linux/arch/powerpc/include/asm/cputable.h

   1#ifndef __ASM_POWERPC_CPUTABLE_H
   2#define __ASM_POWERPC_CPUTABLE_H
   3
   4
   5#include <asm/asm-compat.h>
   6#include <asm/feature-fixups.h>
   7#include <uapi/asm/cputable.h>
   8
   9#ifndef __ASSEMBLY__
  10
  11/* This structure can grow, it's real size is used by head.S code
  12 * via the mkdefs mechanism.
  13 */
  14struct cpu_spec;
  15
  16typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
  17typedef void (*cpu_restore_t)(void);
  18
  19enum powerpc_oprofile_type {
  20        PPC_OPROFILE_INVALID = 0,
  21        PPC_OPROFILE_RS64 = 1,
  22        PPC_OPROFILE_POWER4 = 2,
  23        PPC_OPROFILE_G4 = 3,
  24        PPC_OPROFILE_FSL_EMB = 4,
  25        PPC_OPROFILE_CELL = 5,
  26        PPC_OPROFILE_PA6T = 6,
  27};
  28
  29enum powerpc_pmc_type {
  30        PPC_PMC_DEFAULT = 0,
  31        PPC_PMC_IBM = 1,
  32        PPC_PMC_PA6T = 2,
  33        PPC_PMC_G4 = 3,
  34};
  35
  36struct pt_regs;
  37
  38extern int machine_check_generic(struct pt_regs *regs);
  39extern int machine_check_4xx(struct pt_regs *regs);
  40extern int machine_check_440A(struct pt_regs *regs);
  41extern int machine_check_e500mc(struct pt_regs *regs);
  42extern int machine_check_e500(struct pt_regs *regs);
  43extern int machine_check_e200(struct pt_regs *regs);
  44extern int machine_check_47x(struct pt_regs *regs);
  45
  46/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
  47struct cpu_spec {
  48        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
  49        unsigned int    pvr_mask;
  50        unsigned int    pvr_value;
  51
  52        char            *cpu_name;
  53        unsigned long   cpu_features;           /* Kernel features */
  54        unsigned int    cpu_user_features;      /* Userland features */
  55        unsigned int    cpu_user_features2;     /* Userland features v2 */
  56        unsigned int    mmu_features;           /* MMU features */
  57
  58        /* cache line sizes */
  59        unsigned int    icache_bsize;
  60        unsigned int    dcache_bsize;
  61
  62        /* number of performance monitor counters */
  63        unsigned int    num_pmcs;
  64        enum powerpc_pmc_type pmc_type;
  65
  66        /* this is called to initialize various CPU bits like L1 cache,
  67         * BHT, SPD, etc... from head.S before branching to identify_machine
  68         */
  69        cpu_setup_t     cpu_setup;
  70        /* Used to restore cpu setup on secondary processors and at resume */
  71        cpu_restore_t   cpu_restore;
  72
  73        /* Used by oprofile userspace to select the right counters */
  74        char            *oprofile_cpu_type;
  75
  76        /* Processor specific oprofile operations */
  77        enum powerpc_oprofile_type oprofile_type;
  78
  79        /* Bit locations inside the mmcra change */
  80        unsigned long   oprofile_mmcra_sihv;
  81        unsigned long   oprofile_mmcra_sipr;
  82
  83        /* Bits to clear during an oprofile exception */
  84        unsigned long   oprofile_mmcra_clear;
  85
  86        /* Name of processor class, for the ELF AT_PLATFORM entry */
  87        char            *platform;
  88
  89        /* Processor specific machine check handling. Return negative
  90         * if the error is fatal, 1 if it was fully recovered and 0 to
  91         * pass up (not CPU originated) */
  92        int             (*machine_check)(struct pt_regs *regs);
  93
  94        /*
  95         * Processor specific early machine check handler which is
  96         * called in real mode to handle SLB and TLB errors.
  97         */
  98        long            (*machine_check_early)(struct pt_regs *regs);
  99
 100        /*
 101         * Processor specific routine to flush tlbs.
 102         */
 103        void            (*flush_tlb)(unsigned int action);
 104
 105};
 106
 107extern struct cpu_spec          *cur_cpu_spec;
 108
 109extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
 110
 111extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
 112extern void do_feature_fixups(unsigned long value, void *fixup_start,
 113                              void *fixup_end);
 114
 115extern const char *powerpc_base_platform;
 116
 117/* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
 118enum {
 119        TLB_INVAL_SCOPE_GLOBAL = 0,     /* invalidate all TLBs */
 120        TLB_INVAL_SCOPE_LPID = 1,       /* invalidate TLBs for current LPID */
 121};
 122
 123#endif /* __ASSEMBLY__ */
 124
 125/* CPU kernel features */
 126
 127/* Retain the 32b definitions all use bottom half of word */
 128#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x00000001)
 129#define CPU_FTR_L2CR                    ASM_CONST(0x00000002)
 130#define CPU_FTR_SPEC7450                ASM_CONST(0x00000004)
 131#define CPU_FTR_ALTIVEC                 ASM_CONST(0x00000008)
 132#define CPU_FTR_TAU                     ASM_CONST(0x00000010)
 133#define CPU_FTR_CAN_DOZE                ASM_CONST(0x00000020)
 134#define CPU_FTR_USE_TB                  ASM_CONST(0x00000040)
 135#define CPU_FTR_L2CSR                   ASM_CONST(0x00000080)
 136#define CPU_FTR_601                     ASM_CONST(0x00000100)
 137#define CPU_FTR_DBELL                   ASM_CONST(0x00000200)
 138#define CPU_FTR_CAN_NAP                 ASM_CONST(0x00000400)
 139#define CPU_FTR_L3CR                    ASM_CONST(0x00000800)
 140#define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x00001000)
 141#define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x00002000)
 142#define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x00004000)
 143#define CPU_FTR_NO_DPM                  ASM_CONST(0x00008000)
 144#define CPU_FTR_476_DD2                 ASM_CONST(0x00010000)
 145#define CPU_FTR_NEED_COHERENT           ASM_CONST(0x00020000)
 146#define CPU_FTR_NO_BTIC                 ASM_CONST(0x00040000)
 147#define CPU_FTR_DEBUG_LVL_EXC           ASM_CONST(0x00080000)
 148#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x00100000)
 149#define CPU_FTR_PPC_LE                  ASM_CONST(0x00200000)
 150#define CPU_FTR_REAL_LE                 ASM_CONST(0x00400000)
 151#define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x00800000)
 152#define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x01000000)
 153#define CPU_FTR_SPE                     ASM_CONST(0x02000000)
 154#define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x04000000)
 155#define CPU_FTR_LWSYNC                  ASM_CONST(0x08000000)
 156#define CPU_FTR_NOEXECUTE               ASM_CONST(0x10000000)
 157#define CPU_FTR_INDEXED_DCR             ASM_CONST(0x20000000)
 158#define CPU_FTR_EMB_HV                  ASM_CONST(0x40000000)
 159
 160/*
 161 * Add the 64-bit processor unique features in the top half of the word;
 162 * on 32-bit, make the names available but defined to be 0.
 163 */
 164#ifdef __powerpc64__
 165#define LONG_ASM_CONST(x)               ASM_CONST(x)
 166#else
 167#define LONG_ASM_CONST(x)               0
 168#endif
 169
 170#define CPU_FTR_HVMODE                  LONG_ASM_CONST(0x0000000100000000)
 171#define CPU_FTR_ARCH_201                LONG_ASM_CONST(0x0000000200000000)
 172#define CPU_FTR_ARCH_206                LONG_ASM_CONST(0x0000000400000000)
 173#define CPU_FTR_ARCH_207S               LONG_ASM_CONST(0x0000000800000000)
 174/* Free                                 LONG_ASM_CONST(0x0000001000000000) */
 175#define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000002000000000)
 176#define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000004000000000)
 177#define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000008000000000)
 178#define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000010000000000)
 179#define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000020000000000)
 180#define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000040000000000)
 181#define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0000080000000000)
 182#define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0000100000000000)
 183#define CPU_FTR_VSX                     LONG_ASM_CONST(0x0000200000000000)
 184#define CPU_FTR_SAO                     LONG_ASM_CONST(0x0000400000000000)
 185#define CPU_FTR_CP_USE_DCBTZ            LONG_ASM_CONST(0x0000800000000000)
 186#define CPU_FTR_UNALIGNED_LD_STD        LONG_ASM_CONST(0x0001000000000000)
 187#define CPU_FTR_ASYM_SMT                LONG_ASM_CONST(0x0002000000000000)
 188#define CPU_FTR_STCX_CHECKS_ADDRESS     LONG_ASM_CONST(0x0004000000000000)
 189#define CPU_FTR_POPCNTB                 LONG_ASM_CONST(0x0008000000000000)
 190#define CPU_FTR_POPCNTD                 LONG_ASM_CONST(0x0010000000000000)
 191#define CPU_FTR_ICSWX                   LONG_ASM_CONST(0x0020000000000000)
 192#define CPU_FTR_VMX_COPY                LONG_ASM_CONST(0x0040000000000000)
 193#define CPU_FTR_TM                      LONG_ASM_CONST(0x0080000000000000)
 194#define CPU_FTR_CFAR                    LONG_ASM_CONST(0x0100000000000000)
 195#define CPU_FTR_HAS_PPR                 LONG_ASM_CONST(0x0200000000000000)
 196#define CPU_FTR_DAWR                    LONG_ASM_CONST(0x0400000000000000)
 197#define CPU_FTR_DABRX                   LONG_ASM_CONST(0x0800000000000000)
 198#define CPU_FTR_PMAO_BUG                LONG_ASM_CONST(0x1000000000000000)
 199
 200#ifndef __ASSEMBLY__
 201
 202#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
 203
 204#define MMU_FTR_PPCAS_ARCH_V2   (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
 205
 206/* We only set the altivec features if the kernel was compiled with altivec
 207 * support
 208 */
 209#ifdef CONFIG_ALTIVEC
 210#define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
 211#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
 212#else
 213#define CPU_FTR_ALTIVEC_COMP    0
 214#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
 215#endif
 216
 217/* We only set the VSX features if the kernel was compiled with VSX
 218 * support
 219 */
 220#ifdef CONFIG_VSX
 221#define CPU_FTR_VSX_COMP        CPU_FTR_VSX
 222#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
 223#else
 224#define CPU_FTR_VSX_COMP        0
 225#define PPC_FEATURE_HAS_VSX_COMP    0
 226#endif
 227
 228/* We only set the spe features if the kernel was compiled with spe
 229 * support
 230 */
 231#ifdef CONFIG_SPE
 232#define CPU_FTR_SPE_COMP        CPU_FTR_SPE
 233#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
 234#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
 235#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
 236#else
 237#define CPU_FTR_SPE_COMP        0
 238#define PPC_FEATURE_HAS_SPE_COMP    0
 239#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
 240#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
 241#endif
 242
 243/* We only set the TM feature if the kernel was compiled with TM supprt */
 244#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 245#define CPU_FTR_TM_COMP                 CPU_FTR_TM
 246#define PPC_FEATURE2_HTM_COMP           PPC_FEATURE2_HTM
 247#define PPC_FEATURE2_HTM_NOSC_COMP      PPC_FEATURE2_HTM_NOSC
 248#else
 249#define CPU_FTR_TM_COMP                 0
 250#define PPC_FEATURE2_HTM_COMP           0
 251#define PPC_FEATURE2_HTM_NOSC_COMP      0
 252#endif
 253
 254/* We need to mark all pages as being coherent if we're SMP or we have a
 255 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
 256 * require it for PCI "streaming/prefetch" to work properly.
 257 * This is also required by 52xx family.
 258 */
 259#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
 260        || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
 261        || defined(CONFIG_PPC_MPC52xx)
 262#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 263#else
 264#define CPU_FTR_COMMON                  0
 265#endif
 266
 267/* The powersave features NAP & DOZE seems to confuse BDI when
 268   debugging. So if a BDI is used, disable theses
 269 */
 270#ifndef CONFIG_BDI_SWITCH
 271#define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
 272#define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
 273#else
 274#define CPU_FTR_MAYBE_CAN_DOZE  0
 275#define CPU_FTR_MAYBE_CAN_NAP   0
 276#endif
 277
 278#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
 279        CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
 280#define CPU_FTRS_603    (CPU_FTR_COMMON | \
 281            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 282            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 283#define CPU_FTRS_604    (CPU_FTR_COMMON | \
 284            CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
 285#define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
 286            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 287            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 288#define CPU_FTRS_740    (CPU_FTR_COMMON | \
 289            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 290            CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
 291            CPU_FTR_PPC_LE)
 292#define CPU_FTRS_750    (CPU_FTR_COMMON | \
 293            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 294            CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
 295            CPU_FTR_PPC_LE)
 296#define CPU_FTRS_750CL  (CPU_FTRS_750)
 297#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
 298#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
 299#define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
 300#define CPU_FTRS_750GX  (CPU_FTRS_750FX)
 301#define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | \
 302            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 303            CPU_FTR_ALTIVEC_COMP | \
 304            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 305#define CPU_FTRS_7400   (CPU_FTR_COMMON | \
 306            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 307            CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
 308            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 309#define CPU_FTRS_7450_20        (CPU_FTR_COMMON | \
 310            CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 311            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 312            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 313#define CPU_FTRS_7450_21        (CPU_FTR_COMMON | \
 314            CPU_FTR_USE_TB | \
 315            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 316            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 317            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 318            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 319#define CPU_FTRS_7450_23        (CPU_FTR_COMMON | \
 320            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 321            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 322            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 323            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 324#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
 325            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 326            CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
 327            CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 328#define CPU_FTRS_7455_20        (CPU_FTR_COMMON | \
 329            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 330            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 331            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 332            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 333            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 334#define CPU_FTRS_7455   (CPU_FTR_COMMON | \
 335            CPU_FTR_USE_TB | \
 336            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 337            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 338            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 339#define CPU_FTRS_7447_10        (CPU_FTR_COMMON | \
 340            CPU_FTR_USE_TB | \
 341            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 342            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 343            CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
 344            CPU_FTR_NEED_PAIRED_STWCX)
 345#define CPU_FTRS_7447   (CPU_FTR_COMMON | \
 346            CPU_FTR_USE_TB | \
 347            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 348            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 349            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 350#define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
 351            CPU_FTR_USE_TB | \
 352            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 353            CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 354            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 355#define CPU_FTRS_7448   (CPU_FTR_COMMON | \
 356            CPU_FTR_USE_TB | \
 357            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 358            CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 359            CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 360#define CPU_FTRS_82XX   (CPU_FTR_COMMON | \
 361            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
 362#define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
 363            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
 364#define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
 365            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
 366            CPU_FTR_COMMON)
 367#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
 368            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
 369            CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
 370#define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | CPU_FTR_USE_TB)
 371#define CPU_FTRS_8XX    (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
 372#define CPU_FTRS_40X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 373#define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 374#define CPU_FTRS_440x6  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
 375            CPU_FTR_INDEXED_DCR)
 376#define CPU_FTRS_47X    (CPU_FTRS_440x6)
 377#define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
 378            CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
 379            CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
 380            CPU_FTR_DEBUG_LVL_EXC)
 381#define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 382            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
 383            CPU_FTR_NOEXECUTE)
 384#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 385            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
 386            CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 387#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 388            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 389            CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
 390/*
 391 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
 392 * same workaround as CPU_FTR_CELL_TB_BUG.
 393 */
 394#define CPU_FTRS_E5500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 395            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 396            CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 397            CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
 398#define CPU_FTRS_E6500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 399            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 400            CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 401            CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
 402            CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
 403#define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 404
 405/* 64-bit CPUs */
 406#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 407            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 408            CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
 409            CPU_FTR_STCX_CHECKS_ADDRESS)
 410#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 411            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
 412            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
 413            CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
 414            CPU_FTR_HVMODE | CPU_FTR_DABRX)
 415#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 416            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 417            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 418            CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
 419            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
 420#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 421            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 422            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 423            CPU_FTR_COHERENT_ICACHE | \
 424            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 425            CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
 426            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
 427            CPU_FTR_DABRX)
 428#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 429            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
 430            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 431            CPU_FTR_COHERENT_ICACHE | \
 432            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 433            CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
 434            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 435            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
 436            CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
 437#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 438            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
 439            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 440            CPU_FTR_COHERENT_ICACHE | \
 441            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 442            CPU_FTR_DSCR | CPU_FTR_SAO  | \
 443            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 444            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
 445            CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
 446            CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
 447#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
 448#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
 449#define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 450            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 451            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
 452            CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
 453            CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
 454#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 455            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
 456            CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
 457#define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 458
 459#ifdef __powerpc64__
 460#ifdef CONFIG_PPC_BOOK3E
 461#define CPU_FTRS_POSSIBLE       (CPU_FTRS_E6500 | CPU_FTRS_E5500)
 462#else
 463#define CPU_FTRS_POSSIBLE       \
 464            (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
 465             CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
 466             CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
 467             CPU_FTRS_PA6T | CPU_FTR_VSX)
 468#endif
 469#else
 470enum {
 471        CPU_FTRS_POSSIBLE =
 472#ifdef CONFIG_PPC_BOOK3S_32
 473            CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
 474            CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
 475            CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
 476            CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
 477            CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
 478            CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
 479            CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
 480            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
 481            CPU_FTRS_CLASSIC32 |
 482#else
 483            CPU_FTRS_GENERIC_32 |
 484#endif
 485#ifdef CONFIG_8xx
 486            CPU_FTRS_8XX |
 487#endif
 488#ifdef CONFIG_40x
 489            CPU_FTRS_40X |
 490#endif
 491#ifdef CONFIG_44x
 492            CPU_FTRS_44X | CPU_FTRS_440x6 |
 493#endif
 494#ifdef CONFIG_PPC_47x
 495            CPU_FTRS_47X | CPU_FTR_476_DD2 |
 496#endif
 497#ifdef CONFIG_E200
 498            CPU_FTRS_E200 |
 499#endif
 500#ifdef CONFIG_E500
 501            CPU_FTRS_E500 | CPU_FTRS_E500_2 |
 502#endif
 503#ifdef CONFIG_PPC_E500MC
 504            CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
 505#endif
 506            0,
 507};
 508#endif /* __powerpc64__ */
 509
 510#ifdef __powerpc64__
 511#ifdef CONFIG_PPC_BOOK3E
 512#define CPU_FTRS_ALWAYS         (CPU_FTRS_E6500 & CPU_FTRS_E5500)
 513#else
 514#define CPU_FTRS_ALWAYS         \
 515            (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
 516             CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
 517             CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
 518             CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE)
 519#endif
 520#else
 521enum {
 522        CPU_FTRS_ALWAYS =
 523#ifdef CONFIG_PPC_BOOK3S_32
 524            CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
 525            CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
 526            CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
 527            CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
 528            CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
 529            CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
 530            CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
 531            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
 532            CPU_FTRS_CLASSIC32 &
 533#else
 534            CPU_FTRS_GENERIC_32 &
 535#endif
 536#ifdef CONFIG_8xx
 537            CPU_FTRS_8XX &
 538#endif
 539#ifdef CONFIG_40x
 540            CPU_FTRS_40X &
 541#endif
 542#ifdef CONFIG_44x
 543            CPU_FTRS_44X & CPU_FTRS_440x6 &
 544#endif
 545#ifdef CONFIG_E200
 546            CPU_FTRS_E200 &
 547#endif
 548#ifdef CONFIG_E500
 549            CPU_FTRS_E500 & CPU_FTRS_E500_2 &
 550#endif
 551#ifdef CONFIG_PPC_E500MC
 552            CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
 553#endif
 554            ~CPU_FTR_EMB_HV &   /* can be removed at runtime */
 555            CPU_FTRS_POSSIBLE,
 556};
 557#endif /* __powerpc64__ */
 558
 559static inline int cpu_has_feature(unsigned long feature)
 560{
 561        return (CPU_FTRS_ALWAYS & feature) ||
 562               (CPU_FTRS_POSSIBLE
 563                & cur_cpu_spec->cpu_features
 564                & feature);
 565}
 566
 567#define HBP_NUM 1
 568
 569#endif /* !__ASSEMBLY__ */
 570
 571#endif /* __ASM_POWERPC_CPUTABLE_H */
 572