1#ifndef __PCI_SH4_H
2#define __PCI_SH4_H
3
4#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
5 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7763)
7#include "pci-sh7780.h"
8#else
9#include "pci-sh7751.h"
10#endif
11
12#include <asm/io.h>
13
14#define SH4_PCICR 0x100
15 #define SH4_PCICR_PREFIX 0xA5000000
16 #define SH4_PCICR_FTO 0x00000400
17 #define SH4_PCICR_TRSB 0x00000200
18 #define SH4_PCICR_BSWP 0x00000100
19 #define SH4_PCICR_PLUP 0x00000080
20 #define SH4_PCICR_ARBM 0x00000040
21 #define SH4_PCICR_MD 0x00000030
22 #define SH4_PCICR_SERR 0x00000008
23 #define SH4_PCICR_INTA 0x00000004
24 #define SH4_PCICR_PRST 0x00000002
25 #define SH4_PCICR_CFIN 0x00000001
26#define SH4_PCILSR0 0x104
27#define SH4_PCILSR1 0x108
28#define SH4_PCILAR0 0x10C
29#define SH4_PCILAR1 0x110
30#define SH4_PCIINT 0x114
31 #define SH4_PCIINT_MLCK 0x00008000
32 #define SH4_PCIINT_TABT 0x00004000
33 #define SH4_PCIINT_TRET 0x00000200
34 #define SH4_PCIINT_MFDE 0x00000100
35 #define SH4_PCIINT_PRTY 0x00000080
36 #define SH4_PCIINT_SERR 0x00000040
37 #define SH4_PCIINT_TWDP 0x00000020
38 #define SH4_PCIINT_TRDP 0x00000010
39 #define SH4_PCIINT_MTABT 0x00000008
40 #define SH4_PCIINT_MMABT 0x00000004
41 #define SH4_PCIINT_MWPD 0x00000002
42 #define SH4_PCIINT_MRPD 0x00000001
43#define SH4_PCIINTM 0x118
44 #define SH4_PCIINTM_TTADIM BIT(14)
45 #define SH4_PCIINTM_TMTOIM BIT(9)
46 #define SH4_PCIINTM_MDEIM BIT(8)
47 #define SH4_PCIINTM_APEDIM BIT(7)
48 #define SH4_PCIINTM_SDIM BIT(6)
49 #define SH4_PCIINTM_DPEITWM BIT(5)
50 #define SH4_PCIINTM_PEDITRM BIT(4)
51 #define SH4_PCIINTM_TADIMM BIT(3)
52 #define SH4_PCIINTM_MADIMM BIT(2)
53 #define SH4_PCIINTM_MWPDIM BIT(1)
54 #define SH4_PCIINTM_MRDPEIM BIT(0)
55#define SH4_PCIALR 0x11C
56#define SH4_PCICLR 0x120
57 #define SH4_PCICLR_MPIO 0x80000000
58 #define SH4_PCICLR_MDMA0 0x40000000
59 #define SH4_PCICLR_MDMA1 0x20000000
60 #define SH4_PCICLR_MDMA2 0x10000000
61 #define SH4_PCICLR_MDMA3 0x08000000
62 #define SH4_PCICLR_TGT 0x04000000
63 #define SH4_PCICLR_CMDL 0x0000000F
64#define SH4_PCIAINT 0x130
65 #define SH4_PCIAINT_MBKN 0x00002000
66 #define SH4_PCIAINT_TBTO 0x00001000
67 #define SH4_PCIAINT_MBTO 0x00000800
68 #define SH4_PCIAINT_TABT 0x00000008
69 #define SH4_PCIAINT_MABT 0x00000004
70 #define SH4_PCIAINT_RDPE 0x00000002
71 #define SH4_PCIAINT_WDPE 0x00000001
72#define SH4_PCIAINTM 0x134
73#define SH4_PCIBMLR 0x138
74 #define SH4_PCIBMLR_REQ4 0x00000010
75 #define SH4_PCIBMLR_REQ3 0x00000008
76 #define SH4_PCIBMLR_REQ2 0x00000004
77 #define SH4_PCIBMLR_REQ1 0x00000002
78 #define SH4_PCIBMLR_REQ0 0x00000001
79#define SH4_PCIDMABT 0x140
80 #define SH4_PCIDMABT_RRBN 0x00000001
81#define SH4_PCIDPA0 0x180
82#define SH4_PCIDLA0 0x184
83#define SH4_PCIDTC0 0x188
84#define SH4_PCIDCR0 0x18C
85 #define SH4_PCIDCR_ALGN 0x00000600
86 #define SH4_PCIDCR_MAST 0x00000100
87 #define SH4_PCIDCR_INTM 0x00000080
88 #define SH4_PCIDCR_INTS 0x00000040
89 #define SH4_PCIDCR_LHLD 0x00000020
90 #define SH4_PCIDCR_PHLD 0x00000010
91 #define SH4_PCIDCR_IOSEL 0x00000008
92 #define SH4_PCIDCR_DIR 0x00000004
93 #define SH4_PCIDCR_STOP 0x00000002
94 #define SH4_PCIDCR_STRT 0x00000001
95#define SH4_PCIDPA1 0x190
96#define SH4_PCIDLA1 0x194
97#define SH4_PCIDTC1 0x198
98#define SH4_PCIDCR1 0x19C
99#define SH4_PCIDPA2 0x1A0
100#define SH4_PCIDLA2 0x1A4
101#define SH4_PCIDTC2 0x1A8
102#define SH4_PCIDCR2 0x1AC
103#define SH4_PCIDPA3 0x1B0
104#define SH4_PCIDLA3 0x1B4
105#define SH4_PCIDTC3 0x1B8
106#define SH4_PCIDCR3 0x1BC
107#define SH4_PCIPAR 0x1C0
108 #define SH4_PCIPAR_CFGEN 0x80000000
109 #define SH4_PCIPAR_BUSNO 0x00FF0000
110 #define SH4_PCIPAR_DEVNO 0x0000FF00
111 #define SH4_PCIPAR_REGAD 0x000000FC
112#define SH4_PCIMBR 0x1C4
113 #define SH4_PCIMBR_MASK 0xFF000000
114 #define SH4_PCIMBR_LOCK 0x00000001
115#define SH4_PCIIOBR 0x1C8
116 #define SH4_PCIIOBR_MASK 0xFFFC0000
117 #define SH4_PCIIOBR_LOCK 0x00000001
118#define SH4_PCIPINT 0x1CC
119 #define SH4_PCIPINT_D3 0x00000002
120 #define SH4_PCIPINT_D0 0x00000001
121#define SH4_PCIPINTM 0x1D0
122#define SH4_PCICLKR 0x1D4
123 #define SH4_PCICLKR_PCSTP 0x00000002
124 #define SH4_PCICLKR_BCSTP 0x00000001
125
126#define SH4_PCIBCR1 0x1E0
127 #define SH4_PCIMBR0 SH4_PCIBCR1
128#define SH4_PCIBCR2 0x1E4
129 #define SH4_PCIMBMR0 SH4_PCIBCR2
130#define SH4_PCIWCR1 0x1E8
131#define SH4_PCIWCR2 0x1EC
132#define SH4_PCIWCR3 0x1F0
133 #define SH4_PCIMBR2 SH4_PCIWCR3
134#define SH4_PCIMCR 0x1F4
135#define SH4_PCIBCR3 0x1f8
136#define SH4_PCIPCTR 0x200
137 #define SH4_PCIPCTR_P2EN 0x000400000
138 #define SH4_PCIPCTR_P1EN 0x000200000
139 #define SH4_PCIPCTR_P0EN 0x000100000
140 #define SH4_PCIPCTR_P2UP 0x000000020
141 #define SH4_PCIPCTR_P2IO 0x000000010
142 #define SH4_PCIPCTR_P1UP 0x000000008
143 #define SH4_PCIPCTR_P1IO 0x000000004
144 #define SH4_PCIPCTR_P0UP 0x000000002
145 #define SH4_PCIPCTR_P0IO 0x000000001
146#define SH4_PCIPDTR 0x204
147 #define SH4_PCIPDTR_PB5 0x000000020
148 #define SH4_PCIPDTR_PB4 0x000000010
149 #define SH4_PCIPDTR_PB3 0x000000008
150 #define SH4_PCIPDTR_PB2 0x000000004
151 #define SH4_PCIPDTR_PB1 0x000000002
152 #define SH4_PCIPDTR_PB0 0x000000001
153#define SH4_PCIPDR 0x220
154
155
156extern struct pci_ops sh4_pci_ops;
157int pci_fixup_pcic(struct pci_channel *chan);
158
159struct sh4_pci_address_space {
160 unsigned long base;
161 unsigned long size;
162};
163
164struct sh4_pci_address_map {
165 struct sh4_pci_address_space window0;
166 struct sh4_pci_address_space window1;
167};
168
169static inline void pci_write_reg(struct pci_channel *chan,
170 unsigned long val, unsigned long reg)
171{
172 __raw_writel(val, chan->reg_base + reg);
173}
174
175static inline unsigned long pci_read_reg(struct pci_channel *chan,
176 unsigned long reg)
177{
178 return __raw_readl(chan->reg_base + reg);
179}
180
181#endif
182