1
2
3
4
5
6
7
8
9
10
11#ifndef _ASM_X86_UV_UV_HUB_H
12#define _ASM_X86_UV_UV_HUB_H
13
14#ifdef CONFIG_X86_64
15#include <linux/numa.h>
16#include <linux/percpu.h>
17#include <linux/timer.h>
18#include <linux/io.h>
19#include <asm/types.h>
20#include <asm/percpu.h>
21#include <asm/uv/uv_mmrs.h>
22#include <asm/irq_vectors.h>
23#include <asm/io_apic.h>
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117#define UV_MAX_NUMALINK_BLADES 16384
118
119
120
121
122
123#define UV_MAX_SSI_BLADES 256
124
125
126
127
128#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2)
129
130struct uv_scir_s {
131 struct timer_list timer;
132 unsigned long offset;
133 unsigned long last;
134 unsigned long idle_on;
135 unsigned long idle_off;
136 unsigned char state;
137 unsigned char enabled;
138};
139
140
141
142
143
144
145struct uv_hub_info_s {
146 unsigned long global_mmr_base;
147 unsigned long gpa_mask;
148 unsigned int gnode_extra;
149 unsigned char hub_revision;
150 unsigned char apic_pnode_shift;
151 unsigned char m_shift;
152 unsigned char n_lshift;
153 unsigned long gnode_upper;
154 unsigned long lowmem_remap_top;
155 unsigned long lowmem_remap_base;
156 unsigned short pnode;
157 unsigned short pnode_mask;
158 unsigned short coherency_domain_number;
159 unsigned short numa_blade_id;
160 unsigned char blade_processor_id;
161 unsigned char m_val;
162 unsigned char n_val;
163 struct uv_scir_s scir;
164};
165
166DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
167#define uv_hub_info this_cpu_ptr(&__uv_hub_info)
168#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
169
170
171
172
173
174
175
176#define UV1_HUB_REVISION_BASE 1
177#define UV2_HUB_REVISION_BASE 3
178#define UV3_HUB_REVISION_BASE 5
179
180static inline int is_uv1_hub(void)
181{
182 return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;
183}
184
185static inline int is_uv2_hub(void)
186{
187 return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) &&
188 (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE));
189}
190
191static inline int is_uv3_hub(void)
192{
193 return uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE;
194}
195
196static inline int is_uv_hub(void)
197{
198 return uv_hub_info->hub_revision;
199}
200
201
202static inline int is_uvx_hub(void)
203{
204 return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE;
205}
206
207union uvh_apicid {
208 unsigned long v;
209 struct uvh_apicid_s {
210 unsigned long local_apic_mask : 24;
211 unsigned long local_apic_shift : 5;
212 unsigned long unused1 : 3;
213 unsigned long pnode_mask : 24;
214 unsigned long pnode_shift : 5;
215 unsigned long unused2 : 3;
216 } s;
217};
218
219
220
221
222
223
224
225
226
227#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
228#define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra)
229#define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1)
230
231#define UV1_LOCAL_MMR_BASE 0xf4000000UL
232#define UV1_GLOBAL_MMR32_BASE 0xf8000000UL
233#define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
234#define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
235
236#define UV2_LOCAL_MMR_BASE 0xfa000000UL
237#define UV2_GLOBAL_MMR32_BASE 0xfc000000UL
238#define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
239#define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
240
241#define UV3_LOCAL_MMR_BASE 0xfa000000UL
242#define UV3_GLOBAL_MMR32_BASE 0xfc000000UL
243#define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
244#define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
245
246#define UV_LOCAL_MMR_BASE (is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \
247 (is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \
248 UV3_LOCAL_MMR_BASE))
249#define UV_GLOBAL_MMR32_BASE (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE :\
250 (is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE :\
251 UV3_GLOBAL_MMR32_BASE))
252#define UV_LOCAL_MMR_SIZE (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
253 (is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \
254 UV3_LOCAL_MMR_SIZE))
255#define UV_GLOBAL_MMR32_SIZE (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\
256 (is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE :\
257 UV3_GLOBAL_MMR32_SIZE))
258#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
259
260#define UV_GLOBAL_GRU_MMR_BASE 0x4000000
261
262#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
263#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
264
265#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
266
267#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
268 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
269
270#define UVH_APICID 0x002D0E00L
271#define UV_APIC_PNODE_SHIFT 6
272
273#define UV_APICID_HIBIT_MASK 0xffff0000
274
275
276#define LOCAL_BUS_BASE 0x1c00000
277#define LOCAL_BUS_SIZE (4 * 1024 * 1024)
278
279
280
281
282
283
284
285
286
287
288
289
290#define SCIR_WINDOW_COUNT 64
291#define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
292 LOCAL_BUS_SIZE - \
293 SCIR_WINDOW_COUNT)
294
295#define SCIR_CPU_HEARTBEAT 0x01
296#define SCIR_CPU_ACTIVITY 0x02
297#define SCIR_CPU_HB_INTERVAL (HZ)
298
299
300#define for_each_possible_blade(bid) \
301 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
302
303
304
305
306
307
308
309
310
311static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
312{
313 if (paddr < uv_hub_info->lowmem_remap_top)
314 paddr |= uv_hub_info->lowmem_remap_base;
315 paddr |= uv_hub_info->gnode_upper;
316 paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
317 ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift);
318 return paddr;
319}
320
321
322
323static inline unsigned long uv_gpa(void *v)
324{
325 return uv_soc_phys_ram_to_gpa(__pa(v));
326}
327
328
329static inline int
330uv_gpa_in_mmr_space(unsigned long gpa)
331{
332 return (gpa >> 62) == 0x3UL;
333}
334
335
336static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
337{
338 unsigned long paddr;
339 unsigned long remap_base = uv_hub_info->lowmem_remap_base;
340 unsigned long remap_top = uv_hub_info->lowmem_remap_top;
341
342 gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
343 ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
344 paddr = gpa & uv_hub_info->gpa_mask;
345 if (paddr >= remap_base && paddr < remap_base + remap_top)
346 paddr -= remap_base;
347 return paddr;
348}
349
350
351
352static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
353{
354 return gpa >> uv_hub_info->n_lshift;
355}
356
357
358static inline int uv_gpa_to_pnode(unsigned long gpa)
359{
360 unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1;
361
362 return uv_gpa_to_gnode(gpa) & n_mask;
363}
364
365
366static inline unsigned long uv_gpa_to_offset(unsigned long gpa)
367{
368 return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift;
369}
370
371
372static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
373{
374 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
375}
376
377
378
379
380
381static inline int uv_apicid_to_pnode(int apicid)
382{
383 return (apicid >> uv_hub_info->apic_pnode_shift);
384}
385
386
387
388
389static inline int uv_apicid_to_socket(int apicid)
390{
391 if (is_uv1_hub())
392 return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;
393 else
394 return 0;
395}
396
397
398
399
400
401static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset)
402{
403 return __va(UV_GLOBAL_MMR32_BASE |
404 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
405}
406
407static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val)
408{
409 writeq(val, uv_global_mmr32_address(pnode, offset));
410}
411
412static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset)
413{
414 return readq(uv_global_mmr32_address(pnode, offset));
415}
416
417
418
419
420
421static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset)
422{
423 return __va(UV_GLOBAL_MMR64_BASE |
424 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
425}
426
427static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val)
428{
429 writeq(val, uv_global_mmr64_address(pnode, offset));
430}
431
432static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset)
433{
434 return readq(uv_global_mmr64_address(pnode, offset));
435}
436
437
438
439
440
441static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset)
442{
443 return UV_GLOBAL_GRU_MMR_BASE | offset |
444 ((unsigned long)pnode << uv_hub_info->m_val);
445}
446
447static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
448{
449 writeb(val, uv_global_mmr64_address(pnode, offset));
450}
451
452static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset)
453{
454 return readb(uv_global_mmr64_address(pnode, offset));
455}
456
457
458
459
460
461static inline unsigned long *uv_local_mmr_address(unsigned long offset)
462{
463 return __va(UV_LOCAL_MMR_BASE | offset);
464}
465
466static inline unsigned long uv_read_local_mmr(unsigned long offset)
467{
468 return readq(uv_local_mmr_address(offset));
469}
470
471static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
472{
473 writeq(val, uv_local_mmr_address(offset));
474}
475
476static inline unsigned char uv_read_local_mmr8(unsigned long offset)
477{
478 return readb(uv_local_mmr_address(offset));
479}
480
481static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
482{
483 writeb(val, uv_local_mmr_address(offset));
484}
485
486
487
488
489
490struct uv_blade_info {
491 unsigned short nr_possible_cpus;
492 unsigned short nr_online_cpus;
493 unsigned short pnode;
494 short memory_nid;
495 spinlock_t nmi_lock;
496 unsigned long nmi_count;
497};
498extern struct uv_blade_info *uv_blade_info;
499extern short *uv_node_to_blade;
500extern short *uv_cpu_to_blade;
501extern short uv_possible_blades;
502
503
504static inline int uv_blade_processor_id(void)
505{
506 return uv_hub_info->blade_processor_id;
507}
508
509
510static inline int uv_numa_blade_id(void)
511{
512 return uv_hub_info->numa_blade_id;
513}
514
515
516static inline int uv_cpu_to_blade_id(int cpu)
517{
518 return uv_cpu_to_blade[cpu];
519}
520
521
522static inline int uv_node_to_blade_id(int nid)
523{
524 return uv_node_to_blade[nid];
525}
526
527
528static inline int uv_blade_to_pnode(int bid)
529{
530 return uv_blade_info[bid].pnode;
531}
532
533
534static inline int uv_blade_to_memory_nid(int bid)
535{
536 return uv_blade_info[bid].memory_nid;
537}
538
539
540static inline int uv_blade_nr_possible_cpus(int bid)
541{
542 return uv_blade_info[bid].nr_possible_cpus;
543}
544
545
546static inline int uv_blade_nr_online_cpus(int bid)
547{
548 return uv_blade_info[bid].nr_online_cpus;
549}
550
551
552static inline int uv_cpu_to_pnode(int cpu)
553{
554 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
555}
556
557
558static inline int uv_node_to_pnode(int nid)
559{
560 return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
561}
562
563
564static inline int uv_num_possible_blades(void)
565{
566 return uv_possible_blades;
567}
568
569
570extern void uv_nmi_setup(void);
571
572
573#define UVH_NMI_MMR UVH_SCRATCH5
574#define UVH_NMI_MMR_CLEAR UVH_SCRATCH5_ALIAS
575#define UVH_NMI_MMR_SHIFT 63
576#define UVH_NMI_MMR_TYPE "SCRATCH5"
577
578
579#define UVH_NMI_MMRX UVH_EVENT_OCCURRED0
580#define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS
581#define UVH_NMI_MMRX_SHIFT (is_uv1_hub() ? \
582 UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :\
583 UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT)
584#define UVH_NMI_MMRX_TYPE "EXTIO_INT0"
585
586
587#define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST
588
589
590#define UVH_NMI_MMRX_REQ UVH_SCRATCH5_ALIAS_2
591#define UVH_NMI_MMRX_REQ_SHIFT 62
592
593struct uv_hub_nmi_s {
594 raw_spinlock_t nmi_lock;
595 atomic_t in_nmi;
596 atomic_t cpu_owner;
597 atomic_t read_mmr_count;
598 atomic_t nmi_count;
599 unsigned long nmi_value;
600};
601
602struct uv_cpu_nmi_s {
603 struct uv_hub_nmi_s *hub;
604 int state;
605 int pinging;
606 int queries;
607 int pings;
608};
609
610DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
611
612#define uv_hub_nmi (uv_cpu_nmi.hub)
613#define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu))
614#define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub)
615
616
617#define UV_NMI_STATE_OUT 0
618#define UV_NMI_STATE_IN 1
619#define UV_NMI_STATE_DUMP 2
620#define UV_NMI_STATE_DUMP_DONE 3
621
622
623static inline void uv_set_scir_bits(unsigned char value)
624{
625 if (uv_hub_info->scir.state != value) {
626 uv_hub_info->scir.state = value;
627 uv_write_local_mmr8(uv_hub_info->scir.offset, value);
628 }
629}
630
631static inline unsigned long uv_scir_offset(int apicid)
632{
633 return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f);
634}
635
636static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
637{
638 if (uv_cpu_hub_info(cpu)->scir.state != value) {
639 uv_write_global_mmr8(uv_cpu_to_pnode(cpu),
640 uv_cpu_hub_info(cpu)->scir.offset, value);
641 uv_cpu_hub_info(cpu)->scir.state = value;
642 }
643}
644
645extern unsigned int uv_apicid_hibits;
646static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)
647{
648 apicid |= uv_apicid_hibits;
649 return (1UL << UVH_IPI_INT_SEND_SHFT) |
650 ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
651 (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
652 (vector << UVH_IPI_INT_VECTOR_SHFT);
653}
654
655static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
656{
657 unsigned long val;
658 unsigned long dmode = dest_Fixed;
659
660 if (vector == NMI_VECTOR)
661 dmode = dest_NMI;
662
663 val = uv_hub_ipi_value(apicid, vector, dmode);
664 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
665}
666
667
668
669
670
671
672
673
674static inline int uv_get_min_hub_revision_id(void)
675{
676 return uv_hub_info->hub_revision;
677}
678
679#endif
680#endif
681