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13#include "bcma_private.h"
14
15#include <linux/bcma/bcma.h>
16
17#include <linux/mtd/physmap.h>
18#include <linux/platform_device.h>
19#include <linux/serial.h>
20#include <linux/serial_core.h>
21#include <linux/serial_reg.h>
22#include <linux/time.h>
23#ifdef CONFIG_BCM47XX
24#include <linux/bcm47xx_nvram.h>
25#endif
26
27enum bcma_boot_dev {
28 BCMA_BOOT_DEV_UNK = 0,
29 BCMA_BOOT_DEV_ROM,
30 BCMA_BOOT_DEV_PARALLEL,
31 BCMA_BOOT_DEV_SERIAL,
32 BCMA_BOOT_DEV_NAND,
33};
34
35static const char * const part_probes[] = { "bcm47xxpart", NULL };
36
37static struct physmap_flash_data bcma_pflash_data = {
38 .part_probe_types = part_probes,
39};
40
41static struct resource bcma_pflash_resource = {
42 .name = "bcma_pflash",
43 .flags = IORESOURCE_MEM,
44};
45
46struct platform_device bcma_pflash_dev = {
47 .name = "physmap-flash",
48 .dev = {
49 .platform_data = &bcma_pflash_data,
50 },
51 .resource = &bcma_pflash_resource,
52 .num_resources = 1,
53};
54
55
56static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
57{
58 return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
59 dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
60}
61
62
63static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
64{
65 return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
66 dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
67 dev->bus->chipinfo.pkg == 11 &&
68 dev->id.id == BCMA_CORE_USB20_HOST;
69}
70
71static inline u32 mips_read32(struct bcma_drv_mips *mcore,
72 u16 offset)
73{
74 return bcma_read32(mcore->core, offset);
75}
76
77static inline void mips_write32(struct bcma_drv_mips *mcore,
78 u16 offset,
79 u32 value)
80{
81 bcma_write32(mcore->core, offset, value);
82}
83
84static const u32 ipsflag_irq_mask[] = {
85 0,
86 BCMA_MIPS_IPSFLAG_IRQ1,
87 BCMA_MIPS_IPSFLAG_IRQ2,
88 BCMA_MIPS_IPSFLAG_IRQ3,
89 BCMA_MIPS_IPSFLAG_IRQ4,
90};
91
92static const u32 ipsflag_irq_shift[] = {
93 0,
94 BCMA_MIPS_IPSFLAG_IRQ1_SHIFT,
95 BCMA_MIPS_IPSFLAG_IRQ2_SHIFT,
96 BCMA_MIPS_IPSFLAG_IRQ3_SHIFT,
97 BCMA_MIPS_IPSFLAG_IRQ4_SHIFT,
98};
99
100static u32 bcma_core_mips_irqflag(struct bcma_device *dev)
101{
102 u32 flag;
103
104 if (bcma_core_mips_bcm47162a0_quirk(dev))
105 return dev->core_index;
106 if (bcma_core_mips_bcm5357b0_quirk(dev))
107 return dev->core_index;
108 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
109
110 if (flag)
111 return flag & 0x1F;
112 else
113 return 0x3f;
114}
115
116
117
118
119
120
121unsigned int bcma_core_mips_irq(struct bcma_device *dev)
122{
123 struct bcma_device *mdev = dev->bus->drv_mips.core;
124 u32 irqflag;
125 unsigned int irq;
126
127 irqflag = bcma_core_mips_irqflag(dev);
128 if (irqflag == 0x3f)
129 return 6;
130
131 for (irq = 0; irq <= 4; irq++)
132 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
133 (1 << irqflag))
134 return irq;
135
136 return 5;
137}
138
139static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
140{
141 unsigned int oldirq = bcma_core_mips_irq(dev);
142 struct bcma_bus *bus = dev->bus;
143 struct bcma_device *mdev = bus->drv_mips.core;
144 u32 irqflag;
145
146 irqflag = bcma_core_mips_irqflag(dev);
147 BUG_ON(oldirq == 6);
148
149 dev->irq = irq + 2;
150
151
152 if (oldirq == 0)
153 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
154 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
155 ~(1 << irqflag));
156 else if (oldirq != 5)
157 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
158
159
160 if (irq == 0) {
161 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
162 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
163 (1 << irqflag));
164 } else {
165 u32 irqinitmask = bcma_read32(mdev,
166 BCMA_MIPS_MIPS74K_INTMASK(irq));
167 if (irqinitmask) {
168 struct bcma_device *core;
169
170
171
172
173 list_for_each_entry(core, &bus->cores, list) {
174 if ((1 << bcma_core_mips_irqflag(core)) ==
175 irqinitmask) {
176 bcma_core_mips_set_irq(core, 0);
177 break;
178 }
179 }
180 }
181 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq),
182 1 << irqflag);
183 }
184
185 bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
186 dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
187}
188
189static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
190 u16 coreid, u8 unit)
191{
192 struct bcma_device *core;
193
194 core = bcma_find_core_unit(bus, coreid, unit);
195 if (!core) {
196 bcma_warn(bus,
197 "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
198 coreid, unit);
199 return;
200 }
201
202 bcma_core_mips_set_irq(core, irq);
203}
204
205static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
206{
207 int i;
208 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
209 printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
210 for (i = 0; i <= 6; i++)
211 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
212 printk("\n");
213}
214
215static void bcma_core_mips_dump_irq(struct bcma_bus *bus)
216{
217 struct bcma_device *core;
218
219 list_for_each_entry(core, &bus->cores, list) {
220 bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
221 }
222}
223
224u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
225{
226 struct bcma_bus *bus = mcore->core->bus;
227
228 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
229 return bcma_pmu_get_cpu_clock(&bus->drv_cc);
230
231 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
232 return 0;
233}
234EXPORT_SYMBOL(bcma_cpu_clock);
235
236static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
237{
238 struct bcma_drv_cc *cc = &bus->drv_cc;
239 u8 cc_rev = cc->core->id.rev;
240
241 if (cc_rev == 42) {
242 struct bcma_device *core;
243
244 core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
245 if (core) {
246 switch (bcma_aread32(core, BCMA_IOST) &
247 BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
248 case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
249 return BCMA_BOOT_DEV_SERIAL;
250 case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
251 return BCMA_BOOT_DEV_NAND;
252 case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
253 default:
254 return BCMA_BOOT_DEV_ROM;
255 }
256 }
257 } else {
258 if (cc_rev == 38) {
259 if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
260 return BCMA_BOOT_DEV_NAND;
261 else if (cc->status & BIT(5))
262 return BCMA_BOOT_DEV_ROM;
263 }
264
265 if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
266 BCMA_CC_FLASHT_PARA)
267 return BCMA_BOOT_DEV_PARALLEL;
268 else
269 return BCMA_BOOT_DEV_SERIAL;
270 }
271
272 return BCMA_BOOT_DEV_SERIAL;
273}
274
275static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
276{
277 struct bcma_bus *bus = mcore->core->bus;
278 struct bcma_drv_cc *cc = &bus->drv_cc;
279 struct bcma_pflash *pflash = &cc->pflash;
280 enum bcma_boot_dev boot_dev;
281
282 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
283 case BCMA_CC_FLASHT_STSER:
284 case BCMA_CC_FLASHT_ATSER:
285 bcma_debug(bus, "Found serial flash\n");
286 bcma_sflash_init(cc);
287 break;
288 case BCMA_CC_FLASHT_PARA:
289 bcma_debug(bus, "Found parallel flash\n");
290 pflash->present = true;
291 pflash->window = BCMA_SOC_FLASH2;
292 pflash->window_size = BCMA_SOC_FLASH2_SZ;
293
294 if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
295 BCMA_CC_FLASH_CFG_DS) == 0)
296 pflash->buswidth = 1;
297 else
298 pflash->buswidth = 2;
299
300 bcma_pflash_data.width = pflash->buswidth;
301 bcma_pflash_resource.start = pflash->window;
302 bcma_pflash_resource.end = pflash->window + pflash->window_size;
303
304 break;
305 default:
306 bcma_err(bus, "Flash type not supported\n");
307 }
308
309 if (cc->core->id.rev == 38 ||
310 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
311 if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
312 bcma_debug(bus, "Found NAND flash\n");
313 bcma_nflash_init(cc);
314 }
315 }
316
317
318 boot_dev = bcma_boot_dev(bus);
319 switch (boot_dev) {
320 case BCMA_BOOT_DEV_PARALLEL:
321 case BCMA_BOOT_DEV_SERIAL:
322#ifdef CONFIG_BCM47XX
323 bcm47xx_nvram_init_from_mem(BCMA_SOC_FLASH2,
324 BCMA_SOC_FLASH2_SZ);
325#endif
326 break;
327 case BCMA_BOOT_DEV_NAND:
328#ifdef CONFIG_BCM47XX
329 bcm47xx_nvram_init_from_mem(BCMA_SOC_FLASH1,
330 BCMA_SOC_FLASH1_SZ);
331#endif
332 break;
333 default:
334 break;
335 }
336}
337
338void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
339{
340 struct bcma_bus *bus = mcore->core->bus;
341
342 if (mcore->early_setup_done)
343 return;
344
345 bcma_chipco_serial_init(&bus->drv_cc);
346 bcma_core_mips_flash_detect(mcore);
347
348 mcore->early_setup_done = true;
349}
350
351static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
352{
353 struct bcma_device *cpu, *pcie, *i2s;
354
355
356
357
358 if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
359 bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
360 return;
361
362 cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
363 pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
364 i2s = bcma_find_core(bus, BCMA_CORE_I2S);
365 if (cpu && pcie && i2s &&
366 bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
367 bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
368 bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
369 bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
370 bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
371 bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
372 bcma_debug(bus,
373 "Moved i2s interrupt to oob line 7 instead of 8\n");
374 }
375}
376
377void bcma_core_mips_init(struct bcma_drv_mips *mcore)
378{
379 struct bcma_bus *bus;
380 struct bcma_device *core;
381 bus = mcore->core->bus;
382
383 if (mcore->setup_done)
384 return;
385
386 bcma_debug(bus, "Initializing MIPS core...\n");
387
388 bcma_core_mips_early_init(mcore);
389
390 bcma_fix_i2s_irqflag(bus);
391
392 switch (bus->chipinfo.id) {
393 case BCMA_CHIP_ID_BCM4716:
394 case BCMA_CHIP_ID_BCM4748:
395 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
396 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
397 bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
398 bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
399 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
400 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
401 break;
402 case BCMA_CHIP_ID_BCM5356:
403 case BCMA_CHIP_ID_BCM47162:
404 case BCMA_CHIP_ID_BCM53572:
405 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
406 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
407 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
408 break;
409 case BCMA_CHIP_ID_BCM5357:
410 case BCMA_CHIP_ID_BCM4749:
411 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
412 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
413 bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
414 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
415 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
416 break;
417 case BCMA_CHIP_ID_BCM4706:
418 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
419 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
420 0);
421 bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
422 bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
423 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
424 0);
425 break;
426 default:
427 list_for_each_entry(core, &bus->cores, list) {
428 core->irq = bcma_core_irq(core, 0);
429 }
430 bcma_err(bus,
431 "Unknown device (0x%x) found, can not configure IRQs\n",
432 bus->chipinfo.id);
433 }
434 bcma_debug(bus, "IRQ reconfiguration done\n");
435 bcma_core_mips_dump_irq(bus);
436
437 mcore->setup_done = true;
438}
439
