LXR linux/drivers/clk/mvebu/armada-xp.c

   1/*
   2 * Marvell Armada XP SoC clocks
   3 *
   4 * Copyright (C) 2012 Marvell
   5 *
   6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
   7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   8 * Andrew Lunn <andrew@lunn.ch>
   9 *
  10 * This file is licensed under the terms of the GNU General Public
  11 * License version 2.  This program is licensed "as is" without any
  12 * warranty of any kind, whether express or implied.
  13 */
  14
  15#include <linux/kernel.h>
  16#include <linux/clk-provider.h>
  17#include <linux/io.h>
  18#include <linux/of.h>
  19#include "common.h"
  20
  21/*
  22 * Core Clocks
  23 *
  24 * Armada XP Sample At Reset is a 64 bit bitfiled split in two
  25 * register of 32 bits
  26 */
  27
  28#define SARL                            0       /* Low part [0:31] */
  29#define  SARL_AXP_PCLK_FREQ_OPT         21
  30#define  SARL_AXP_PCLK_FREQ_OPT_MASK    0x7
  31#define  SARL_AXP_FAB_FREQ_OPT          24
  32#define  SARL_AXP_FAB_FREQ_OPT_MASK     0xF
  33#define SARH                            4       /* High part [32:63] */
  34#define  SARH_AXP_PCLK_FREQ_OPT         (52-32)
  35#define  SARH_AXP_PCLK_FREQ_OPT_MASK    0x1
  36#define  SARH_AXP_PCLK_FREQ_OPT_SHIFT   3
  37#define  SARH_AXP_FAB_FREQ_OPT          (51-32)
  38#define  SARH_AXP_FAB_FREQ_OPT_MASK     0x1
  39#define  SARH_AXP_FAB_FREQ_OPT_SHIFT    4
  40
  41enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
  42
  43static const struct coreclk_ratio axp_coreclk_ratios[] __initconst = {
  44        { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
  45        { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
  46        { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
  47};
  48
  49/* Armada XP TCLK frequency is fixed to 250MHz */
  50static u32 __init axp_get_tclk_freq(void __iomem *sar)
  51{
  52        return 250000000;
  53}
  54
  55static const u32 axp_cpu_freqs[] __initconst = {
  56        1000000000,
  57        1066000000,
  58        1200000000,
  59        1333000000,
  60        1500000000,
  61        1666000000,
  62        1800000000,
  63        2000000000,
  64        667000000,
  65        0,
  66        800000000,
  67        1600000000,
  68};
  69
  70static u32 __init axp_get_cpu_freq(void __iomem *sar)
  71{
  72        u32 cpu_freq;
  73        u8 cpu_freq_select = 0;
  74
  75        cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
  76                           SARL_AXP_PCLK_FREQ_OPT_MASK);
  77        /*
  78         * The upper bit is not contiguous to the other ones and
  79         * located in the high part of the SAR registers
  80         */
  81        cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
  82             SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
  83        if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
  84                pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
  85                cpu_freq = 0;
  86        } else
  87                cpu_freq = axp_cpu_freqs[cpu_freq_select];
  88
  89        return cpu_freq;
  90}
  91
  92static const int axp_nbclk_ratios[32][2] __initconst = {
  93        {0, 1}, {1, 2}, {2, 2}, {2, 2},
  94        {1, 2}, {1, 2}, {1, 1}, {2, 3},
  95        {0, 1}, {1, 2}, {2, 4}, {0, 1},
  96        {1, 2}, {0, 1}, {0, 1}, {2, 2},
  97        {0, 1}, {0, 1}, {0, 1}, {1, 1},
  98        {2, 3}, {0, 1}, {0, 1}, {0, 1},
  99        {0, 1}, {0, 1}, {0, 1}, {1, 1},
 100        {0, 1}, {0, 1}, {0, 1}, {0, 1},
 101};
 102
 103static const int axp_hclk_ratios[32][2] __initconst = {
 104        {0, 1}, {1, 2}, {2, 6}, {2, 3},
 105        {1, 3}, {1, 4}, {1, 2}, {2, 6},
 106        {0, 1}, {1, 6}, {2, 10}, {0, 1},
 107        {1, 4}, {0, 1}, {0, 1}, {2, 5},
 108        {0, 1}, {0, 1}, {0, 1}, {1, 2},
 109        {2, 6}, {0, 1}, {0, 1}, {0, 1},
 110        {0, 1}, {0, 1}, {0, 1}, {1, 1},
 111        {0, 1}, {0, 1}, {0, 1}, {0, 1},
 112};
 113
 114static const int axp_dramclk_ratios[32][2] __initconst = {
 115        {0, 1}, {1, 2}, {2, 3}, {2, 3},
 116        {1, 3}, {1, 2}, {1, 2}, {2, 6},
 117        {0, 1}, {1, 3}, {2, 5}, {0, 1},
 118        {1, 4}, {0, 1}, {0, 1}, {2, 5},
 119        {0, 1}, {0, 1}, {0, 1}, {1, 1},
 120        {2, 3}, {0, 1}, {0, 1}, {0, 1},
 121        {0, 1}, {0, 1}, {0, 1}, {1, 1},
 122        {0, 1}, {0, 1}, {0, 1}, {0, 1},
 123};
 124
 125static void __init axp_get_clk_ratio(
 126        void __iomem *sar, int id, int *mult, int *div)
 127{
 128        u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
 129              SARL_AXP_FAB_FREQ_OPT_MASK);
 130        /*
 131         * The upper bit is not contiguous to the other ones and
 132         * located in the high part of the SAR registers
 133         */
 134        opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
 135                 SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
 136
 137        switch (id) {
 138        case AXP_CPU_TO_NBCLK:
 139                *mult = axp_nbclk_ratios[opt][0];
 140                *div = axp_nbclk_ratios[opt][1];
 141                break;
 142        case AXP_CPU_TO_HCLK:
 143                *mult = axp_hclk_ratios[opt][0];
 144                *div = axp_hclk_ratios[opt][1];
 145                break;
 146        case AXP_CPU_TO_DRAMCLK:
 147                *mult = axp_dramclk_ratios[opt][0];
 148                *div = axp_dramclk_ratios[opt][1];
 149                break;
 150        }
 151}
 152
 153static const struct coreclk_soc_desc axp_coreclks = {
 154        .get_tclk_freq = axp_get_tclk_freq,
 155        .get_cpu_freq = axp_get_cpu_freq,
 156        .get_clk_ratio = axp_get_clk_ratio,
 157        .ratios = axp_coreclk_ratios,
 158        .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
 159};
 160
 161/*
 162 * Clock Gating Control
 163 */
 164
 165static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
 166        { "audio", NULL, 0, 0 },
 167        { "ge3", NULL, 1, 0 },
 168        { "ge2", NULL,  2, 0 },
 169        { "ge1", NULL, 3, 0 },
 170        { "ge0", NULL, 4, 0 },
 171        { "pex00", NULL, 5, 0 },
 172        { "pex01", NULL, 6, 0 },
 173        { "pex02", NULL, 7, 0 },
 174        { "pex03", NULL, 8, 0 },
 175        { "pex10", NULL, 9, 0 },
 176        { "pex11", NULL, 10, 0 },
 177        { "pex12", NULL, 11, 0 },
 178        { "pex13", NULL, 12, 0 },
 179        { "bp", NULL, 13, 0 },
 180        { "sata0lnk", NULL, 14, 0 },
 181        { "sata0", "sata0lnk", 15, 0 },
 182        { "lcd", NULL, 16, 0 },
 183        { "sdio", NULL, 17, 0 },
 184        { "usb0", NULL, 18, 0 },
 185        { "usb1", NULL, 19, 0 },
 186        { "usb2", NULL, 20, 0 },
 187        { "xor0", NULL, 22, 0 },
 188        { "crypto", NULL, 23, 0 },
 189        { "tdm", NULL, 25, 0 },
 190        { "pex20", NULL, 26, 0 },
 191        { "pex30", NULL, 27, 0 },
 192        { "xor1", NULL, 28, 0 },
 193        { "sata1lnk", NULL, 29, 0 },
 194        { "sata1", "sata1lnk", 30, 0 },
 195        { }
 196};
 197
 198static void __init axp_clk_init(struct device_node *np)
 199{
 200        struct device_node *cgnp =
 201                of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
 202
 203        mvebu_coreclk_setup(np, &axp_coreclks);
 204
 205        if (cgnp)
 206                mvebu_clk_gating_setup(cgnp, axp_gating_desc);
 207}
 208CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
 209