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16#include <asm/div64.h>
17#include <linux/slab.h>
18#include <linux/io.h>
19#include <linux/delay.h>
20#include <linux/clk-provider.h>
21#include <linux/regmap.h>
22#include "clk.h"
23
24#define PLL_MODE_MASK 0x3
25#define PLL_MODE_SLOW 0x0
26#define PLL_MODE_NORM 0x1
27#define PLL_MODE_DEEP 0x2
28
29struct rockchip_clk_pll {
30 struct clk_hw hw;
31
32 struct clk_mux pll_mux;
33 const struct clk_ops *pll_mux_ops;
34
35 struct notifier_block clk_nb;
36
37 void __iomem *reg_base;
38 int lock_offset;
39 unsigned int lock_shift;
40 enum rockchip_pll_type type;
41 u8 flags;
42 const struct rockchip_pll_rate_table *rate_table;
43 unsigned int rate_count;
44 spinlock_t *lock;
45};
46
47#define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
48#define to_rockchip_clk_pll_nb(nb) \
49 container_of(nb, struct rockchip_clk_pll, clk_nb)
50
51static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
52 struct rockchip_clk_pll *pll, unsigned long rate)
53{
54 const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
55 int i;
56
57 for (i = 0; i < pll->rate_count; i++) {
58 if (rate == rate_table[i].rate)
59 return &rate_table[i];
60 }
61
62 return NULL;
63}
64
65static long rockchip_pll_round_rate(struct clk_hw *hw,
66 unsigned long drate, unsigned long *prate)
67{
68 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
69 const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
70 int i;
71
72
73 for (i = 0; i < pll->rate_count; i++) {
74 if (drate >= rate_table[i].rate)
75 return rate_table[i].rate;
76 }
77
78
79 return rate_table[i - 1].rate;
80}
81
82
83
84
85
86
87static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
88{
89 struct regmap *grf = rockchip_clk_get_grf();
90 unsigned int val;
91 int delay = 24000000, ret;
92
93 while (delay > 0) {
94 ret = regmap_read(grf, pll->lock_offset, &val);
95 if (ret) {
96 pr_err("%s: failed to read pll lock status: %d\n",
97 __func__, ret);
98 return ret;
99 }
100
101 if (val & BIT(pll->lock_shift))
102 return 0;
103 delay--;
104 }
105
106 pr_err("%s: timeout waiting for pll to lock\n", __func__);
107 return -ETIMEDOUT;
108}
109
110
111
112
113
114#define RK3066_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1)
115
116#define RK3066_PLLCON(i) (i * 0x4)
117#define RK3066_PLLCON0_OD_MASK 0xf
118#define RK3066_PLLCON0_OD_SHIFT 0
119#define RK3066_PLLCON0_NR_MASK 0x3f
120#define RK3066_PLLCON0_NR_SHIFT 8
121#define RK3066_PLLCON1_NF_MASK 0x1fff
122#define RK3066_PLLCON1_NF_SHIFT 0
123#define RK3066_PLLCON2_NB_MASK 0xfff
124#define RK3066_PLLCON2_NB_SHIFT 0
125#define RK3066_PLLCON3_RESET (1 << 5)
126#define RK3066_PLLCON3_PWRDOWN (1 << 1)
127#define RK3066_PLLCON3_BYPASS (1 << 0)
128
129static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
130 unsigned long prate)
131{
132 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
133 u64 nf, nr, no, rate64 = prate;
134 u32 pllcon;
135
136 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
137 if (pllcon & RK3066_PLLCON3_BYPASS) {
138 pr_debug("%s: pll %s is bypassed\n", __func__,
139 clk_hw_get_name(hw));
140 return prate;
141 }
142
143 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
144 nf = (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK;
145
146 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
147 nr = (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK;
148 no = (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK;
149
150 rate64 *= (nf + 1);
151 do_div(rate64, nr + 1);
152 do_div(rate64, no + 1);
153
154 return (unsigned long)rate64;
155}
156
157static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
158 unsigned long prate)
159{
160 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
161 const struct rockchip_pll_rate_table *rate;
162 unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);
163 struct regmap *grf = rockchip_clk_get_grf();
164 struct clk_mux *pll_mux = &pll->pll_mux;
165 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
166 int rate_change_remuxed = 0;
167 int cur_parent;
168 int ret;
169
170 if (IS_ERR(grf)) {
171 pr_debug("%s: grf regmap not available, aborting rate change\n",
172 __func__);
173 return PTR_ERR(grf);
174 }
175
176 pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
177 __func__, clk_hw_get_name(hw), old_rate, drate, prate);
178
179
180 rate = rockchip_get_pll_settings(pll, drate);
181 if (!rate) {
182 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
183 drate, clk_hw_get_name(hw));
184 return -EINVAL;
185 }
186
187 pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
188 __func__, rate->rate, rate->nr, rate->no, rate->nf);
189
190 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
191 if (cur_parent == PLL_MODE_NORM) {
192 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
193 rate_change_remuxed = 1;
194 }
195
196
197 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
198 pll->reg_base + RK3066_PLLCON(3));
199
200
201 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
202 RK3066_PLLCON0_NR_SHIFT) |
203 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
204 RK3066_PLLCON0_OD_SHIFT),
205 pll->reg_base + RK3066_PLLCON(0));
206
207 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
208 RK3066_PLLCON1_NF_SHIFT),
209 pll->reg_base + RK3066_PLLCON(1));
210 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
211 RK3066_PLLCON2_NB_SHIFT),
212 pll->reg_base + RK3066_PLLCON(2));
213
214
215 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
216 pll->reg_base + RK3066_PLLCON(3));
217 udelay(RK3066_PLL_RESET_DELAY(rate->nr));
218
219
220 ret = rockchip_pll_wait_lock(pll);
221 if (ret) {
222 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
223 __func__, old_rate);
224 rockchip_rk3066_pll_set_rate(hw, old_rate, prate);
225 }
226
227 if (rate_change_remuxed)
228 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
229
230 return ret;
231}
232
233static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
234{
235 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
236
237 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
238 pll->reg_base + RK3066_PLLCON(3));
239
240 return 0;
241}
242
243static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
244{
245 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
246
247 writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
248 RK3066_PLLCON3_PWRDOWN, 0),
249 pll->reg_base + RK3066_PLLCON(3));
250}
251
252static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
253{
254 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
255 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
256
257 return !(pllcon & RK3066_PLLCON3_PWRDOWN);
258}
259
260static void rockchip_rk3066_pll_init(struct clk_hw *hw)
261{
262 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
263 const struct rockchip_pll_rate_table *rate;
264 unsigned int nf, nr, no, nb;
265 unsigned long drate;
266 u32 pllcon;
267
268 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
269 return;
270
271 drate = clk_hw_get_rate(hw);
272 rate = rockchip_get_pll_settings(pll, drate);
273
274
275 if (!rate)
276 return;
277
278 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
279 nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK) + 1;
280 no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK) + 1;
281
282 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
283 nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK) + 1;
284
285 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
286 nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) & RK3066_PLLCON2_NB_MASK) + 1;
287
288 pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",
289 __func__, clk_hw_get_name(hw), drate, rate->nr, nr,
290 rate->no, no, rate->nf, nf, rate->nb, nb);
291 if (rate->nr != nr || rate->no != no || rate->nf != nf
292 || rate->nb != nb) {
293 struct clk_hw *parent = clk_hw_get_parent(hw);
294 unsigned long prate;
295
296 if (!parent) {
297 pr_warn("%s: parent of %s not available\n",
298 __func__, clk_hw_get_name(hw));
299 return;
300 }
301
302 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
303 __func__, clk_hw_get_name(hw));
304 prate = clk_hw_get_rate(parent);
305 rockchip_rk3066_pll_set_rate(hw, drate, prate);
306 }
307}
308
309static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
310 .recalc_rate = rockchip_rk3066_pll_recalc_rate,
311 .enable = rockchip_rk3066_pll_enable,
312 .disable = rockchip_rk3066_pll_disable,
313 .is_enabled = rockchip_rk3066_pll_is_enabled,
314};
315
316static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
317 .recalc_rate = rockchip_rk3066_pll_recalc_rate,
318 .round_rate = rockchip_pll_round_rate,
319 .set_rate = rockchip_rk3066_pll_set_rate,
320 .enable = rockchip_rk3066_pll_enable,
321 .disable = rockchip_rk3066_pll_disable,
322 .is_enabled = rockchip_rk3066_pll_is_enabled,
323 .init = rockchip_rk3066_pll_init,
324};
325
326
327
328
329
330struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
331 const char *name, const char *const *parent_names,
332 u8 num_parents, void __iomem *base, int con_offset,
333 int grf_lock_offset, int lock_shift, int mode_offset,
334 int mode_shift, struct rockchip_pll_rate_table *rate_table,
335 u8 clk_pll_flags, spinlock_t *lock)
336{
337 const char *pll_parents[3];
338 struct clk_init_data init;
339 struct rockchip_clk_pll *pll;
340 struct clk_mux *pll_mux;
341 struct clk *pll_clk, *mux_clk;
342 char pll_name[20];
343
344 if (num_parents != 2) {
345 pr_err("%s: needs two parent clocks\n", __func__);
346 return ERR_PTR(-EINVAL);
347 }
348
349
350 snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
351
352 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
353 if (!pll)
354 return ERR_PTR(-ENOMEM);
355
356
357 pll->pll_mux_ops = &clk_mux_ops;
358 pll_mux = &pll->pll_mux;
359 pll_mux->reg = base + mode_offset;
360 pll_mux->shift = mode_shift;
361 pll_mux->mask = PLL_MODE_MASK;
362 pll_mux->flags = 0;
363 pll_mux->lock = lock;
364 pll_mux->hw.init = &init;
365
366 if (pll_type == pll_rk3066)
367 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
368
369
370 pll_parents[0] = parent_names[0];
371 pll_parents[1] = pll_name;
372 pll_parents[2] = parent_names[1];
373
374 init.name = name;
375 init.flags = CLK_SET_RATE_PARENT;
376 init.ops = pll->pll_mux_ops;
377 init.parent_names = pll_parents;
378 init.num_parents = ARRAY_SIZE(pll_parents);
379
380 mux_clk = clk_register(NULL, &pll_mux->hw);
381 if (IS_ERR(mux_clk))
382 goto err_mux;
383
384
385 init.name = pll_name;
386
387
388 init.flags = CLK_IGNORE_UNUSED;
389
390 init.parent_names = &parent_names[0];
391 init.num_parents = 1;
392
393 if (rate_table) {
394 int len;
395
396
397 for (len = 0; rate_table[len].rate != 0; )
398 len++;
399
400 pll->rate_count = len;
401 pll->rate_table = kmemdup(rate_table,
402 pll->rate_count *
403 sizeof(struct rockchip_pll_rate_table),
404 GFP_KERNEL);
405 WARN(!pll->rate_table,
406 "%s: could not allocate rate table for %s\n",
407 __func__, name);
408 }
409
410 switch (pll_type) {
411 case pll_rk3066:
412 if (!pll->rate_table)
413 init.ops = &rockchip_rk3066_pll_clk_norate_ops;
414 else
415 init.ops = &rockchip_rk3066_pll_clk_ops;
416 break;
417 default:
418 pr_warn("%s: Unknown pll type for pll clk %s\n",
419 __func__, name);
420 }
421
422 pll->hw.init = &init;
423 pll->type = pll_type;
424 pll->reg_base = base + con_offset;
425 pll->lock_offset = grf_lock_offset;
426 pll->lock_shift = lock_shift;
427 pll->flags = clk_pll_flags;
428 pll->lock = lock;
429
430 pll_clk = clk_register(NULL, &pll->hw);
431 if (IS_ERR(pll_clk)) {
432 pr_err("%s: failed to register pll clock %s : %ld\n",
433 __func__, name, PTR_ERR(pll_clk));
434 goto err_pll;
435 }
436
437 return mux_clk;
438
439err_pll:
440 clk_unregister(mux_clk);
441 mux_clk = pll_clk;
442err_mux:
443 kfree(pll);
444 return mux_clk;
445}
446
