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17#include <linux/slab.h>
18#include <linux/io.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/clk-provider.h>
23
24#include "clk.h"
25
26#define PLL_BASE_BYPASS BIT(31)
27#define PLL_BASE_ENABLE BIT(30)
28#define PLL_BASE_REF_ENABLE BIT(29)
29#define PLL_BASE_OVERRIDE BIT(28)
30
31#define PLL_BASE_DIVP_SHIFT 20
32#define PLL_BASE_DIVP_WIDTH 3
33#define PLL_BASE_DIVN_SHIFT 8
34#define PLL_BASE_DIVN_WIDTH 10
35#define PLL_BASE_DIVM_SHIFT 0
36#define PLL_BASE_DIVM_WIDTH 5
37#define PLLU_POST_DIVP_MASK 0x1
38
39#define PLL_MISC_DCCON_SHIFT 20
40#define PLL_MISC_CPCON_SHIFT 8
41#define PLL_MISC_CPCON_WIDTH 4
42#define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43#define PLL_MISC_LFCON_SHIFT 4
44#define PLL_MISC_LFCON_WIDTH 4
45#define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46#define PLL_MISC_VCOCON_SHIFT 0
47#define PLL_MISC_VCOCON_WIDTH 4
48#define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
49
50#define OUT_OF_TABLE_CPCON 8
51
52#define PMC_PLLP_WB0_OVERRIDE 0xf8
53#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
55
56#define PLL_POST_LOCK_DELAY 50
57
58#define PLLDU_LFCON_SET_DIVN 600
59
60#define PLLE_BASE_DIVCML_SHIFT 24
61#define PLLE_BASE_DIVCML_MASK 0xf
62#define PLLE_BASE_DIVP_SHIFT 16
63#define PLLE_BASE_DIVP_WIDTH 6
64#define PLLE_BASE_DIVN_SHIFT 8
65#define PLLE_BASE_DIVN_WIDTH 8
66#define PLLE_BASE_DIVM_SHIFT 0
67#define PLLE_BASE_DIVM_WIDTH 8
68
69#define PLLE_MISC_SETUP_BASE_SHIFT 16
70#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
71#define PLLE_MISC_LOCK_ENABLE BIT(9)
72#define PLLE_MISC_READY BIT(15)
73#define PLLE_MISC_SETUP_EX_SHIFT 2
74#define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
75#define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
76 PLLE_MISC_SETUP_EX_MASK)
77#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
78
79#define PLLE_SS_CTRL 0x68
80#define PLLE_SS_CNTL_BYPASS_SS BIT(10)
81#define PLLE_SS_CNTL_INTERP_RESET BIT(11)
82#define PLLE_SS_CNTL_SSC_BYP BIT(12)
83#define PLLE_SS_CNTL_CENTER BIT(14)
84#define PLLE_SS_CNTL_INVERT BIT(15)
85#define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
86 PLLE_SS_CNTL_SSC_BYP)
87#define PLLE_SS_MAX_MASK 0x1ff
88#define PLLE_SS_MAX_VAL 0x25
89#define PLLE_SS_INC_MASK (0xff << 16)
90#define PLLE_SS_INC_VAL (0x1 << 16)
91#define PLLE_SS_INCINTRV_MASK (0x3f << 24)
92#define PLLE_SS_INCINTRV_VAL (0x20 << 24)
93#define PLLE_SS_COEFFICIENTS_MASK \
94 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
95#define PLLE_SS_COEFFICIENTS_VAL \
96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
97
98#define PLLE_AUX_PLLP_SEL BIT(2)
99#define PLLE_AUX_USE_LOCKDET BIT(3)
100#define PLLE_AUX_ENABLE_SWCTL BIT(4)
101#define PLLE_AUX_SS_SWCTL BIT(6)
102#define PLLE_AUX_SEQ_ENABLE BIT(24)
103#define PLLE_AUX_SEQ_START_STATE BIT(25)
104#define PLLE_AUX_PLLRE_SEL BIT(28)
105
106#define XUSBIO_PLL_CFG0 0x51c
107#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
108#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
109#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
110#define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
111#define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
112
113#define SATA_PLL_CFG0 0x490
114#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
115#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
116#define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
117#define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
118
119#define PLLE_MISC_PLLE_PTS BIT(8)
120#define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
121#define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
122#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
123#define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
124#define PLLE_MISC_VREG_CTRL_SHIFT 2
125#define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
126
127#define PLLCX_MISC_STROBE BIT(31)
128#define PLLCX_MISC_RESET BIT(30)
129#define PLLCX_MISC_SDM_DIV_SHIFT 28
130#define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
131#define PLLCX_MISC_FILT_DIV_SHIFT 26
132#define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
133#define PLLCX_MISC_ALPHA_SHIFT 18
134#define PLLCX_MISC_DIV_LOW_RANGE \
135 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
136 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
137#define PLLCX_MISC_DIV_HIGH_RANGE \
138 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
139 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
140#define PLLCX_MISC_COEF_LOW_RANGE \
141 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
142#define PLLCX_MISC_KA_SHIFT 2
143#define PLLCX_MISC_KB_SHIFT 9
144#define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
145 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
146 PLLCX_MISC_DIV_LOW_RANGE | \
147 PLLCX_MISC_RESET)
148#define PLLCX_MISC1_DEFAULT 0x000d2308
149#define PLLCX_MISC2_DEFAULT 0x30211200
150#define PLLCX_MISC3_DEFAULT 0x200
151
152#define PMC_SATA_PWRGT 0x1ac
153#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
154#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
155
156#define PLLSS_MISC_KCP 0
157#define PLLSS_MISC_KVCO 0
158#define PLLSS_MISC_SETUP 0
159#define PLLSS_EN_SDM 0
160#define PLLSS_EN_SSC 0
161#define PLLSS_EN_DITHER2 0
162#define PLLSS_EN_DITHER 1
163#define PLLSS_SDM_RESET 0
164#define PLLSS_CLAMP 0
165#define PLLSS_SDM_SSC_MAX 0
166#define PLLSS_SDM_SSC_MIN 0
167#define PLLSS_SDM_SSC_STEP 0
168#define PLLSS_SDM_DIN 0
169#define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
170 (PLLSS_MISC_KVCO << 24) | \
171 PLLSS_MISC_SETUP)
172#define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
173 (PLLSS_EN_SSC << 30) | \
174 (PLLSS_EN_DITHER2 << 29) | \
175 (PLLSS_EN_DITHER << 28) | \
176 (PLLSS_SDM_RESET) << 27 | \
177 (PLLSS_CLAMP << 22))
178#define PLLSS_CTRL1_DEFAULT \
179 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
180#define PLLSS_CTRL2_DEFAULT \
181 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
182#define PLLSS_LOCK_OVERRIDE BIT(24)
183#define PLLSS_REF_SRC_SEL_SHIFT 25
184#define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
185
186#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
187#define pll_readl_base(p) pll_readl(p->params->base_reg, p)
188#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
189#define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
190
191#define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
192#define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
193#define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
194#define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
195
196#define mask(w) ((1 << (w)) - 1)
197#define divm_mask(p) mask(p->params->div_nmp->divm_width)
198#define divn_mask(p) mask(p->params->div_nmp->divn_width)
199#define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
200 mask(p->params->div_nmp->divp_width))
201
202#define divm_shift(p) (p)->params->div_nmp->divm_shift
203#define divn_shift(p) (p)->params->div_nmp->divn_shift
204#define divp_shift(p) (p)->params->div_nmp->divp_shift
205
206#define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
207#define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
208#define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
209
210#define divm_max(p) (divm_mask(p))
211#define divn_max(p) (divn_mask(p))
212#define divp_max(p) (1 << (divp_mask(p)))
213
214static struct div_nmp default_nmp = {
215 .divn_shift = PLL_BASE_DIVN_SHIFT,
216 .divn_width = PLL_BASE_DIVN_WIDTH,
217 .divm_shift = PLL_BASE_DIVM_SHIFT,
218 .divm_width = PLL_BASE_DIVM_WIDTH,
219 .divp_shift = PLL_BASE_DIVP_SHIFT,
220 .divp_width = PLL_BASE_DIVP_WIDTH,
221};
222
223static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
224{
225 u32 val;
226
227 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
228 return;
229
230 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
231 return;
232
233 val = pll_readl_misc(pll);
234 val |= BIT(pll->params->lock_enable_bit_idx);
235 pll_writel_misc(val, pll);
236}
237
238static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
239{
240 int i;
241 u32 val, lock_mask;
242 void __iomem *lock_addr;
243
244 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
245 udelay(pll->params->lock_delay);
246 return 0;
247 }
248
249 lock_addr = pll->clk_base;
250 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
251 lock_addr += pll->params->misc_reg;
252 else
253 lock_addr += pll->params->base_reg;
254
255 lock_mask = pll->params->lock_mask;
256
257 for (i = 0; i < pll->params->lock_delay; i++) {
258 val = readl_relaxed(lock_addr);
259 if ((val & lock_mask) == lock_mask) {
260 udelay(PLL_POST_LOCK_DELAY);
261 return 0;
262 }
263 udelay(2);
264 }
265
266 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
267 clk_hw_get_name(&pll->hw));
268
269 return -1;
270}
271
272static int clk_pll_is_enabled(struct clk_hw *hw)
273{
274 struct tegra_clk_pll *pll = to_clk_pll(hw);
275 u32 val;
276
277 if (pll->params->flags & TEGRA_PLLM) {
278 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
279 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
280 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
281 }
282
283 val = pll_readl_base(pll);
284
285 return val & PLL_BASE_ENABLE ? 1 : 0;
286}
287
288static void _clk_pll_enable(struct clk_hw *hw)
289{
290 struct tegra_clk_pll *pll = to_clk_pll(hw);
291 u32 val;
292
293 clk_pll_enable_lock(pll);
294
295 val = pll_readl_base(pll);
296 if (pll->params->flags & TEGRA_PLL_BYPASS)
297 val &= ~PLL_BASE_BYPASS;
298 val |= PLL_BASE_ENABLE;
299 pll_writel_base(val, pll);
300
301 if (pll->params->flags & TEGRA_PLLM) {
302 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
303 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
304 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
305 }
306}
307
308static void _clk_pll_disable(struct clk_hw *hw)
309{
310 struct tegra_clk_pll *pll = to_clk_pll(hw);
311 u32 val;
312
313 val = pll_readl_base(pll);
314 if (pll->params->flags & TEGRA_PLL_BYPASS)
315 val &= ~PLL_BASE_BYPASS;
316 val &= ~PLL_BASE_ENABLE;
317 pll_writel_base(val, pll);
318
319 if (pll->params->flags & TEGRA_PLLM) {
320 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
321 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
322 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
323 }
324}
325
326static int clk_pll_enable(struct clk_hw *hw)
327{
328 struct tegra_clk_pll *pll = to_clk_pll(hw);
329 unsigned long flags = 0;
330 int ret;
331
332 if (pll->lock)
333 spin_lock_irqsave(pll->lock, flags);
334
335 _clk_pll_enable(hw);
336
337 ret = clk_pll_wait_for_lock(pll);
338
339 if (pll->lock)
340 spin_unlock_irqrestore(pll->lock, flags);
341
342 return ret;
343}
344
345static void clk_pll_disable(struct clk_hw *hw)
346{
347 struct tegra_clk_pll *pll = to_clk_pll(hw);
348 unsigned long flags = 0;
349
350 if (pll->lock)
351 spin_lock_irqsave(pll->lock, flags);
352
353 _clk_pll_disable(hw);
354
355 if (pll->lock)
356 spin_unlock_irqrestore(pll->lock, flags);
357}
358
359static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
360{
361 struct tegra_clk_pll *pll = to_clk_pll(hw);
362 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
363
364 if (p_tohw) {
365 while (p_tohw->pdiv) {
366 if (p_div <= p_tohw->pdiv)
367 return p_tohw->hw_val;
368 p_tohw++;
369 }
370 return -EINVAL;
371 }
372 return -EINVAL;
373}
374
375static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
376{
377 struct tegra_clk_pll *pll = to_clk_pll(hw);
378 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
379
380 if (p_tohw) {
381 while (p_tohw->pdiv) {
382 if (p_div_hw == p_tohw->hw_val)
383 return p_tohw->pdiv;
384 p_tohw++;
385 }
386 return -EINVAL;
387 }
388
389 return 1 << p_div_hw;
390}
391
392static int _get_table_rate(struct clk_hw *hw,
393 struct tegra_clk_pll_freq_table *cfg,
394 unsigned long rate, unsigned long parent_rate)
395{
396 struct tegra_clk_pll *pll = to_clk_pll(hw);
397 struct tegra_clk_pll_freq_table *sel;
398
399 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
400 if (sel->input_rate == parent_rate &&
401 sel->output_rate == rate)
402 break;
403
404 if (sel->input_rate == 0)
405 return -EINVAL;
406
407 cfg->input_rate = sel->input_rate;
408 cfg->output_rate = sel->output_rate;
409 cfg->m = sel->m;
410 cfg->n = sel->n;
411 cfg->p = sel->p;
412 cfg->cpcon = sel->cpcon;
413
414 return 0;
415}
416
417static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
418 unsigned long rate, unsigned long parent_rate)
419{
420 struct tegra_clk_pll *pll = to_clk_pll(hw);
421 unsigned long cfreq;
422 u32 p_div = 0;
423 int ret;
424
425 switch (parent_rate) {
426 case 12000000:
427 case 26000000:
428 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
429 break;
430 case 13000000:
431 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
432 break;
433 case 16800000:
434 case 19200000:
435 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
436 break;
437 case 9600000:
438 case 28800000:
439
440
441
442 cfreq = parent_rate/(parent_rate/1000000);
443 break;
444 default:
445 pr_err("%s Unexpected reference rate %lu\n",
446 __func__, parent_rate);
447 BUG();
448 }
449
450
451 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
452 cfg->output_rate <<= 1)
453 p_div++;
454
455 cfg->m = parent_rate / cfreq;
456 cfg->n = cfg->output_rate / cfreq;
457 cfg->cpcon = OUT_OF_TABLE_CPCON;
458
459 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
460 (1 << p_div) > divp_max(pll)
461 || cfg->output_rate > pll->params->vco_max) {
462 return -EINVAL;
463 }
464
465 cfg->output_rate >>= p_div;
466
467 if (pll->params->pdiv_tohw) {
468 ret = _p_div_to_hw(hw, 1 << p_div);
469 if (ret < 0)
470 return ret;
471 else
472 cfg->p = ret;
473 } else
474 cfg->p = p_div;
475
476 return 0;
477}
478
479static void _update_pll_mnp(struct tegra_clk_pll *pll,
480 struct tegra_clk_pll_freq_table *cfg)
481{
482 u32 val;
483 struct tegra_clk_pll_params *params = pll->params;
484 struct div_nmp *div_nmp = params->div_nmp;
485
486 if ((params->flags & TEGRA_PLLM) &&
487 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
488 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
489 val = pll_override_readl(params->pmc_divp_reg, pll);
490 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
491 val |= cfg->p << div_nmp->override_divp_shift;
492 pll_override_writel(val, params->pmc_divp_reg, pll);
493
494 val = pll_override_readl(params->pmc_divnm_reg, pll);
495 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
496 ~(divn_mask(pll) << div_nmp->override_divn_shift);
497 val |= (cfg->m << div_nmp->override_divm_shift) |
498 (cfg->n << div_nmp->override_divn_shift);
499 pll_override_writel(val, params->pmc_divnm_reg, pll);
500 } else {
501 val = pll_readl_base(pll);
502
503 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
504 divp_mask_shifted(pll));
505
506 val |= (cfg->m << divm_shift(pll)) |
507 (cfg->n << divn_shift(pll)) |
508 (cfg->p << divp_shift(pll));
509
510 pll_writel_base(val, pll);
511 }
512}
513
514static void _get_pll_mnp(struct tegra_clk_pll *pll,
515 struct tegra_clk_pll_freq_table *cfg)
516{
517 u32 val;
518 struct tegra_clk_pll_params *params = pll->params;
519 struct div_nmp *div_nmp = params->div_nmp;
520
521 if ((params->flags & TEGRA_PLLM) &&
522 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
523 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
524 val = pll_override_readl(params->pmc_divp_reg, pll);
525 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
526
527 val = pll_override_readl(params->pmc_divnm_reg, pll);
528 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
529 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
530 } else {
531 val = pll_readl_base(pll);
532
533 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
534 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
535 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
536 }
537}
538
539static void _update_pll_cpcon(struct tegra_clk_pll *pll,
540 struct tegra_clk_pll_freq_table *cfg,
541 unsigned long rate)
542{
543 u32 val;
544
545 val = pll_readl_misc(pll);
546
547 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
548 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
549
550 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
551 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
552 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
553 val |= 1 << PLL_MISC_LFCON_SHIFT;
554 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
555 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
556 if (rate >= (pll->params->vco_max >> 1))
557 val |= 1 << PLL_MISC_DCCON_SHIFT;
558 }
559
560 pll_writel_misc(val, pll);
561}
562
563static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
564 unsigned long rate)
565{
566 struct tegra_clk_pll *pll = to_clk_pll(hw);
567 int state, ret = 0;
568
569 state = clk_pll_is_enabled(hw);
570
571 if (state)
572 _clk_pll_disable(hw);
573
574 _update_pll_mnp(pll, cfg);
575
576 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
577 _update_pll_cpcon(pll, cfg, rate);
578
579 if (state) {
580 _clk_pll_enable(hw);
581 ret = clk_pll_wait_for_lock(pll);
582 }
583
584 return ret;
585}
586
587static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
588 unsigned long parent_rate)
589{
590 struct tegra_clk_pll *pll = to_clk_pll(hw);
591 struct tegra_clk_pll_freq_table cfg, old_cfg;
592 unsigned long flags = 0;
593 int ret = 0;
594
595 if (pll->params->flags & TEGRA_PLL_FIXED) {
596 if (rate != pll->params->fixed_rate) {
597 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
598 __func__, clk_hw_get_name(hw),
599 pll->params->fixed_rate, rate);
600 return -EINVAL;
601 }
602 return 0;
603 }
604
605 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
606 _calc_rate(hw, &cfg, rate, parent_rate)) {
607 pr_err("%s: Failed to set %s rate %lu\n", __func__,
608 clk_hw_get_name(hw), rate);
609 WARN_ON(1);
610 return -EINVAL;
611 }
612 if (pll->lock)
613 spin_lock_irqsave(pll->lock, flags);
614
615 _get_pll_mnp(pll, &old_cfg);
616
617 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
618 ret = _program_pll(hw, &cfg, rate);
619
620 if (pll->lock)
621 spin_unlock_irqrestore(pll->lock, flags);
622
623 return ret;
624}
625
626static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
627 unsigned long *prate)
628{
629 struct tegra_clk_pll *pll = to_clk_pll(hw);
630 struct tegra_clk_pll_freq_table cfg;
631
632 if (pll->params->flags & TEGRA_PLL_FIXED)
633 return pll->params->fixed_rate;
634
635
636 if (pll->params->flags & TEGRA_PLLM)
637 return clk_hw_get_rate(hw);
638
639 if (_get_table_rate(hw, &cfg, rate, *prate) &&
640 _calc_rate(hw, &cfg, rate, *prate))
641 return -EINVAL;
642
643 return cfg.output_rate;
644}
645
646static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
647 unsigned long parent_rate)
648{
649 struct tegra_clk_pll *pll = to_clk_pll(hw);
650 struct tegra_clk_pll_freq_table cfg;
651 u32 val;
652 u64 rate = parent_rate;
653 int pdiv;
654
655 val = pll_readl_base(pll);
656
657 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
658 return parent_rate;
659
660 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
661 !(val & PLL_BASE_OVERRIDE)) {
662 struct tegra_clk_pll_freq_table sel;
663 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
664 parent_rate)) {
665 pr_err("Clock %s has unknown fixed frequency\n",
666 clk_hw_get_name(hw));
667 BUG();
668 }
669 return pll->params->fixed_rate;
670 }
671
672 _get_pll_mnp(pll, &cfg);
673
674 pdiv = _hw_to_p_div(hw, cfg.p);
675 if (pdiv < 0) {
676 WARN_ON(1);
677 pdiv = 1;
678 }
679
680 cfg.m *= pdiv;
681
682 rate *= cfg.n;
683 do_div(rate, cfg.m);
684
685 return rate;
686}
687
688static int clk_plle_training(struct tegra_clk_pll *pll)
689{
690 u32 val;
691 unsigned long timeout;
692
693 if (!pll->pmc)
694 return -ENOSYS;
695
696
697
698
699
700 val = readl(pll->pmc + PMC_SATA_PWRGT);
701 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
702 writel(val, pll->pmc + PMC_SATA_PWRGT);
703
704 val = readl(pll->pmc + PMC_SATA_PWRGT);
705 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
706 writel(val, pll->pmc + PMC_SATA_PWRGT);
707
708 val = readl(pll->pmc + PMC_SATA_PWRGT);
709 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
710 writel(val, pll->pmc + PMC_SATA_PWRGT);
711
712 val = pll_readl_misc(pll);
713
714 timeout = jiffies + msecs_to_jiffies(100);
715 while (1) {
716 val = pll_readl_misc(pll);
717 if (val & PLLE_MISC_READY)
718 break;
719 if (time_after(jiffies, timeout)) {
720 pr_err("%s: timeout waiting for PLLE\n", __func__);
721 return -EBUSY;
722 }
723 udelay(300);
724 }
725
726 return 0;
727}
728
729static int clk_plle_enable(struct clk_hw *hw)
730{
731 struct tegra_clk_pll *pll = to_clk_pll(hw);
732 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
733 struct tegra_clk_pll_freq_table sel;
734 u32 val;
735 int err;
736
737 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
738 return -EINVAL;
739
740 clk_pll_disable(hw);
741
742 val = pll_readl_misc(pll);
743 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
744 pll_writel_misc(val, pll);
745
746 val = pll_readl_misc(pll);
747 if (!(val & PLLE_MISC_READY)) {
748 err = clk_plle_training(pll);
749 if (err)
750 return err;
751 }
752
753 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
754
755 val = pll_readl_base(pll);
756 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
757 divm_mask_shifted(pll));
758 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
759 val |= sel.m << divm_shift(pll);
760 val |= sel.n << divn_shift(pll);
761 val |= sel.p << divp_shift(pll);
762 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
763 pll_writel_base(val, pll);
764 }
765
766 val = pll_readl_misc(pll);
767 val |= PLLE_MISC_SETUP_VALUE;
768 val |= PLLE_MISC_LOCK_ENABLE;
769 pll_writel_misc(val, pll);
770
771 val = readl(pll->clk_base + PLLE_SS_CTRL);
772 val &= ~PLLE_SS_COEFFICIENTS_MASK;
773 val |= PLLE_SS_DISABLE;
774 writel(val, pll->clk_base + PLLE_SS_CTRL);
775
776 val = pll_readl_base(pll);
777 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
778 pll_writel_base(val, pll);
779
780 clk_pll_wait_for_lock(pll);
781
782 return 0;
783}
784
785static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
786 unsigned long parent_rate)
787{
788 struct tegra_clk_pll *pll = to_clk_pll(hw);
789 u32 val = pll_readl_base(pll);
790 u32 divn = 0, divm = 0, divp = 0;
791 u64 rate = parent_rate;
792
793 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
794 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
795 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
796 divm *= divp;
797
798 rate *= divn;
799 do_div(rate, divm);
800 return rate;
801}
802
803const struct clk_ops tegra_clk_pll_ops = {
804 .is_enabled = clk_pll_is_enabled,
805 .enable = clk_pll_enable,
806 .disable = clk_pll_disable,
807 .recalc_rate = clk_pll_recalc_rate,
808 .round_rate = clk_pll_round_rate,
809 .set_rate = clk_pll_set_rate,
810};
811
812const struct clk_ops tegra_clk_plle_ops = {
813 .recalc_rate = clk_plle_recalc_rate,
814 .is_enabled = clk_pll_is_enabled,
815 .disable = clk_pll_disable,
816 .enable = clk_plle_enable,
817};
818
819#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
820 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
821 defined(CONFIG_ARCH_TEGRA_132_SOC)
822
823static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
824 unsigned long parent_rate)
825{
826 if (parent_rate > pll_params->cf_max)
827 return 2;
828 else
829 return 1;
830}
831
832static unsigned long _clip_vco_min(unsigned long vco_min,
833 unsigned long parent_rate)
834{
835 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
836}
837
838static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
839 void __iomem *clk_base,
840 unsigned long parent_rate)
841{
842 u32 val;
843 u32 step_a, step_b;
844
845 switch (parent_rate) {
846 case 12000000:
847 case 13000000:
848 case 26000000:
849 step_a = 0x2B;
850 step_b = 0x0B;
851 break;
852 case 16800000:
853 step_a = 0x1A;
854 step_b = 0x09;
855 break;
856 case 19200000:
857 step_a = 0x12;
858 step_b = 0x08;
859 break;
860 default:
861 pr_err("%s: Unexpected reference rate %lu\n",
862 __func__, parent_rate);
863 WARN_ON(1);
864 return -EINVAL;
865 }
866
867 val = step_a << pll_params->stepa_shift;
868 val |= step_b << pll_params->stepb_shift;
869 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
870
871 return 0;
872}
873
874static int clk_pll_iddq_enable(struct clk_hw *hw)
875{
876 struct tegra_clk_pll *pll = to_clk_pll(hw);
877 unsigned long flags = 0;
878
879 u32 val;
880 int ret;
881
882 if (pll->lock)
883 spin_lock_irqsave(pll->lock, flags);
884
885 val = pll_readl(pll->params->iddq_reg, pll);
886 val &= ~BIT(pll->params->iddq_bit_idx);
887 pll_writel(val, pll->params->iddq_reg, pll);
888 udelay(2);
889
890 _clk_pll_enable(hw);
891
892 ret = clk_pll_wait_for_lock(pll);
893
894 if (pll->lock)
895 spin_unlock_irqrestore(pll->lock, flags);
896
897 return 0;
898}
899
900static void clk_pll_iddq_disable(struct clk_hw *hw)
901{
902 struct tegra_clk_pll *pll = to_clk_pll(hw);
903 unsigned long flags = 0;
904 u32 val;
905
906 if (pll->lock)
907 spin_lock_irqsave(pll->lock, flags);
908
909 _clk_pll_disable(hw);
910
911 val = pll_readl(pll->params->iddq_reg, pll);
912 val |= BIT(pll->params->iddq_bit_idx);
913 pll_writel(val, pll->params->iddq_reg, pll);
914 udelay(2);
915
916 if (pll->lock)
917 spin_unlock_irqrestore(pll->lock, flags);
918}
919
920static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
921 struct tegra_clk_pll_freq_table *cfg,
922 unsigned long rate, unsigned long parent_rate)
923{
924 struct tegra_clk_pll *pll = to_clk_pll(hw);
925 unsigned int p;
926 int p_div;
927
928 if (!rate)
929 return -EINVAL;
930
931 p = DIV_ROUND_UP(pll->params->vco_min, rate);
932 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
933 cfg->output_rate = rate * p;
934 cfg->n = cfg->output_rate * cfg->m / parent_rate;
935
936 p_div = _p_div_to_hw(hw, p);
937 if (p_div < 0)
938 return p_div;
939 else
940 cfg->p = p_div;
941
942 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
943 return -EINVAL;
944
945 return 0;
946}
947
948static int _pll_ramp_calc_pll(struct clk_hw *hw,
949 struct tegra_clk_pll_freq_table *cfg,
950 unsigned long rate, unsigned long parent_rate)
951{
952 struct tegra_clk_pll *pll = to_clk_pll(hw);
953 int err = 0, p_div;
954
955 err = _get_table_rate(hw, cfg, rate, parent_rate);
956 if (err < 0)
957 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
958 else {
959 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
960 WARN_ON(1);
961 err = -EINVAL;
962 goto out;
963 }
964 p_div = _p_div_to_hw(hw, cfg->p);
965 if (p_div < 0)
966 return p_div;
967 else
968 cfg->p = p_div;
969 }
970
971 if (cfg->p > pll->params->max_p)
972 err = -EINVAL;
973
974out:
975 return err;
976}
977
978static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
979 unsigned long parent_rate)
980{
981 struct tegra_clk_pll *pll = to_clk_pll(hw);
982 struct tegra_clk_pll_freq_table cfg, old_cfg;
983 unsigned long flags = 0;
984 int ret;
985
986 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
987 if (ret < 0)
988 return ret;
989
990 if (pll->lock)
991 spin_lock_irqsave(pll->lock, flags);
992
993 _get_pll_mnp(pll, &old_cfg);
994
995 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
996 ret = _program_pll(hw, &cfg, rate);
997
998 if (pll->lock)
999 spin_unlock_irqrestore(pll->lock, flags);
1000
1001 return ret;
1002}
1003
1004static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1005 unsigned long *prate)
1006{
1007 struct tegra_clk_pll_freq_table cfg;
1008 int ret, p_div;
1009 u64 output_rate = *prate;
1010
1011 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1012 if (ret < 0)
1013 return ret;
1014
1015 p_div = _hw_to_p_div(hw, cfg.p);
1016 if (p_div < 0)
1017 return p_div;
1018
1019 output_rate *= cfg.n;
1020 do_div(output_rate, cfg.m * p_div);
1021
1022 return output_rate;
1023}
1024
1025static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
1026 unsigned long parent_rate)
1027{
1028 struct tegra_clk_pll_freq_table cfg;
1029 struct tegra_clk_pll *pll = to_clk_pll(hw);
1030 unsigned long flags = 0;
1031 int state, ret = 0;
1032
1033 if (pll->lock)
1034 spin_lock_irqsave(pll->lock, flags);
1035
1036 state = clk_pll_is_enabled(hw);
1037 if (state) {
1038 if (rate != clk_get_rate(hw->clk)) {
1039 pr_err("%s: Cannot change active PLLM\n", __func__);
1040 ret = -EINVAL;
1041 goto out;
1042 }
1043 goto out;
1044 }
1045
1046 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1047 if (ret < 0)
1048 goto out;
1049
1050 _update_pll_mnp(pll, &cfg);
1051
1052out:
1053 if (pll->lock)
1054 spin_unlock_irqrestore(pll->lock, flags);
1055
1056 return ret;
1057}
1058
1059static void _pllcx_strobe(struct tegra_clk_pll *pll)
1060{
1061 u32 val;
1062
1063 val = pll_readl_misc(pll);
1064 val |= PLLCX_MISC_STROBE;
1065 pll_writel_misc(val, pll);
1066 udelay(2);
1067
1068 val &= ~PLLCX_MISC_STROBE;
1069 pll_writel_misc(val, pll);
1070}
1071
1072static int clk_pllc_enable(struct clk_hw *hw)
1073{
1074 struct tegra_clk_pll *pll = to_clk_pll(hw);
1075 u32 val;
1076 int ret;
1077 unsigned long flags = 0;
1078
1079 if (pll->lock)
1080 spin_lock_irqsave(pll->lock, flags);
1081
1082 _clk_pll_enable(hw);
1083 udelay(2);
1084
1085 val = pll_readl_misc(pll);
1086 val &= ~PLLCX_MISC_RESET;
1087 pll_writel_misc(val, pll);
1088 udelay(2);
1089
1090 _pllcx_strobe(pll);
1091
1092 ret = clk_pll_wait_for_lock(pll);
1093
1094 if (pll->lock)
1095 spin_unlock_irqrestore(pll->lock, flags);
1096
1097 return ret;
1098}
1099
1100static void _clk_pllc_disable(struct clk_hw *hw)
1101{
1102 struct tegra_clk_pll *pll = to_clk_pll(hw);
1103 u32 val;
1104
1105 _clk_pll_disable(hw);
1106
1107 val = pll_readl_misc(pll);
1108 val |= PLLCX_MISC_RESET;
1109 pll_writel_misc(val, pll);
1110 udelay(2);
1111}
1112
1113static void clk_pllc_disable(struct clk_hw *hw)
1114{
1115 struct tegra_clk_pll *pll = to_clk_pll(hw);
1116 unsigned long flags = 0;
1117
1118 if (pll->lock)
1119 spin_lock_irqsave(pll->lock, flags);
1120
1121 _clk_pllc_disable(hw);
1122
1123 if (pll->lock)
1124 spin_unlock_irqrestore(pll->lock, flags);
1125}
1126
1127static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1128 unsigned long input_rate, u32 n)
1129{
1130 u32 val, n_threshold;
1131
1132 switch (input_rate) {
1133 case 12000000:
1134 n_threshold = 70;
1135 break;
1136 case 13000000:
1137 case 26000000:
1138 n_threshold = 71;
1139 break;
1140 case 16800000:
1141 n_threshold = 55;
1142 break;
1143 case 19200000:
1144 n_threshold = 48;
1145 break;
1146 default:
1147 pr_err("%s: Unexpected reference rate %lu\n",
1148 __func__, input_rate);
1149 return -EINVAL;
1150 }
1151
1152 val = pll_readl_misc(pll);
1153 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1154 val |= n <= n_threshold ?
1155 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1156 pll_writel_misc(val, pll);
1157
1158 return 0;
1159}
1160
1161static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1162 unsigned long parent_rate)
1163{
1164 struct tegra_clk_pll_freq_table cfg, old_cfg;
1165 struct tegra_clk_pll *pll = to_clk_pll(hw);
1166 unsigned long flags = 0;
1167 int state, ret = 0;
1168
1169 if (pll->lock)
1170 spin_lock_irqsave(pll->lock, flags);
1171
1172 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1173 if (ret < 0)
1174 goto out;
1175
1176 _get_pll_mnp(pll, &old_cfg);
1177
1178 if (cfg.m != old_cfg.m) {
1179 WARN_ON(1);
1180 goto out;
1181 }
1182
1183 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1184 goto out;
1185
1186 state = clk_pll_is_enabled(hw);
1187 if (state)
1188 _clk_pllc_disable(hw);
1189
1190 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1191 if (ret < 0)
1192 goto out;
1193
1194 _update_pll_mnp(pll, &cfg);
1195
1196 if (state)
1197 ret = clk_pllc_enable(hw);
1198
1199out:
1200 if (pll->lock)
1201 spin_unlock_irqrestore(pll->lock, flags);
1202
1203 return ret;
1204}
1205
1206static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1207 struct tegra_clk_pll_freq_table *cfg,
1208 unsigned long rate, unsigned long parent_rate)
1209{
1210 u16 m, n;
1211 u64 output_rate = parent_rate;
1212
1213 m = _pll_fixed_mdiv(pll->params, parent_rate);
1214 n = rate * m / parent_rate;
1215
1216 output_rate *= n;
1217 do_div(output_rate, m);
1218
1219 if (cfg) {
1220 cfg->m = m;
1221 cfg->n = n;
1222 }
1223
1224 return output_rate;
1225}
1226
1227static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1228 unsigned long parent_rate)
1229{
1230 struct tegra_clk_pll_freq_table cfg, old_cfg;
1231 struct tegra_clk_pll *pll = to_clk_pll(hw);
1232 unsigned long flags = 0;
1233 int state, ret = 0;
1234
1235 if (pll->lock)
1236 spin_lock_irqsave(pll->lock, flags);
1237
1238 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1239 _get_pll_mnp(pll, &old_cfg);
1240 cfg.p = old_cfg.p;
1241
1242 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1243 state = clk_pll_is_enabled(hw);
1244 if (state)
1245 _clk_pll_disable(hw);
1246
1247 _update_pll_mnp(pll, &cfg);
1248
1249 if (state) {
1250 _clk_pll_enable(hw);
1251 ret = clk_pll_wait_for_lock(pll);
1252 }
1253 }
1254
1255 if (pll->lock)
1256 spin_unlock_irqrestore(pll->lock, flags);
1257
1258 return ret;
1259}
1260
1261static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1262 unsigned long parent_rate)
1263{
1264 struct tegra_clk_pll_freq_table cfg;
1265 struct tegra_clk_pll *pll = to_clk_pll(hw);
1266 u64 rate = parent_rate;
1267
1268 _get_pll_mnp(pll, &cfg);
1269
1270 rate *= cfg.n;
1271 do_div(rate, cfg.m);
1272
1273 return rate;
1274}
1275
1276static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1277 unsigned long *prate)
1278{
1279 struct tegra_clk_pll *pll = to_clk_pll(hw);
1280
1281 return _pllre_calc_rate(pll, NULL, rate, *prate);
1282}
1283
1284static int clk_plle_tegra114_enable(struct clk_hw *hw)
1285{
1286 struct tegra_clk_pll *pll = to_clk_pll(hw);
1287 struct tegra_clk_pll_freq_table sel;
1288 u32 val;
1289 int ret;
1290 unsigned long flags = 0;
1291 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1292
1293 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1294 return -EINVAL;
1295
1296 if (pll->lock)
1297 spin_lock_irqsave(pll->lock, flags);
1298
1299 val = pll_readl_base(pll);
1300 val &= ~BIT(29);
1301 pll_writel_base(val, pll);
1302
1303 val = pll_readl(pll->params->aux_reg, pll);
1304 val |= PLLE_AUX_ENABLE_SWCTL;
1305 val &= ~PLLE_AUX_SEQ_ENABLE;
1306 pll_writel(val, pll->params->aux_reg, pll);
1307 udelay(1);
1308
1309 val = pll_readl_misc(pll);
1310 val |= PLLE_MISC_LOCK_ENABLE;
1311 val |= PLLE_MISC_IDDQ_SW_CTRL;
1312 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1313 val |= PLLE_MISC_PLLE_PTS;
1314 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1315 pll_writel_misc(val, pll);
1316 udelay(5);
1317
1318 val = pll_readl(PLLE_SS_CTRL, pll);
1319 val |= PLLE_SS_DISABLE;
1320 pll_writel(val, PLLE_SS_CTRL, pll);
1321
1322 val = pll_readl_base(pll);
1323 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1324 divm_mask_shifted(pll));
1325 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1326 val |= sel.m << divm_shift(pll);
1327 val |= sel.n << divn_shift(pll);
1328 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1329 pll_writel_base(val, pll);
1330 udelay(1);
1331
1332 _clk_pll_enable(hw);
1333 ret = clk_pll_wait_for_lock(pll);
1334
1335 if (ret < 0)
1336 goto out;
1337
1338 val = pll_readl(PLLE_SS_CTRL, pll);
1339 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1340 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1341 val |= PLLE_SS_COEFFICIENTS_VAL;
1342 pll_writel(val, PLLE_SS_CTRL, pll);
1343 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1344 pll_writel(val, PLLE_SS_CTRL, pll);
1345 udelay(1);
1346 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1347 pll_writel(val, PLLE_SS_CTRL, pll);
1348 udelay(1);
1349
1350
1351 val = pll_readl_misc(pll);
1352 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1353 pll_writel_misc(val, pll);
1354
1355 val = pll_readl(pll->params->aux_reg, pll);
1356 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1357 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1358 pll_writel(val, pll->params->aux_reg, pll);
1359 udelay(1);
1360 val |= PLLE_AUX_SEQ_ENABLE;
1361 pll_writel(val, pll->params->aux_reg, pll);
1362
1363 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1364 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1365 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1366 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1367 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1368 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1369 udelay(1);
1370 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1371 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1372
1373
1374 val = pll_readl(SATA_PLL_CFG0, pll);
1375 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1376 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1377 val |= SATA_PLL_CFG0_SEQ_START_STATE;
1378 pll_writel(val, SATA_PLL_CFG0, pll);
1379
1380 udelay(1);
1381
1382 val = pll_readl(SATA_PLL_CFG0, pll);
1383 val |= SATA_PLL_CFG0_SEQ_ENABLE;
1384 pll_writel(val, SATA_PLL_CFG0, pll);
1385
1386out:
1387 if (pll->lock)
1388 spin_unlock_irqrestore(pll->lock, flags);
1389
1390 return ret;
1391}
1392
1393static void clk_plle_tegra114_disable(struct clk_hw *hw)
1394{
1395 struct tegra_clk_pll *pll = to_clk_pll(hw);
1396 unsigned long flags = 0;
1397 u32 val;
1398
1399 if (pll->lock)
1400 spin_lock_irqsave(pll->lock, flags);
1401
1402 _clk_pll_disable(hw);
1403
1404 val = pll_readl_misc(pll);
1405 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1406 pll_writel_misc(val, pll);
1407 udelay(1);
1408
1409 if (pll->lock)
1410 spin_unlock_irqrestore(pll->lock, flags);
1411}
1412#endif
1413
1414static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1415 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1416 spinlock_t *lock)
1417{
1418 struct tegra_clk_pll *pll;
1419
1420 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1421 if (!pll)
1422 return ERR_PTR(-ENOMEM);
1423
1424 pll->clk_base = clk_base;
1425 pll->pmc = pmc;
1426
1427 pll->params = pll_params;
1428 pll->lock = lock;
1429
1430 if (!pll_params->div_nmp)
1431 pll_params->div_nmp = &default_nmp;
1432
1433 return pll;
1434}
1435
1436static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1437 const char *name, const char *parent_name, unsigned long flags,
1438 const struct clk_ops *ops)
1439{
1440 struct clk_init_data init;
1441
1442 init.name = name;
1443 init.ops = ops;
1444 init.flags = flags;
1445 init.parent_names = (parent_name ? &parent_name : NULL);
1446 init.num_parents = (parent_name ? 1 : 0);
1447
1448
1449 pll->hw.init = &init;
1450
1451 return clk_register(NULL, &pll->hw);
1452}
1453
1454struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1455 void __iomem *clk_base, void __iomem *pmc,
1456 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1457 spinlock_t *lock)
1458{
1459 struct tegra_clk_pll *pll;
1460 struct clk *clk;
1461
1462 pll_params->flags |= TEGRA_PLL_BYPASS;
1463 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1464 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1465 if (IS_ERR(pll))
1466 return ERR_CAST(pll);
1467
1468 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1469 &tegra_clk_pll_ops);
1470 if (IS_ERR(clk))
1471 kfree(pll);
1472
1473 return clk;
1474}
1475
1476static struct div_nmp pll_e_nmp = {
1477 .divn_shift = PLLE_BASE_DIVN_SHIFT,
1478 .divn_width = PLLE_BASE_DIVN_WIDTH,
1479 .divm_shift = PLLE_BASE_DIVM_SHIFT,
1480 .divm_width = PLLE_BASE_DIVM_WIDTH,
1481 .divp_shift = PLLE_BASE_DIVP_SHIFT,
1482 .divp_width = PLLE_BASE_DIVP_WIDTH,
1483};
1484
1485struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1486 void __iomem *clk_base, void __iomem *pmc,
1487 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1488 spinlock_t *lock)
1489{
1490 struct tegra_clk_pll *pll;
1491 struct clk *clk;
1492
1493 pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1494 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1495
1496 if (!pll_params->div_nmp)
1497 pll_params->div_nmp = &pll_e_nmp;
1498
1499 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1500 if (IS_ERR(pll))
1501 return ERR_CAST(pll);
1502
1503 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1504 &tegra_clk_plle_ops);
1505 if (IS_ERR(clk))
1506 kfree(pll);
1507
1508 return clk;
1509}
1510
1511#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1512 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1513 defined(CONFIG_ARCH_TEGRA_132_SOC)
1514static const struct clk_ops tegra_clk_pllxc_ops = {
1515 .is_enabled = clk_pll_is_enabled,
1516 .enable = clk_pll_iddq_enable,
1517 .disable = clk_pll_iddq_disable,
1518 .recalc_rate = clk_pll_recalc_rate,
1519 .round_rate = clk_pll_ramp_round_rate,
1520 .set_rate = clk_pllxc_set_rate,
1521};
1522
1523static const struct clk_ops tegra_clk_pllm_ops = {
1524 .is_enabled = clk_pll_is_enabled,
1525 .enable = clk_pll_iddq_enable,
1526 .disable = clk_pll_iddq_disable,
1527 .recalc_rate = clk_pll_recalc_rate,
1528 .round_rate = clk_pll_ramp_round_rate,
1529 .set_rate = clk_pllm_set_rate,
1530};
1531
1532static const struct clk_ops tegra_clk_pllc_ops = {
1533 .is_enabled = clk_pll_is_enabled,
1534 .enable = clk_pllc_enable,
1535 .disable = clk_pllc_disable,
1536 .recalc_rate = clk_pll_recalc_rate,
1537 .round_rate = clk_pll_ramp_round_rate,
1538 .set_rate = clk_pllc_set_rate,
1539};
1540
1541static const struct clk_ops tegra_clk_pllre_ops = {
1542 .is_enabled = clk_pll_is_enabled,
1543 .enable = clk_pll_iddq_enable,
1544 .disable = clk_pll_iddq_disable,
1545 .recalc_rate = clk_pllre_recalc_rate,
1546 .round_rate = clk_pllre_round_rate,
1547 .set_rate = clk_pllre_set_rate,
1548};
1549
1550static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1551 .is_enabled = clk_pll_is_enabled,
1552 .enable = clk_plle_tegra114_enable,
1553 .disable = clk_plle_tegra114_disable,
1554 .recalc_rate = clk_pll_recalc_rate,
1555};
1556
1557
1558struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1559 void __iomem *clk_base, void __iomem *pmc,
1560 unsigned long flags,
1561 struct tegra_clk_pll_params *pll_params,
1562 spinlock_t *lock)
1563{
1564 struct tegra_clk_pll *pll;
1565 struct clk *clk, *parent;
1566 unsigned long parent_rate;
1567 int err;
1568 u32 val, val_iddq;
1569
1570 parent = __clk_lookup(parent_name);
1571 if (!parent) {
1572 WARN(1, "parent clk %s of %s must be registered first\n",
1573 parent_name, name);
1574 return ERR_PTR(-EINVAL);
1575 }
1576
1577 if (!pll_params->pdiv_tohw)
1578 return ERR_PTR(-EINVAL);
1579
1580 parent_rate = clk_get_rate(parent);
1581
1582 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1583
1584 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
1585 if (err)
1586 return ERR_PTR(err);
1587
1588 val = readl_relaxed(clk_base + pll_params->base_reg);
1589 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1590
1591 if (val & PLL_BASE_ENABLE)
1592 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1593 else {
1594 val_iddq |= BIT(pll_params->iddq_bit_idx);
1595 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1596 }
1597
1598 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1599 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1600 if (IS_ERR(pll))
1601 return ERR_CAST(pll);
1602
1603 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1604 &tegra_clk_pllxc_ops);
1605 if (IS_ERR(clk))
1606 kfree(pll);
1607
1608 return clk;
1609}
1610
1611struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1612 void __iomem *clk_base, void __iomem *pmc,
1613 unsigned long flags,
1614 struct tegra_clk_pll_params *pll_params,
1615 spinlock_t *lock, unsigned long parent_rate)
1616{
1617 u32 val;
1618 struct tegra_clk_pll *pll;
1619 struct clk *clk;
1620
1621 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
1622
1623 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1624
1625 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1626 if (IS_ERR(pll))
1627 return ERR_CAST(pll);
1628
1629
1630
1631 val = pll_readl_base(pll);
1632 if (val & PLL_BASE_ENABLE)
1633 WARN_ON(val & pll_params->iddq_bit_idx);
1634 else {
1635 int m;
1636
1637 m = _pll_fixed_mdiv(pll_params, parent_rate);
1638 val = m << divm_shift(pll);
1639 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
1640 pll_writel_base(val, pll);
1641 }
1642
1643
1644
1645 val = pll_readl_misc(pll);
1646 val &= ~BIT(29);
1647 pll_writel_misc(val, pll);
1648
1649 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1650 &tegra_clk_pllre_ops);
1651 if (IS_ERR(clk))
1652 kfree(pll);
1653
1654 return clk;
1655}
1656
1657struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1658 void __iomem *clk_base, void __iomem *pmc,
1659 unsigned long flags,
1660 struct tegra_clk_pll_params *pll_params,
1661 spinlock_t *lock)
1662{
1663 struct tegra_clk_pll *pll;
1664 struct clk *clk, *parent;
1665 unsigned long parent_rate;
1666
1667 if (!pll_params->pdiv_tohw)
1668 return ERR_PTR(-EINVAL);
1669
1670 parent = __clk_lookup(parent_name);
1671 if (!parent) {
1672 WARN(1, "parent clk %s of %s must be registered first\n",
1673 parent_name, name);
1674 return ERR_PTR(-EINVAL);
1675 }
1676
1677 parent_rate = clk_get_rate(parent);
1678
1679 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1680
1681 pll_params->flags |= TEGRA_PLL_BYPASS;
1682 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1683 pll_params->flags |= TEGRA_PLLM;
1684 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1685 if (IS_ERR(pll))
1686 return ERR_CAST(pll);
1687
1688 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1689 &tegra_clk_pllm_ops);
1690 if (IS_ERR(clk))
1691 kfree(pll);
1692
1693 return clk;
1694}
1695
1696struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1697 void __iomem *clk_base, void __iomem *pmc,
1698 unsigned long flags,
1699 struct tegra_clk_pll_params *pll_params,
1700 spinlock_t *lock)
1701{
1702 struct clk *parent, *clk;
1703 struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1704 struct tegra_clk_pll *pll;
1705 struct tegra_clk_pll_freq_table cfg;
1706 unsigned long parent_rate;
1707
1708 if (!p_tohw)
1709 return ERR_PTR(-EINVAL);
1710
1711 parent = __clk_lookup(parent_name);
1712 if (!parent) {
1713 WARN(1, "parent clk %s of %s must be registered first\n",
1714 parent_name, name);
1715 return ERR_PTR(-EINVAL);
1716 }
1717
1718 parent_rate = clk_get_rate(parent);
1719
1720 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1721
1722 pll_params->flags |= TEGRA_PLL_BYPASS;
1723 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1724 if (IS_ERR(pll))
1725 return ERR_CAST(pll);
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1737 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1738
1739 while (p_tohw->pdiv) {
1740 if (p_tohw->pdiv == 2) {
1741 cfg.p = p_tohw->hw_val;
1742 break;
1743 }
1744 p_tohw++;
1745 }
1746
1747 if (!p_tohw->pdiv) {
1748 WARN_ON(1);
1749 return ERR_PTR(-EINVAL);
1750 }
1751
1752 pll_writel_base(0, pll);
1753 _update_pll_mnp(pll, &cfg);
1754
1755 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1756 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1757 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1758 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1759
1760 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1761
1762 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1763 &tegra_clk_pllc_ops);
1764 if (IS_ERR(clk))
1765 kfree(pll);
1766
1767 return clk;
1768}
1769
1770struct clk *tegra_clk_register_plle_tegra114(const char *name,
1771 const char *parent_name,
1772 void __iomem *clk_base, unsigned long flags,
1773 struct tegra_clk_pll_params *pll_params,
1774 spinlock_t *lock)
1775{
1776 struct tegra_clk_pll *pll;
1777 struct clk *clk;
1778 u32 val, val_aux;
1779
1780 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1781 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1782 if (IS_ERR(pll))
1783 return ERR_CAST(pll);
1784
1785
1786
1787 val = pll_readl_base(pll);
1788 val_aux = pll_readl(pll_params->aux_reg, pll);
1789
1790 if (val & PLL_BASE_ENABLE) {
1791 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1792 (val_aux & PLLE_AUX_PLLP_SEL))
1793 WARN(1, "pll_e enabled with unsupported parent %s\n",
1794 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1795 "pll_re_vco");
1796 } else {
1797 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1798 pll_writel(val_aux, pll_params->aux_reg, pll);
1799 }
1800
1801 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1802 &tegra_clk_plle_tegra114_ops);
1803 if (IS_ERR(clk))
1804 kfree(pll);
1805
1806 return clk;
1807}
1808#endif
1809
1810#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
1811static const struct clk_ops tegra_clk_pllss_ops = {
1812 .is_enabled = clk_pll_is_enabled,
1813 .enable = clk_pll_iddq_enable,
1814 .disable = clk_pll_iddq_disable,
1815 .recalc_rate = clk_pll_recalc_rate,
1816 .round_rate = clk_pll_ramp_round_rate,
1817 .set_rate = clk_pllxc_set_rate,
1818};
1819
1820struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1821 void __iomem *clk_base, unsigned long flags,
1822 struct tegra_clk_pll_params *pll_params,
1823 spinlock_t *lock)
1824{
1825 struct tegra_clk_pll *pll;
1826 struct clk *clk, *parent;
1827 struct tegra_clk_pll_freq_table cfg;
1828 unsigned long parent_rate;
1829 u32 val;
1830 int i;
1831
1832 if (!pll_params->div_nmp)
1833 return ERR_PTR(-EINVAL);
1834
1835 parent = __clk_lookup(parent_name);
1836 if (!parent) {
1837 WARN(1, "parent clk %s of %s must be registered first\n",
1838 parent_name, name);
1839 return ERR_PTR(-EINVAL);
1840 }
1841
1842 pll_params->flags = TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_USE_LOCK;
1843 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1844 if (IS_ERR(pll))
1845 return ERR_CAST(pll);
1846
1847 val = pll_readl_base(pll);
1848 val &= ~PLLSS_REF_SRC_SEL_MASK;
1849 pll_writel_base(val, pll);
1850
1851 parent_rate = clk_get_rate(parent);
1852
1853 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1854
1855
1856
1857 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1858 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1859
1860 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
1861 ;
1862 if (!i) {
1863 kfree(pll);
1864 return ERR_PTR(-EINVAL);
1865 }
1866
1867 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
1868
1869 _update_pll_mnp(pll, &cfg);
1870
1871 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
1872 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
1873 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
1874 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
1875
1876 val = pll_readl_base(pll);
1877 if (val & PLL_BASE_ENABLE) {
1878 if (val & BIT(pll_params->iddq_bit_idx)) {
1879 WARN(1, "%s is on but IDDQ set\n", name);
1880 kfree(pll);
1881 return ERR_PTR(-EINVAL);
1882 }
1883 } else
1884 val |= BIT(pll_params->iddq_bit_idx);
1885
1886 val &= ~PLLSS_LOCK_OVERRIDE;
1887 pll_writel_base(val, pll);
1888
1889 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1890 &tegra_clk_pllss_ops);
1891
1892 if (IS_ERR(clk))
1893 kfree(pll);
1894
1895 return clk;
1896}
1897#endif
1898
