1
2
3
4
5
6config EDAC_ATOMIC_SCRUB
7 bool
8
9config EDAC_SUPPORT
10 bool
11
12menuconfig EDAC
13 bool "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT
15 help
16 EDAC is designed to report errors in the core system.
17 These are low-level errors that are reported in the CPU or
18 supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
21
22 If this code is reporting problems on your system, please
23 see the EDAC project web pages for more information at:
24
25 <http://bluesmoke.sourceforge.net/>
26
27 and:
28
29 <http://buttersideup.com/edacwiki>
30
31 There is also a mailing list for the EDAC project, which can
32 be found via the sourceforge page.
33
34if EDAC
35
36config EDAC_LEGACY_SYSFS
37 bool "EDAC legacy sysfs"
38 default y
39 help
40 Enable the compatibility sysfs nodes.
41 Use 'Y' if your edac utilities aren't ported to work with the newer
42 structures.
43
44config EDAC_DEBUG
45 bool "Debugging"
46 help
47 This turns on debugging information for the entire EDAC subsystem.
48 You do so by inserting edac_module with "edac_debug_level=x." Valid
49 levels are 0-4 (from low to high) and by default it is set to 2.
50 Usually you should select 'N' here.
51
52config EDAC_DECODE_MCE
53 tristate "Decode MCEs in human-readable form (only on AMD for now)"
54 depends on CPU_SUP_AMD && X86_MCE_AMD
55 default y
56 ---help---
57 Enable this option if you want to decode Machine Check Exceptions
58 occurring on your machine in human-readable form.
59
60 You should definitely say Y here in case you want to decode MCEs
61 which occur really early upon boot, before the module infrastructure
62 has been initialized.
63
64config EDAC_MM_EDAC
65 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
66 select RAS
67 help
68 Some systems are able to detect and correct errors in main
69 memory. EDAC can report statistics on memory error
70 detection and correction (EDAC - or commonly referred to ECC
71 errors). EDAC will also try to decode where these errors
72 occurred so that a particular failing memory module can be
73 replaced. If unsure, select 'Y'.
74
75config EDAC_GHES
76 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
77 depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
78 default y
79 help
80 Not all machines support hardware-driven error report. Some of those
81 provide a BIOS-driven error report mechanism via ACPI, using the
82 APEI/GHES driver. By enabling this option, the error reports provided
83 by GHES are sent to userspace via the EDAC API.
84
85 When this option is enabled, it will disable the hardware-driven
86 mechanisms, if a GHES BIOS is detected, entering into the
87 "Firmware First" mode.
88
89 It should be noticed that keeping both GHES and a hardware-driven
90 error mechanism won't work well, as BIOS will race with OS, while
91 reading the error registers. So, if you want to not use "Firmware
92 first" GHES error mechanism, you should disable GHES either at
93 compilation time or by passing "ghes.disable=1" Kernel parameter
94 at boot time.
95
96 In doubt, say 'Y'.
97
98config EDAC_AMD64
99 tristate "AMD64 (Opteron, Athlon64)"
100 depends on EDAC_MM_EDAC && AMD_NB && EDAC_DECODE_MCE
101 help
102 Support for error detection and correction of DRAM ECC errors on
103 the AMD64 families (>= K8) of memory controllers.
104
105config EDAC_AMD64_ERROR_INJECTION
106 bool "Sysfs HW Error injection facilities"
107 depends on EDAC_AMD64
108 help
109 Recent Opterons (Family 10h and later) provide for Memory Error
110 Injection into the ECC detection circuits. The amd64_edac module
111 allows the operator/user to inject Uncorrectable and Correctable
112 errors into DRAM.
113
114 When enabled, in each of the respective memory controller directories
115 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
116
117 - inject_section (0..3, 16-byte section of 64-byte cacheline),
118 - inject_word (0..8, 16-bit word of 16-byte section),
119 - inject_ecc_vector (hex ecc vector: select bits of inject word)
120
121 In addition, there are two control files, inject_read and inject_write,
122 which trigger the DRAM ECC Read and Write respectively.
123
124config EDAC_AMD76X
125 tristate "AMD 76x (760, 762, 768)"
126 depends on EDAC_MM_EDAC && PCI && X86_32
127 help
128 Support for error detection and correction on the AMD 76x
129 series of chipsets used with the Athlon processor.
130
131config EDAC_E7XXX
132 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
133 depends on EDAC_MM_EDAC && PCI && X86_32
134 help
135 Support for error detection and correction on the Intel
136 E7205, E7500, E7501 and E7505 server chipsets.
137
138config EDAC_E752X
139 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
140 depends on EDAC_MM_EDAC && PCI && X86
141 help
142 Support for error detection and correction on the Intel
143 E7520, E7525, E7320 server chipsets.
144
145config EDAC_I82443BXGX
146 tristate "Intel 82443BX/GX (440BX/GX)"
147 depends on EDAC_MM_EDAC && PCI && X86_32
148 depends on BROKEN
149 help
150 Support for error detection and correction on the Intel
151 82443BX/GX memory controllers (440BX/GX chipsets).
152
153config EDAC_I82875P
154 tristate "Intel 82875p (D82875P, E7210)"
155 depends on EDAC_MM_EDAC && PCI && X86_32
156 help
157 Support for error detection and correction on the Intel
158 DP82785P and E7210 server chipsets.
159
160config EDAC_I82975X
161 tristate "Intel 82975x (D82975x)"
162 depends on EDAC_MM_EDAC && PCI && X86
163 help
164 Support for error detection and correction on the Intel
165 DP82975x server chipsets.
166
167config EDAC_I3000
168 tristate "Intel 3000/3010"
169 depends on EDAC_MM_EDAC && PCI && X86
170 help
171 Support for error detection and correction on the Intel
172 3000 and 3010 server chipsets.
173
174config EDAC_I3200
175 tristate "Intel 3200"
176 depends on EDAC_MM_EDAC && PCI && X86
177 help
178 Support for error detection and correction on the Intel
179 3200 and 3210 server chipsets.
180
181config EDAC_IE31200
182 tristate "Intel e312xx"
183 depends on EDAC_MM_EDAC && PCI && X86
184 help
185 Support for error detection and correction on the Intel
186 E3-1200 based DRAM controllers.
187
188config EDAC_X38
189 tristate "Intel X38"
190 depends on EDAC_MM_EDAC && PCI && X86
191 help
192 Support for error detection and correction on the Intel
193 X38 server chipsets.
194
195config EDAC_I5400
196 tristate "Intel 5400 (Seaburg) chipsets"
197 depends on EDAC_MM_EDAC && PCI && X86
198 help
199 Support for error detection and correction the Intel
200 i5400 MCH chipset (Seaburg).
201
202config EDAC_I7CORE
203 tristate "Intel i7 Core (Nehalem) processors"
204 depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
205 help
206 Support for error detection and correction the Intel
207 i7 Core (Nehalem) Integrated Memory Controller that exists on
208 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
209 and Xeon 55xx processors.
210
211config EDAC_I82860
212 tristate "Intel 82860"
213 depends on EDAC_MM_EDAC && PCI && X86_32
214 help
215 Support for error detection and correction on the Intel
216 82860 chipset.
217
218config EDAC_R82600
219 tristate "Radisys 82600 embedded chipset"
220 depends on EDAC_MM_EDAC && PCI && X86_32
221 help
222 Support for error detection and correction on the Radisys
223 82600 embedded chipset.
224
225config EDAC_I5000
226 tristate "Intel Greencreek/Blackford chipset"
227 depends on EDAC_MM_EDAC && X86 && PCI
228 help
229 Support for error detection and correction the Intel
230 Greekcreek/Blackford chipsets.
231
232config EDAC_I5100
233 tristate "Intel San Clemente MCH"
234 depends on EDAC_MM_EDAC && X86 && PCI
235 help
236 Support for error detection and correction the Intel
237 San Clemente MCH.
238
239config EDAC_I7300
240 tristate "Intel Clarksboro MCH"
241 depends on EDAC_MM_EDAC && X86 && PCI
242 help
243 Support for error detection and correction the Intel
244 Clarksboro MCH (Intel 7300 chipset).
245
246config EDAC_SBRIDGE
247 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
248 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
249 depends on PCI_MMCONFIG
250 help
251 Support for error detection and correction the Intel
252 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
253
254config EDAC_MPC85XX
255 tristate "Freescale MPC83xx / MPC85xx"
256 depends on EDAC_MM_EDAC && FSL_SOC
257 help
258 Support for error detection and correction on the Freescale
259 MPC8349, MPC8560, MPC8540, MPC8548, T4240
260
261config EDAC_MV64X60
262 tristate "Marvell MV64x60"
263 depends on EDAC_MM_EDAC && MV64X60
264 help
265 Support for error detection and correction on the Marvell
266 MV64360 and MV64460 chipsets.
267
268config EDAC_PASEMI
269 tristate "PA Semi PWRficient"
270 depends on EDAC_MM_EDAC && PCI
271 depends on PPC_PASEMI
272 help
273 Support for error detection and correction on PA Semi
274 PWRficient.
275
276config EDAC_CELL
277 tristate "Cell Broadband Engine memory controller"
278 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
279 help
280 Support for error detection and correction on the
281 Cell Broadband Engine internal memory controller
282 on platform without a hypervisor
283
284config EDAC_PPC4XX
285 tristate "PPC4xx IBM DDR2 Memory Controller"
286 depends on EDAC_MM_EDAC && 4xx
287 help
288 This enables support for EDAC on the ECC memory used
289 with the IBM DDR2 memory controller found in various
290 PowerPC 4xx embedded processors such as the 405EX[r],
291 440SP, 440SPe, 460EX, 460GT and 460SX.
292
293config EDAC_AMD8131
294 tristate "AMD8131 HyperTransport PCI-X Tunnel"
295 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
296 help
297 Support for error detection and correction on the
298 AMD8131 HyperTransport PCI-X Tunnel chip.
299 Note, add more Kconfig dependency if it's adopted
300 on some machine other than Maple.
301
302config EDAC_AMD8111
303 tristate "AMD8111 HyperTransport I/O Hub"
304 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
305 help
306 Support for error detection and correction on the
307 AMD8111 HyperTransport I/O Hub chip.
308 Note, add more Kconfig dependency if it's adopted
309 on some machine other than Maple.
310
311config EDAC_CPC925
312 tristate "IBM CPC925 Memory Controller (PPC970FX)"
313 depends on EDAC_MM_EDAC && PPC64
314 help
315 Support for error detection and correction on the
316 IBM CPC925 Bridge and Memory Controller, which is
317 a companion chip to the PowerPC 970 family of
318 processors.
319
320config EDAC_TILE
321 tristate "Tilera Memory Controller"
322 depends on EDAC_MM_EDAC && TILE
323 default y
324 help
325 Support for error detection and correction on the
326 Tilera memory controller.
327
328config EDAC_HIGHBANK_MC
329 tristate "Highbank Memory Controller"
330 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
331 help
332 Support for error detection and correction on the
333 Calxeda Highbank memory controller.
334
335config EDAC_HIGHBANK_L2
336 tristate "Highbank L2 Cache"
337 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
338 help
339 Support for error detection and correction on the
340 Calxeda Highbank memory controller.
341
342config EDAC_OCTEON_PC
343 tristate "Cavium Octeon Primary Caches"
344 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
345 help
346 Support for error detection and correction on the primary caches of
347 the cnMIPS cores of Cavium Octeon family SOCs.
348
349config EDAC_OCTEON_L2C
350 tristate "Cavium Octeon Secondary Caches (L2C)"
351 depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
352 help
353 Support for error detection and correction on the
354 Cavium Octeon family of SOCs.
355
356config EDAC_OCTEON_LMC
357 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
358 depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
359 help
360 Support for error detection and correction on the
361 Cavium Octeon family of SOCs.
362
363config EDAC_OCTEON_PCI
364 tristate "Cavium Octeon PCI Controller"
365 depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
366 help
367 Support for error detection and correction on the
368 Cavium Octeon family of SOCs.
369
370config EDAC_ALTERA_MC
371 bool "Altera SDRAM Memory Controller EDAC"
372 depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
373 help
374 Support for error detection and correction on the
375 Altera SDRAM memory controller. Note that the
376 preloader must initialize the SDRAM before loading
377 the kernel.
378
379config EDAC_SYNOPSYS
380 tristate "Synopsys DDR Memory Controller"
381 depends on EDAC_MM_EDAC && ARCH_ZYNQ
382 help
383 Support for error detection and correction on the Synopsys DDR
384 memory controller.
385
386config EDAC_XGENE
387 tristate "APM X-Gene SoC"
388 depends on EDAC_MM_EDAC && (ARM64 || COMPILE_TEST)
389 help
390 Support for error detection and correction on the
391 APM X-Gene family of SOCs.
392
393endif
394
