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32#include <drm/drmP.h>
33#include <drm/amdgpu_drm.h>
34#include <drm/drm_gem.h>
35#include "amdgpu_drv.h"
36
37#include <drm/drm_pciids.h>
38#include <linux/console.h>
39#include <linux/module.h>
40#include <linux/pm_runtime.h>
41#include <linux/vga_switcheroo.h>
42#include "drm_crtc_helper.h"
43
44#include "amdgpu.h"
45#include "amdgpu_irq.h"
46
47#include "amdgpu_amdkfd.h"
48
49
50
51
52
53
54#define KMS_DRIVER_MAJOR 3
55#define KMS_DRIVER_MINOR 1
56#define KMS_DRIVER_PATCHLEVEL 0
57
58int amdgpu_vram_limit = 0;
59int amdgpu_gart_size = -1;
60int amdgpu_benchmarking = 0;
61int amdgpu_testing = 0;
62int amdgpu_audio = -1;
63int amdgpu_disp_priority = 0;
64int amdgpu_hw_i2c = 0;
65int amdgpu_pcie_gen2 = -1;
66int amdgpu_msi = -1;
67int amdgpu_lockup_timeout = 0;
68int amdgpu_dpm = -1;
69int amdgpu_smc_load_fw = 1;
70int amdgpu_aspm = -1;
71int amdgpu_runtime_pm = -1;
72int amdgpu_hard_reset = 0;
73unsigned amdgpu_ip_block_mask = 0xffffffff;
74int amdgpu_bapm = -1;
75int amdgpu_deep_color = 0;
76int amdgpu_vm_size = 8;
77int amdgpu_vm_block_size = -1;
78int amdgpu_exp_hw_support = 0;
79int amdgpu_enable_scheduler = 0;
80int amdgpu_sched_jobs = 16;
81int amdgpu_sched_hw_submission = 2;
82int amdgpu_enable_semaphores = 1;
83
84MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
85module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
86
87MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
88module_param_named(gartsize, amdgpu_gart_size, int, 0600);
89
90MODULE_PARM_DESC(benchmark, "Run benchmark");
91module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
92
93MODULE_PARM_DESC(test, "Run tests");
94module_param_named(test, amdgpu_testing, int, 0444);
95
96MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
97module_param_named(audio, amdgpu_audio, int, 0444);
98
99MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
100module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
101
102MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
103module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
104
105MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
106module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
107
108MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
109module_param_named(msi, amdgpu_msi, int, 0444);
110
111MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
112module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
113
114MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
115module_param_named(dpm, amdgpu_dpm, int, 0444);
116
117MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
118module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
119
120MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
121module_param_named(aspm, amdgpu_aspm, int, 0444);
122
123MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
124module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
125
126MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
127module_param_named(hard_reset, amdgpu_hard_reset, int, 0444);
128
129MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
130module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
131
132MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
133module_param_named(bapm, amdgpu_bapm, int, 0444);
134
135MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
136module_param_named(deep_color, amdgpu_deep_color, int, 0444);
137
138MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 8GB)");
139module_param_named(vm_size, amdgpu_vm_size, int, 0444);
140
141MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
142module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
143
144MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
145module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
146
147MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable, 0 = disable ((default))");
148module_param_named(enable_scheduler, amdgpu_enable_scheduler, int, 0444);
149
150MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 16)");
151module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
152
153MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
154module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
155
156MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable (default), 0 = disable)");
157module_param_named(enable_semaphores, amdgpu_enable_semaphores, int, 0644);
158
159static struct pci_device_id pciidlist[] = {
160#ifdef CONFIG_DRM_AMDGPU_CIK
161
162 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
163 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
164 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
165 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
166 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
167 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
168 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
169 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
170 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
171 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
172 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
173 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
174 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
175 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
176 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
177 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
178 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
179 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
180 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
181 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
182 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
183 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
184
185 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
186 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
187 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
188 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
189 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
190 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
191 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
192 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
193 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
194 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
195 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
196
197 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
198 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
199 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
200 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
201 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
202 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
203 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
204 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
205 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
206 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
207 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
208 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
209
210 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
211 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
212 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
213 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
214 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
215 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
216 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
217 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
218 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
219 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
220 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
221 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
222 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
223 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
224 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
225 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
226
227 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
228 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
229 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
230 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
231 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
232 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
233 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
234 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
235 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
236 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
237 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
238 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
239 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
240 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
241 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
242 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
243#endif
244
245 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
246 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
247 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
248 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
249 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
250
251 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
252 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
253 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
254 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
255 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
256 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
257 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
258 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
259 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
260
261 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
262
263 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
264 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
265 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
266 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
267 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
268
269 {0, 0, 0}
270};
271
272MODULE_DEVICE_TABLE(pci, pciidlist);
273
274static struct drm_driver kms_driver;
275
276static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
277{
278 struct apertures_struct *ap;
279 bool primary = false;
280
281 ap = alloc_apertures(1);
282 if (!ap)
283 return -ENOMEM;
284
285 ap->ranges[0].base = pci_resource_start(pdev, 0);
286 ap->ranges[0].size = pci_resource_len(pdev, 0);
287
288#ifdef CONFIG_X86
289 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
290#endif
291 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
292 kfree(ap);
293
294 return 0;
295}
296
297static int amdgpu_pci_probe(struct pci_dev *pdev,
298 const struct pci_device_id *ent)
299{
300 unsigned long flags = ent->driver_data;
301 int ret;
302
303 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
304 DRM_INFO("This hardware requires experimental hardware support.\n"
305 "See modparam exp_hw_support\n");
306 return -ENODEV;
307 }
308
309
310 ret = amdgpu_kick_out_firmware_fb(pdev);
311 if (ret)
312 return ret;
313
314 return drm_get_pci_dev(pdev, ent, &kms_driver);
315}
316
317static void
318amdgpu_pci_remove(struct pci_dev *pdev)
319{
320 struct drm_device *dev = pci_get_drvdata(pdev);
321
322 drm_put_dev(dev);
323}
324
325static int amdgpu_pmops_suspend(struct device *dev)
326{
327 struct pci_dev *pdev = to_pci_dev(dev);
328 struct drm_device *drm_dev = pci_get_drvdata(pdev);
329 return amdgpu_suspend_kms(drm_dev, true, true);
330}
331
332static int amdgpu_pmops_resume(struct device *dev)
333{
334 struct pci_dev *pdev = to_pci_dev(dev);
335 struct drm_device *drm_dev = pci_get_drvdata(pdev);
336 return amdgpu_resume_kms(drm_dev, true, true);
337}
338
339static int amdgpu_pmops_freeze(struct device *dev)
340{
341 struct pci_dev *pdev = to_pci_dev(dev);
342 struct drm_device *drm_dev = pci_get_drvdata(pdev);
343 return amdgpu_suspend_kms(drm_dev, false, true);
344}
345
346static int amdgpu_pmops_thaw(struct device *dev)
347{
348 struct pci_dev *pdev = to_pci_dev(dev);
349 struct drm_device *drm_dev = pci_get_drvdata(pdev);
350 return amdgpu_resume_kms(drm_dev, false, true);
351}
352
353static int amdgpu_pmops_runtime_suspend(struct device *dev)
354{
355 struct pci_dev *pdev = to_pci_dev(dev);
356 struct drm_device *drm_dev = pci_get_drvdata(pdev);
357 int ret;
358
359 if (!amdgpu_device_is_px(drm_dev)) {
360 pm_runtime_forbid(dev);
361 return -EBUSY;
362 }
363
364 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
365 drm_kms_helper_poll_disable(drm_dev);
366 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
367
368 ret = amdgpu_suspend_kms(drm_dev, false, false);
369 pci_save_state(pdev);
370 pci_disable_device(pdev);
371 pci_ignore_hotplug(pdev);
372 pci_set_power_state(pdev, PCI_D3cold);
373 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
374
375 return 0;
376}
377
378static int amdgpu_pmops_runtime_resume(struct device *dev)
379{
380 struct pci_dev *pdev = to_pci_dev(dev);
381 struct drm_device *drm_dev = pci_get_drvdata(pdev);
382 int ret;
383
384 if (!amdgpu_device_is_px(drm_dev))
385 return -EINVAL;
386
387 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
388
389 pci_set_power_state(pdev, PCI_D0);
390 pci_restore_state(pdev);
391 ret = pci_enable_device(pdev);
392 if (ret)
393 return ret;
394 pci_set_master(pdev);
395
396 ret = amdgpu_resume_kms(drm_dev, false, false);
397 drm_kms_helper_poll_enable(drm_dev);
398 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
399 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
400 return 0;
401}
402
403static int amdgpu_pmops_runtime_idle(struct device *dev)
404{
405 struct pci_dev *pdev = to_pci_dev(dev);
406 struct drm_device *drm_dev = pci_get_drvdata(pdev);
407 struct drm_crtc *crtc;
408
409 if (!amdgpu_device_is_px(drm_dev)) {
410 pm_runtime_forbid(dev);
411 return -EBUSY;
412 }
413
414 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
415 if (crtc->enabled) {
416 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
417 return -EBUSY;
418 }
419 }
420
421 pm_runtime_mark_last_busy(dev);
422 pm_runtime_autosuspend(dev);
423
424 return 1;
425}
426
427long amdgpu_drm_ioctl(struct file *filp,
428 unsigned int cmd, unsigned long arg)
429{
430 struct drm_file *file_priv = filp->private_data;
431 struct drm_device *dev;
432 long ret;
433 dev = file_priv->minor->dev;
434 ret = pm_runtime_get_sync(dev->dev);
435 if (ret < 0)
436 return ret;
437
438 ret = drm_ioctl(filp, cmd, arg);
439
440 pm_runtime_mark_last_busy(dev->dev);
441 pm_runtime_put_autosuspend(dev->dev);
442 return ret;
443}
444
445static const struct dev_pm_ops amdgpu_pm_ops = {
446 .suspend = amdgpu_pmops_suspend,
447 .resume = amdgpu_pmops_resume,
448 .freeze = amdgpu_pmops_freeze,
449 .thaw = amdgpu_pmops_thaw,
450 .poweroff = amdgpu_pmops_freeze,
451 .restore = amdgpu_pmops_resume,
452 .runtime_suspend = amdgpu_pmops_runtime_suspend,
453 .runtime_resume = amdgpu_pmops_runtime_resume,
454 .runtime_idle = amdgpu_pmops_runtime_idle,
455};
456
457static const struct file_operations amdgpu_driver_kms_fops = {
458 .owner = THIS_MODULE,
459 .open = drm_open,
460 .release = drm_release,
461 .unlocked_ioctl = amdgpu_drm_ioctl,
462 .mmap = amdgpu_mmap,
463 .poll = drm_poll,
464 .read = drm_read,
465#ifdef CONFIG_COMPAT
466 .compat_ioctl = amdgpu_kms_compat_ioctl,
467#endif
468};
469
470static struct drm_driver kms_driver = {
471 .driver_features =
472 DRIVER_USE_AGP |
473 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
474 DRIVER_PRIME | DRIVER_RENDER,
475 .dev_priv_size = 0,
476 .load = amdgpu_driver_load_kms,
477 .open = amdgpu_driver_open_kms,
478 .preclose = amdgpu_driver_preclose_kms,
479 .postclose = amdgpu_driver_postclose_kms,
480 .lastclose = amdgpu_driver_lastclose_kms,
481 .set_busid = drm_pci_set_busid,
482 .unload = amdgpu_driver_unload_kms,
483 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
484 .enable_vblank = amdgpu_enable_vblank_kms,
485 .disable_vblank = amdgpu_disable_vblank_kms,
486 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
487 .get_scanout_position = amdgpu_get_crtc_scanoutpos,
488#if defined(CONFIG_DEBUG_FS)
489 .debugfs_init = amdgpu_debugfs_init,
490 .debugfs_cleanup = amdgpu_debugfs_cleanup,
491#endif
492 .irq_preinstall = amdgpu_irq_preinstall,
493 .irq_postinstall = amdgpu_irq_postinstall,
494 .irq_uninstall = amdgpu_irq_uninstall,
495 .irq_handler = amdgpu_irq_handler,
496 .ioctls = amdgpu_ioctls_kms,
497 .gem_free_object = amdgpu_gem_object_free,
498 .gem_open_object = amdgpu_gem_object_open,
499 .gem_close_object = amdgpu_gem_object_close,
500 .dumb_create = amdgpu_mode_dumb_create,
501 .dumb_map_offset = amdgpu_mode_dumb_mmap,
502 .dumb_destroy = drm_gem_dumb_destroy,
503 .fops = &amdgpu_driver_kms_fops,
504
505 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
506 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
507 .gem_prime_export = amdgpu_gem_prime_export,
508 .gem_prime_import = drm_gem_prime_import,
509 .gem_prime_pin = amdgpu_gem_prime_pin,
510 .gem_prime_unpin = amdgpu_gem_prime_unpin,
511 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
512 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
513 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
514 .gem_prime_vmap = amdgpu_gem_prime_vmap,
515 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
516
517 .name = DRIVER_NAME,
518 .desc = DRIVER_DESC,
519 .date = DRIVER_DATE,
520 .major = KMS_DRIVER_MAJOR,
521 .minor = KMS_DRIVER_MINOR,
522 .patchlevel = KMS_DRIVER_PATCHLEVEL,
523};
524
525static struct drm_driver *driver;
526static struct pci_driver *pdriver;
527
528static struct pci_driver amdgpu_kms_pci_driver = {
529 .name = DRIVER_NAME,
530 .id_table = pciidlist,
531 .probe = amdgpu_pci_probe,
532 .remove = amdgpu_pci_remove,
533 .driver.pm = &amdgpu_pm_ops,
534};
535
536static int __init amdgpu_init(void)
537{
538#ifdef CONFIG_VGA_CONSOLE
539 if (vgacon_text_force()) {
540 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
541 return -EINVAL;
542 }
543#endif
544 DRM_INFO("amdgpu kernel modesetting enabled.\n");
545 driver = &kms_driver;
546 pdriver = &amdgpu_kms_pci_driver;
547 driver->driver_features |= DRIVER_MODESET;
548 driver->num_ioctls = amdgpu_max_kms_ioctl;
549 amdgpu_register_atpx_handler();
550
551 amdgpu_amdkfd_init();
552
553
554 return drm_pci_init(driver, pdriver);
555}
556
557static void __exit amdgpu_exit(void)
558{
559 amdgpu_amdkfd_fini();
560 drm_pci_exit(driver, pdriver);
561 amdgpu_unregister_atpx_handler();
562}
563
564module_init(amdgpu_init);
565module_exit(amdgpu_exit);
566
567MODULE_AUTHOR(DRIVER_AUTHOR);
568MODULE_DESCRIPTION(DRIVER_DESC);
569MODULE_LICENSE("GPL and additional rights");
570
