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30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34#include <uapi/drm/drm_fourcc.h>
35
36#include "i915_reg.h"
37#include "intel_bios.h"
38#include "intel_ringbuffer.h"
39#include "intel_lrc.h"
40#include "i915_gem_gtt.h"
41#include "i915_gem_render_state.h"
42#include <linux/io-mapping.h>
43#include <linux/i2c.h>
44#include <linux/i2c-algo-bit.h>
45#include <drm/intel-gtt.h>
46#include <drm/drm_legacy.h>
47#include <drm/drm_gem.h>
48#include <linux/backlight.h>
49#include <linux/hashtable.h>
50#include <linux/intel-iommu.h>
51#include <linux/kref.h>
52#include <linux/pm_qos.h>
53
54
55
56
57#define DRIVER_NAME "i915"
58#define DRIVER_DESC "Intel Graphics"
59#define DRIVER_DATE "20150731"
60
61#undef WARN_ON
62
63#if 0
64#define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
69#else
70#define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
71#endif
72
73#undef WARN_ON_ONCE
74#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
75
76#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
78
79
80
81
82
83
84
85
86#define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
90 WARN(1, format); \
91 else \
92 DRM_ERROR(format); \
93 } \
94 unlikely(__ret_warn_on); \
95})
96
97#define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
102 else \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
104 } \
105 unlikely(__ret_warn_on); \
106})
107
108enum pipe {
109 INVALID_PIPE = -1,
110 PIPE_A = 0,
111 PIPE_B,
112 PIPE_C,
113 _PIPE_EDP,
114 I915_MAX_PIPES = _PIPE_EDP
115};
116#define pipe_name(p) ((p) + 'A')
117
118enum transcoder {
119 TRANSCODER_A = 0,
120 TRANSCODER_B,
121 TRANSCODER_C,
122 TRANSCODER_EDP,
123 I915_MAX_TRANSCODERS
124};
125#define transcoder_name(t) ((t) + 'A')
126
127
128
129
130
131
132
133#define I915_MAX_PLANES 4
134
135enum plane {
136 PLANE_A = 0,
137 PLANE_B,
138 PLANE_C,
139};
140#define plane_name(p) ((p) + 'A')
141
142#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
143
144enum port {
145 PORT_A = 0,
146 PORT_B,
147 PORT_C,
148 PORT_D,
149 PORT_E,
150 I915_MAX_PORTS
151};
152#define port_name(p) ((p) + 'A')
153
154#define I915_NUM_PHYS_VLV 2
155
156enum dpio_channel {
157 DPIO_CH0,
158 DPIO_CH1
159};
160
161enum dpio_phy {
162 DPIO_PHY0,
163 DPIO_PHY1
164};
165
166enum intel_display_power_domain {
167 POWER_DOMAIN_PIPE_A,
168 POWER_DOMAIN_PIPE_B,
169 POWER_DOMAIN_PIPE_C,
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
173 POWER_DOMAIN_TRANSCODER_A,
174 POWER_DOMAIN_TRANSCODER_B,
175 POWER_DOMAIN_TRANSCODER_C,
176 POWER_DOMAIN_TRANSCODER_EDP,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES,
185 POWER_DOMAIN_PORT_DDI_E_2_LANES,
186 POWER_DOMAIN_PORT_DSI,
187 POWER_DOMAIN_PORT_CRT,
188 POWER_DOMAIN_PORT_OTHER,
189 POWER_DOMAIN_VGA,
190 POWER_DOMAIN_AUDIO,
191 POWER_DOMAIN_PLLS,
192 POWER_DOMAIN_AUX_A,
193 POWER_DOMAIN_AUX_B,
194 POWER_DOMAIN_AUX_C,
195 POWER_DOMAIN_AUX_D,
196 POWER_DOMAIN_INIT,
197
198 POWER_DOMAIN_NUM,
199};
200
201#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
202#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
203 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
204#define POWER_DOMAIN_TRANSCODER(tran) \
205 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
206 (tran) + POWER_DOMAIN_TRANSCODER_A)
207
208enum hpd_pin {
209 HPD_NONE = 0,
210 HPD_TV = HPD_NONE,
211 HPD_CRT,
212 HPD_SDVO_B,
213 HPD_SDVO_C,
214 HPD_PORT_A,
215 HPD_PORT_B,
216 HPD_PORT_C,
217 HPD_PORT_D,
218 HPD_PORT_E,
219 HPD_NUM_PINS
220};
221
222#define for_each_hpd_pin(__pin) \
223 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
224
225struct i915_hotplug {
226 struct work_struct hotplug_work;
227
228 struct {
229 unsigned long last_jiffies;
230 int count;
231 enum {
232 HPD_ENABLED = 0,
233 HPD_DISABLED = 1,
234 HPD_MARK_DISABLED = 2
235 } state;
236 } stats[HPD_NUM_PINS];
237 u32 event_bits;
238 struct delayed_work reenable_work;
239
240 struct intel_digital_port *irq_port[I915_MAX_PORTS];
241 u32 long_port_mask;
242 u32 short_port_mask;
243 struct work_struct dig_port_work;
244
245
246
247
248
249
250
251
252 struct workqueue_struct *dp_wq;
253};
254
255#define I915_GEM_GPU_DOMAINS \
256 (I915_GEM_DOMAIN_RENDER | \
257 I915_GEM_DOMAIN_SAMPLER | \
258 I915_GEM_DOMAIN_COMMAND | \
259 I915_GEM_DOMAIN_INSTRUCTION | \
260 I915_GEM_DOMAIN_VERTEX)
261
262#define for_each_pipe(__dev_priv, __p) \
263 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
264#define for_each_plane(__dev_priv, __pipe, __p) \
265 for ((__p) = 0; \
266 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
267 (__p)++)
268#define for_each_sprite(__dev_priv, __p, __s) \
269 for ((__s) = 0; \
270 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
271 (__s)++)
272
273#define for_each_crtc(dev, crtc) \
274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
275
276#define for_each_intel_plane(dev, intel_plane) \
277 list_for_each_entry(intel_plane, \
278 &dev->mode_config.plane_list, \
279 base.head)
280
281#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
282 list_for_each_entry(intel_plane, \
283 &(dev)->mode_config.plane_list, \
284 base.head) \
285 if ((intel_plane)->pipe == (intel_crtc)->pipe)
286
287#define for_each_intel_crtc(dev, intel_crtc) \
288 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
289
290#define for_each_intel_encoder(dev, intel_encoder) \
291 list_for_each_entry(intel_encoder, \
292 &(dev)->mode_config.encoder_list, \
293 base.head)
294
295#define for_each_intel_connector(dev, intel_connector) \
296 list_for_each_entry(intel_connector, \
297 &dev->mode_config.connector_list, \
298 base.head)
299
300#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
301 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
302 if ((intel_encoder)->base.crtc == (__crtc))
303
304#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
305 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
306 if ((intel_connector)->base.encoder == (__encoder))
307
308#define for_each_power_domain(domain, mask) \
309 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
310 if ((1 << (domain)) & (mask))
311
312struct drm_i915_private;
313struct i915_mm_struct;
314struct i915_mmu_object;
315
316struct drm_i915_file_private {
317 struct drm_i915_private *dev_priv;
318 struct drm_file *file;
319
320 struct {
321 spinlock_t lock;
322 struct list_head request_list;
323
324
325
326
327
328#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
329 } mm;
330 struct idr context_idr;
331
332 struct intel_rps_client {
333 struct list_head link;
334 unsigned boosts;
335 } rps;
336
337 struct intel_engine_cs *bsd_ring;
338};
339
340enum intel_dpll_id {
341 DPLL_ID_PRIVATE = -1,
342
343 DPLL_ID_PCH_PLL_A = 0,
344 DPLL_ID_PCH_PLL_B = 1,
345
346 DPLL_ID_WRPLL1 = 0,
347 DPLL_ID_WRPLL2 = 1,
348
349 DPLL_ID_SKL_DPLL1 = 0,
350 DPLL_ID_SKL_DPLL2 = 1,
351 DPLL_ID_SKL_DPLL3 = 2,
352};
353#define I915_NUM_PLLS 3
354
355struct intel_dpll_hw_state {
356
357 uint32_t dpll;
358 uint32_t dpll_md;
359 uint32_t fp0;
360 uint32_t fp1;
361
362
363 uint32_t wrpll;
364
365
366
367
368
369
370
371
372 uint32_t ctrl1;
373
374 uint32_t cfgcr1, cfgcr2;
375
376
377 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
378 pcsdw12;
379};
380
381struct intel_shared_dpll_config {
382 unsigned crtc_mask;
383 struct intel_dpll_hw_state hw_state;
384};
385
386struct intel_shared_dpll {
387 struct intel_shared_dpll_config config;
388
389 int active;
390 bool on;
391 const char *name;
392
393 enum intel_dpll_id id;
394
395
396 void (*mode_set)(struct drm_i915_private *dev_priv,
397 struct intel_shared_dpll *pll);
398 void (*enable)(struct drm_i915_private *dev_priv,
399 struct intel_shared_dpll *pll);
400 void (*disable)(struct drm_i915_private *dev_priv,
401 struct intel_shared_dpll *pll);
402 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
403 struct intel_shared_dpll *pll,
404 struct intel_dpll_hw_state *hw_state);
405};
406
407#define SKL_DPLL0 0
408#define SKL_DPLL1 1
409#define SKL_DPLL2 2
410#define SKL_DPLL3 3
411
412
413struct intel_link_m_n {
414 uint32_t tu;
415 uint32_t gmch_m;
416 uint32_t gmch_n;
417 uint32_t link_m;
418 uint32_t link_n;
419};
420
421void intel_link_compute_m_n(int bpp, int nlanes,
422 int pixel_clock, int link_clock,
423 struct intel_link_m_n *m_n);
424
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434
435#define DRIVER_MAJOR 1
436#define DRIVER_MINOR 6
437#define DRIVER_PATCHLEVEL 0
438
439#define WATCH_LISTS 0
440
441struct opregion_header;
442struct opregion_acpi;
443struct opregion_swsci;
444struct opregion_asle;
445
446struct intel_opregion {
447 struct opregion_header __iomem *header;
448 struct opregion_acpi __iomem *acpi;
449 struct opregion_swsci __iomem *swsci;
450 u32 swsci_gbda_sub_functions;
451 u32 swsci_sbcb_sub_functions;
452 struct opregion_asle __iomem *asle;
453 void __iomem *vbt;
454 u32 __iomem *lid_state;
455 struct work_struct asle_work;
456};
457#define OPREGION_SIZE (8*1024)
458
459struct intel_overlay;
460struct intel_overlay_error_state;
461
462#define I915_FENCE_REG_NONE -1
463#define I915_MAX_NUM_FENCES 32
464
465#define I915_MAX_NUM_FENCE_BITS 6
466
467struct drm_i915_fence_reg {
468 struct list_head lru_list;
469 struct drm_i915_gem_object *obj;
470 int pin_count;
471};
472
473struct sdvo_device_mapping {
474 u8 initialized;
475 u8 dvo_port;
476 u8 slave_addr;
477 u8 dvo_wiring;
478 u8 i2c_pin;
479 u8 ddc_pin;
480};
481
482struct intel_display_error_state;
483
484struct drm_i915_error_state {
485 struct kref ref;
486 struct timeval time;
487
488 char error_msg[128];
489 int iommu;
490 u32 reset_count;
491 u32 suspend_count;
492
493
494 u32 eir;
495 u32 pgtbl_er;
496 u32 ier;
497 u32 gtier[4];
498 u32 ccid;
499 u32 derrmr;
500 u32 forcewake;
501 u32 error;
502 u32 err_int;
503 u32 fault_data0;
504 u32 fault_data1;
505 u32 done_reg;
506 u32 gac_eco;
507 u32 gam_ecochk;
508 u32 gab_ctl;
509 u32 gfx_mode;
510 u32 extra_instdone[I915_NUM_INSTDONE_REG];
511 u64 fence[I915_MAX_NUM_FENCES];
512 struct intel_overlay_error_state *overlay;
513 struct intel_display_error_state *display;
514 struct drm_i915_error_object *semaphore_obj;
515
516 struct drm_i915_error_ring {
517 bool valid;
518
519 bool waiting;
520 int hangcheck_score;
521 enum intel_ring_hangcheck_action hangcheck_action;
522 int num_requests;
523
524
525 u32 cpu_ring_head;
526 u32 cpu_ring_tail;
527
528 u32 semaphore_seqno[I915_NUM_RINGS - 1];
529
530
531 u32 start;
532 u32 tail;
533 u32 head;
534 u32 ctl;
535 u32 hws;
536 u32 ipeir;
537 u32 ipehr;
538 u32 instdone;
539 u32 bbstate;
540 u32 instpm;
541 u32 instps;
542 u32 seqno;
543 u64 bbaddr;
544 u64 acthd;
545 u32 fault_reg;
546 u64 faddr;
547 u32 rc_psmi;
548 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
549
550 struct drm_i915_error_object {
551 int page_count;
552 u32 gtt_offset;
553 u32 *pages[0];
554 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
555
556 struct drm_i915_error_request {
557 long jiffies;
558 u32 seqno;
559 u32 tail;
560 } *requests;
561
562 struct {
563 u32 gfx_mode;
564 union {
565 u64 pdp[4];
566 u32 pp_dir_base;
567 };
568 } vm_info;
569
570 pid_t pid;
571 char comm[TASK_COMM_LEN];
572 } ring[I915_NUM_RINGS];
573
574 struct drm_i915_error_buffer {
575 u32 size;
576 u32 name;
577 u32 rseqno[I915_NUM_RINGS], wseqno;
578 u32 gtt_offset;
579 u32 read_domains;
580 u32 write_domain;
581 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
582 s32 pinned:2;
583 u32 tiling:2;
584 u32 dirty:1;
585 u32 purgeable:1;
586 u32 userptr:1;
587 s32 ring:4;
588 u32 cache_level:3;
589 } **active_bo, **pinned_bo;
590
591 u32 *active_bo_count, *pinned_bo_count;
592 u32 vm_count;
593};
594
595struct intel_connector;
596struct intel_encoder;
597struct intel_crtc_state;
598struct intel_initial_plane_config;
599struct intel_crtc;
600struct intel_limit;
601struct dpll;
602
603struct drm_i915_display_funcs {
604 int (*get_display_clock_speed)(struct drm_device *dev);
605 int (*get_fifo_size)(struct drm_device *dev, int plane);
606
607
608
609
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611
612
613
614
615
616
617
618
619 bool (*find_dpll)(const struct intel_limit *limit,
620 struct intel_crtc_state *crtc_state,
621 int target, int refclk,
622 struct dpll *match_clock,
623 struct dpll *best_clock);
624 void (*update_wm)(struct drm_crtc *crtc);
625 void (*update_sprite_wm)(struct drm_plane *plane,
626 struct drm_crtc *crtc,
627 uint32_t sprite_width, uint32_t sprite_height,
628 int pixel_size, bool enable, bool scaled);
629 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
630 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
631
632
633 bool (*get_pipe_config)(struct intel_crtc *,
634 struct intel_crtc_state *);
635 void (*get_initial_plane_config)(struct intel_crtc *,
636 struct intel_initial_plane_config *);
637 int (*crtc_compute_clock)(struct intel_crtc *crtc,
638 struct intel_crtc_state *crtc_state);
639 void (*crtc_enable)(struct drm_crtc *crtc);
640 void (*crtc_disable)(struct drm_crtc *crtc);
641 void (*audio_codec_enable)(struct drm_connector *connector,
642 struct intel_encoder *encoder,
643 struct drm_display_mode *mode);
644 void (*audio_codec_disable)(struct intel_encoder *encoder);
645 void (*fdi_link_train)(struct drm_crtc *crtc);
646 void (*init_clock_gating)(struct drm_device *dev);
647 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
648 struct drm_framebuffer *fb,
649 struct drm_i915_gem_object *obj,
650 struct drm_i915_gem_request *req,
651 uint32_t flags);
652 void (*update_primary_plane)(struct drm_crtc *crtc,
653 struct drm_framebuffer *fb,
654 int x, int y);
655 void (*hpd_irq_setup)(struct drm_device *dev);
656
657
658
659
660
661
662 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
663 uint32_t (*get_backlight)(struct intel_connector *connector);
664 void (*set_backlight)(struct intel_connector *connector,
665 uint32_t level);
666 void (*disable_backlight)(struct intel_connector *connector);
667 void (*enable_backlight)(struct intel_connector *connector);
668};
669
670enum forcewake_domain_id {
671 FW_DOMAIN_ID_RENDER = 0,
672 FW_DOMAIN_ID_BLITTER,
673 FW_DOMAIN_ID_MEDIA,
674
675 FW_DOMAIN_ID_COUNT
676};
677
678enum forcewake_domains {
679 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
680 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
681 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
682 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
683 FORCEWAKE_BLITTER |
684 FORCEWAKE_MEDIA)
685};
686
687struct intel_uncore_funcs {
688 void (*force_wake_get)(struct drm_i915_private *dev_priv,
689 enum forcewake_domains domains);
690 void (*force_wake_put)(struct drm_i915_private *dev_priv,
691 enum forcewake_domains domains);
692
693 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
694 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
695 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
696 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
697
698 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
699 uint8_t val, bool trace);
700 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
701 uint16_t val, bool trace);
702 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
703 uint32_t val, bool trace);
704 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
705 uint64_t val, bool trace);
706};
707
708struct intel_uncore {
709 spinlock_t lock;
710
711 struct intel_uncore_funcs funcs;
712
713 unsigned fifo_count;
714 enum forcewake_domains fw_domains;
715
716 struct intel_uncore_forcewake_domain {
717 struct drm_i915_private *i915;
718 enum forcewake_domain_id id;
719 unsigned wake_count;
720 struct timer_list timer;
721 u32 reg_set;
722 u32 val_set;
723 u32 val_clear;
724 u32 reg_ack;
725 u32 reg_post;
726 u32 val_reset;
727 } fw_domain[FW_DOMAIN_ID_COUNT];
728};
729
730
731#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
732 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
733 (i__) < FW_DOMAIN_ID_COUNT; \
734 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
735 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
736
737#define for_each_fw_domain(domain__, dev_priv__, i__) \
738 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
739
740enum csr_state {
741 FW_UNINITIALIZED = 0,
742 FW_LOADED,
743 FW_FAILED
744};
745
746struct intel_csr {
747 const char *fw_path;
748 uint32_t *dmc_payload;
749 uint32_t dmc_fw_size;
750 uint32_t mmio_count;
751 uint32_t mmioaddr[8];
752 uint32_t mmiodata[8];
753 enum csr_state state;
754};
755
756#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
757 func(is_mobile) sep \
758 func(is_i85x) sep \
759 func(is_i915g) sep \
760 func(is_i945gm) sep \
761 func(is_g33) sep \
762 func(need_gfx_hws) sep \
763 func(is_g4x) sep \
764 func(is_pineview) sep \
765 func(is_broadwater) sep \
766 func(is_crestline) sep \
767 func(is_ivybridge) sep \
768 func(is_valleyview) sep \
769 func(is_haswell) sep \
770 func(is_skylake) sep \
771 func(is_preliminary) sep \
772 func(has_fbc) sep \
773 func(has_pipe_cxsr) sep \
774 func(has_hotplug) sep \
775 func(cursor_needs_physical) sep \
776 func(has_overlay) sep \
777 func(overlay_needs_physical) sep \
778 func(supports_tv) sep \
779 func(has_llc) sep \
780 func(has_ddi) sep \
781 func(has_fpga_dbg)
782
783#define DEFINE_FLAG(name) u8 name:1
784#define SEP_SEMICOLON ;
785
786struct intel_device_info {
787 u32 display_mmio_offset;
788 u16 device_id;
789 u8 num_pipes:3;
790 u8 num_sprites[I915_MAX_PIPES];
791 u8 gen;
792 u8 ring_mask;
793 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
794
795 int pipe_offsets[I915_MAX_TRANSCODERS];
796 int trans_offsets[I915_MAX_TRANSCODERS];
797 int palette_offsets[I915_MAX_PIPES];
798 int cursor_offsets[I915_MAX_PIPES];
799
800
801 u8 slice_total;
802 u8 subslice_total;
803 u8 subslice_per_slice;
804 u8 eu_total;
805 u8 eu_per_subslice;
806
807 u8 subslice_7eu[3];
808 u8 has_slice_pg:1;
809 u8 has_subslice_pg:1;
810 u8 has_eu_pg:1;
811};
812
813#undef DEFINE_FLAG
814#undef SEP_SEMICOLON
815
816enum i915_cache_level {
817 I915_CACHE_NONE = 0,
818 I915_CACHE_LLC,
819 I915_CACHE_L3_LLC,
820
821
822
823 I915_CACHE_WT,
824};
825
826struct i915_ctx_hang_stats {
827
828 unsigned batch_pending;
829
830
831 unsigned batch_active;
832
833
834 unsigned long guilty_ts;
835
836
837
838
839 unsigned long ban_period_seconds;
840
841
842 bool banned;
843};
844
845
846#define DEFAULT_CONTEXT_HANDLE 0
847
848#define CONTEXT_NO_ZEROMAP (1<<0)
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868struct intel_context {
869 struct kref ref;
870 int user_handle;
871 uint8_t remap_slice;
872 struct drm_i915_private *i915;
873 int flags;
874 struct drm_i915_file_private *file_priv;
875 struct i915_ctx_hang_stats hang_stats;
876 struct i915_hw_ppgtt *ppgtt;
877
878
879 struct {
880 struct drm_i915_gem_object *rcs_state;
881 bool initialized;
882 } legacy_hw_ctx;
883
884
885 bool rcs_initialized;
886 struct {
887 struct drm_i915_gem_object *state;
888 struct intel_ringbuffer *ringbuf;
889 int pin_count;
890 } engine[I915_NUM_RINGS];
891
892 struct list_head link;
893};
894
895enum fb_op_origin {
896 ORIGIN_GTT,
897 ORIGIN_CPU,
898 ORIGIN_CS,
899 ORIGIN_FLIP,
900 ORIGIN_DIRTYFB,
901};
902
903struct i915_fbc {
904
905
906 struct mutex lock;
907 unsigned long uncompressed_size;
908 unsigned threshold;
909 unsigned int fb_id;
910 unsigned int possible_framebuffer_bits;
911 unsigned int busy_bits;
912 struct intel_crtc *crtc;
913 int y;
914
915 struct drm_mm_node compressed_fb;
916 struct drm_mm_node *compressed_llb;
917
918 bool false_color;
919
920
921
922 bool enabled;
923
924 struct intel_fbc_work {
925 struct delayed_work work;
926 struct intel_crtc *crtc;
927 struct drm_framebuffer *fb;
928 } *fbc_work;
929
930 enum no_fbc_reason {
931 FBC_OK,
932 FBC_UNSUPPORTED,
933 FBC_NO_OUTPUT,
934 FBC_STOLEN_TOO_SMALL,
935 FBC_UNSUPPORTED_MODE,
936 FBC_MODE_TOO_LARGE,
937 FBC_BAD_PLANE,
938 FBC_NOT_TILED,
939 FBC_MULTIPLE_PIPES,
940 FBC_MODULE_PARAM,
941 FBC_CHIP_DEFAULT,
942 FBC_ROTATION,
943 FBC_IN_DBG_MASTER,
944 } no_fbc_reason;
945
946 bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
947 void (*enable_fbc)(struct intel_crtc *crtc);
948 void (*disable_fbc)(struct drm_i915_private *dev_priv);
949};
950
951
952
953
954
955
956enum drrs_refresh_rate_type {
957 DRRS_HIGH_RR,
958 DRRS_LOW_RR,
959 DRRS_MAX_RR,
960};
961
962enum drrs_support_type {
963 DRRS_NOT_SUPPORTED = 0,
964 STATIC_DRRS_SUPPORT = 1,
965 SEAMLESS_DRRS_SUPPORT = 2
966};
967
968struct intel_dp;
969struct i915_drrs {
970 struct mutex mutex;
971 struct delayed_work work;
972 struct intel_dp *dp;
973 unsigned busy_frontbuffer_bits;
974 enum drrs_refresh_rate_type refresh_rate_type;
975 enum drrs_support_type type;
976};
977
978struct i915_psr {
979 struct mutex lock;
980 bool sink_support;
981 bool source_ok;
982 struct intel_dp *enabled;
983 bool active;
984 struct delayed_work work;
985 unsigned busy_frontbuffer_bits;
986 bool psr2_support;
987 bool aux_frame_sync;
988};
989
990enum intel_pch {
991 PCH_NONE = 0,
992 PCH_IBX,
993 PCH_CPT,
994 PCH_LPT,
995 PCH_SPT,
996 PCH_NOP,
997};
998
999enum intel_sbi_destination {
1000 SBI_ICLK,
1001 SBI_MPHY,
1002};
1003
1004#define QUIRK_PIPEA_FORCE (1<<0)
1005#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1006#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1007#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1008#define QUIRK_PIPEB_FORCE (1<<4)
1009#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1010
1011struct intel_fbdev;
1012struct intel_fbc_work;
1013
1014struct intel_gmbus {
1015 struct i2c_adapter adapter;
1016 u32 force_bit;
1017 u32 reg0;
1018 u32 gpio_reg;
1019 struct i2c_algo_bit_data bit_algo;
1020 struct drm_i915_private *dev_priv;
1021};
1022
1023struct i915_suspend_saved_registers {
1024 u32 saveDSPARB;
1025 u32 saveLVDS;
1026 u32 savePP_ON_DELAYS;
1027 u32 savePP_OFF_DELAYS;
1028 u32 savePP_ON;
1029 u32 savePP_OFF;
1030 u32 savePP_CONTROL;
1031 u32 savePP_DIVISOR;
1032 u32 saveFBC_CONTROL;
1033 u32 saveCACHE_MODE_0;
1034 u32 saveMI_ARB_STATE;
1035 u32 saveSWF0[16];
1036 u32 saveSWF1[16];
1037 u32 saveSWF2[3];
1038 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1039 u32 savePCH_PORT_HOTPLUG;
1040 u16 saveGCDGMBUS;
1041};
1042
1043struct vlv_s0ix_state {
1044
1045 u32 wr_watermark;
1046 u32 gfx_prio_ctrl;
1047 u32 arb_mode;
1048 u32 gfx_pend_tlb0;
1049 u32 gfx_pend_tlb1;
1050 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1051 u32 media_max_req_count;
1052 u32 gfx_max_req_count;
1053 u32 render_hwsp;
1054 u32 ecochk;
1055 u32 bsd_hwsp;
1056 u32 blt_hwsp;
1057 u32 tlb_rd_addr;
1058
1059
1060 u32 g3dctl;
1061 u32 gsckgctl;
1062 u32 mbctl;
1063
1064
1065 u32 ucgctl1;
1066 u32 ucgctl3;
1067 u32 rcgctl1;
1068 u32 rcgctl2;
1069 u32 rstctl;
1070 u32 misccpctl;
1071
1072
1073 u32 gfxpause;
1074 u32 rpdeuhwtc;
1075 u32 rpdeuc;
1076 u32 ecobus;
1077 u32 pwrdwnupctl;
1078 u32 rp_down_timeout;
1079 u32 rp_deucsw;
1080 u32 rcubmabdtmr;
1081 u32 rcedata;
1082 u32 spare2gh;
1083
1084
1085 u32 gt_imr;
1086 u32 gt_ier;
1087 u32 pm_imr;
1088 u32 pm_ier;
1089 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1090
1091
1092 u32 tilectl;
1093 u32 gt_fifoctl;
1094 u32 gtlc_wake_ctrl;
1095 u32 gtlc_survive;
1096 u32 pmwgicz;
1097
1098
1099 u32 gu_ctl0;
1100 u32 gu_ctl1;
1101 u32 pcbr;
1102 u32 clock_gate_dis2;
1103};
1104
1105struct intel_rps_ei {
1106 u32 cz_clock;
1107 u32 render_c0;
1108 u32 media_c0;
1109};
1110
1111struct intel_gen6_power_mgmt {
1112
1113
1114
1115
1116 struct work_struct work;
1117 bool interrupts_enabled;
1118 u32 pm_iir;
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130 u8 cur_freq;
1131 u8 min_freq_softlimit;
1132 u8 max_freq_softlimit;
1133 u8 max_freq;
1134 u8 min_freq;
1135 u8 idle_freq;
1136 u8 efficient_freq;
1137 u8 rp1_freq;
1138 u8 rp0_freq;
1139 u32 cz_freq;
1140
1141 u8 up_threshold;
1142 u8 down_threshold;
1143
1144 int last_adj;
1145 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1146
1147 spinlock_t client_lock;
1148 struct list_head clients;
1149 bool client_boost;
1150
1151 bool enabled;
1152 struct delayed_work delayed_resume_work;
1153 unsigned boosts;
1154
1155 struct intel_rps_client semaphores, mmioflips;
1156
1157
1158 struct intel_rps_ei up_ei, down_ei;
1159
1160
1161
1162
1163
1164
1165
1166 struct mutex hw_lock;
1167};
1168
1169
1170extern spinlock_t mchdev_lock;
1171
1172struct intel_ilk_power_mgmt {
1173 u8 cur_delay;
1174 u8 min_delay;
1175 u8 max_delay;
1176 u8 fmax;
1177 u8 fstart;
1178
1179 u64 last_count1;
1180 unsigned long last_time1;
1181 unsigned long chipset_power;
1182 u64 last_count2;
1183 u64 last_time2;
1184 unsigned long gfx_power;
1185 u8 corr;
1186
1187 int c_m;
1188 int r_t;
1189};
1190
1191struct drm_i915_private;
1192struct i915_power_well;
1193
1194struct i915_power_well_ops {
1195
1196
1197
1198
1199
1200
1201 void (*sync_hw)(struct drm_i915_private *dev_priv,
1202 struct i915_power_well *power_well);
1203
1204
1205
1206
1207
1208 void (*enable)(struct drm_i915_private *dev_priv,
1209 struct i915_power_well *power_well);
1210
1211
1212
1213
1214 void (*disable)(struct drm_i915_private *dev_priv,
1215 struct i915_power_well *power_well);
1216
1217 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1218 struct i915_power_well *power_well);
1219};
1220
1221
1222struct i915_power_well {
1223 const char *name;
1224 bool always_on;
1225
1226 int count;
1227
1228 bool hw_enabled;
1229 unsigned long domains;
1230 unsigned long data;
1231 const struct i915_power_well_ops *ops;
1232};
1233
1234struct i915_power_domains {
1235
1236
1237
1238
1239 bool init_power_on;
1240 bool initializing;
1241 int power_well_count;
1242
1243 struct mutex lock;
1244 int domain_use_count[POWER_DOMAIN_NUM];
1245 struct i915_power_well *power_wells;
1246};
1247
1248#define MAX_L3_SLICES 2
1249struct intel_l3_parity {
1250 u32 *remap_info[MAX_L3_SLICES];
1251 struct work_struct error_work;
1252 int which_slice;
1253};
1254
1255struct i915_gem_mm {
1256
1257 struct drm_mm stolen;
1258
1259
1260 struct mutex stolen_lock;
1261
1262
1263
1264 struct list_head bound_list;
1265
1266
1267
1268
1269
1270 struct list_head unbound_list;
1271
1272
1273 unsigned long stolen_base;
1274
1275
1276 struct i915_hw_ppgtt *aliasing_ppgtt;
1277
1278 struct notifier_block oom_notifier;
1279 struct shrinker shrinker;
1280 bool shrinker_no_lock_stealing;
1281
1282
1283 struct list_head fence_list;
1284
1285
1286
1287
1288
1289
1290
1291
1292 struct delayed_work retire_work;
1293
1294
1295
1296
1297
1298
1299
1300
1301 struct delayed_work idle_work;
1302
1303
1304
1305
1306
1307 bool interruptible;
1308
1309
1310
1311
1312
1313
1314
1315 bool busy;
1316
1317
1318 int bsd_ring_dispatch_index;
1319
1320
1321 uint32_t bit_6_swizzle_x;
1322
1323 uint32_t bit_6_swizzle_y;
1324
1325
1326 spinlock_t object_stat_lock;
1327 size_t object_memory;
1328 u32 object_count;
1329};
1330
1331struct drm_i915_error_state_buf {
1332 struct drm_i915_private *i915;
1333 unsigned bytes;
1334 unsigned size;
1335 int err;
1336 u8 *buf;
1337 loff_t start;
1338 loff_t pos;
1339};
1340
1341struct i915_error_state_file_priv {
1342 struct drm_device *dev;
1343 struct drm_i915_error_state *error;
1344};
1345
1346struct i915_gpu_error {
1347
1348#define DRM_I915_HANGCHECK_PERIOD 1500
1349#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1350
1351#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1352
1353 struct workqueue_struct *hangcheck_wq;
1354 struct delayed_work hangcheck_work;
1355
1356
1357 spinlock_t lock;
1358
1359 struct drm_i915_error_state *first_error;
1360
1361 unsigned long missed_irq_rings;
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384 atomic_t reset_counter;
1385
1386#define I915_RESET_IN_PROGRESS_FLAG 1
1387#define I915_WEDGED (1 << 31)
1388
1389
1390
1391
1392
1393 wait_queue_head_t reset_queue;
1394
1395
1396
1397
1398 u32 stop_rings;
1399#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1400#define I915_STOP_RING_ALLOW_WARN (1 << 30)
1401
1402
1403 unsigned int test_irq_rings;
1404
1405
1406 bool reload_in_reset;
1407};
1408
1409enum modeset_restore {
1410 MODESET_ON_LID_OPEN,
1411 MODESET_DONE,
1412 MODESET_SUSPENDED,
1413};
1414
1415#define DP_AUX_A 0x40
1416#define DP_AUX_B 0x10
1417#define DP_AUX_C 0x20
1418#define DP_AUX_D 0x30
1419
1420#define DDC_PIN_B 0x05
1421#define DDC_PIN_C 0x04
1422#define DDC_PIN_D 0x06
1423
1424struct ddi_vbt_port_info {
1425
1426
1427
1428
1429
1430#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1431 uint8_t hdmi_level_shift;
1432
1433 uint8_t supports_dvi:1;
1434 uint8_t supports_hdmi:1;
1435 uint8_t supports_dp:1;
1436
1437 uint8_t alternate_aux_channel;
1438 uint8_t alternate_ddc_pin;
1439
1440 uint8_t dp_boost_level;
1441 uint8_t hdmi_boost_level;
1442};
1443
1444enum psr_lines_to_wait {
1445 PSR_0_LINES_TO_WAIT = 0,
1446 PSR_1_LINE_TO_WAIT,
1447 PSR_4_LINES_TO_WAIT,
1448 PSR_8_LINES_TO_WAIT
1449};
1450
1451struct intel_vbt_data {
1452 struct drm_display_mode *lfp_lvds_vbt_mode;
1453 struct drm_display_mode *sdvo_lvds_vbt_mode;
1454
1455
1456 unsigned int int_tv_support:1;
1457 unsigned int lvds_dither:1;
1458 unsigned int lvds_vbt:1;
1459 unsigned int int_crt_support:1;
1460 unsigned int lvds_use_ssc:1;
1461 unsigned int display_clock_mode:1;
1462 unsigned int fdi_rx_polarity_inverted:1;
1463 unsigned int has_mipi:1;
1464 int lvds_ssc_freq;
1465 unsigned int bios_lvds_val;
1466
1467 enum drrs_support_type drrs_type;
1468
1469
1470 int edp_rate;
1471 int edp_lanes;
1472 int edp_preemphasis;
1473 int edp_vswing;
1474 bool edp_initialized;
1475 bool edp_support;
1476 int edp_bpp;
1477 struct edp_power_seq edp_pps;
1478
1479 struct {
1480 bool full_link;
1481 bool require_aux_wakeup;
1482 int idle_frames;
1483 enum psr_lines_to_wait lines_to_wait;
1484 int tp1_wakeup_time;
1485 int tp2_tp3_wakeup_time;
1486 } psr;
1487
1488 struct {
1489 u16 pwm_freq_hz;
1490 bool present;
1491 bool active_low_pwm;
1492 u8 min_brightness;
1493 } backlight;
1494
1495
1496 struct {
1497 u16 port;
1498 u16 panel_id;
1499 struct mipi_config *config;
1500 struct mipi_pps_data *pps;
1501 u8 seq_version;
1502 u32 size;
1503 u8 *data;
1504 u8 *sequence[MIPI_SEQ_MAX];
1505 } dsi;
1506
1507 int crt_ddc_pin;
1508
1509 int child_dev_num;
1510 union child_device_config *child_dev;
1511
1512 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1513};
1514
1515enum intel_ddb_partitioning {
1516 INTEL_DDB_PART_1_2,
1517 INTEL_DDB_PART_5_6,
1518};
1519
1520struct intel_wm_level {
1521 bool enable;
1522 uint32_t pri_val;
1523 uint32_t spr_val;
1524 uint32_t cur_val;
1525 uint32_t fbc_val;
1526};
1527
1528struct ilk_wm_values {
1529 uint32_t wm_pipe[3];
1530 uint32_t wm_lp[3];
1531 uint32_t wm_lp_spr[3];
1532 uint32_t wm_linetime[3];
1533 bool enable_fbc_wm;
1534 enum intel_ddb_partitioning partitioning;
1535};
1536
1537struct vlv_pipe_wm {
1538 uint16_t primary;
1539 uint16_t sprite[2];
1540 uint8_t cursor;
1541};
1542
1543struct vlv_sr_wm {
1544 uint16_t plane;
1545 uint8_t cursor;
1546};
1547
1548struct vlv_wm_values {
1549 struct vlv_pipe_wm pipe[3];
1550 struct vlv_sr_wm sr;
1551 struct {
1552 uint8_t cursor;
1553 uint8_t sprite[2];
1554 uint8_t primary;
1555 } ddl[3];
1556 uint8_t level;
1557 bool cxsr;
1558};
1559
1560struct skl_ddb_entry {
1561 uint16_t start, end;
1562};
1563
1564static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1565{
1566 return entry->end - entry->start;
1567}
1568
1569static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1570 const struct skl_ddb_entry *e2)
1571{
1572 if (e1->start == e2->start && e1->end == e2->end)
1573 return true;
1574
1575 return false;
1576}
1577
1578struct skl_ddb_allocation {
1579 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1580 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1581 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1582 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1583};
1584
1585struct skl_wm_values {
1586 bool dirty[I915_MAX_PIPES];
1587 struct skl_ddb_allocation ddb;
1588 uint32_t wm_linetime[I915_MAX_PIPES];
1589 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1590 uint32_t cursor[I915_MAX_PIPES][8];
1591 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1592 uint32_t cursor_trans[I915_MAX_PIPES];
1593};
1594
1595struct skl_wm_level {
1596 bool plane_en[I915_MAX_PLANES];
1597 bool cursor_en;
1598 uint16_t plane_res_b[I915_MAX_PLANES];
1599 uint8_t plane_res_l[I915_MAX_PLANES];
1600 uint16_t cursor_res_b;
1601 uint8_t cursor_res_l;
1602};
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627struct i915_runtime_pm {
1628 bool suspended;
1629 bool irqs_enabled;
1630};
1631
1632enum intel_pipe_crc_source {
1633 INTEL_PIPE_CRC_SOURCE_NONE,
1634 INTEL_PIPE_CRC_SOURCE_PLANE1,
1635 INTEL_PIPE_CRC_SOURCE_PLANE2,
1636 INTEL_PIPE_CRC_SOURCE_PF,
1637 INTEL_PIPE_CRC_SOURCE_PIPE,
1638
1639 INTEL_PIPE_CRC_SOURCE_TV,
1640 INTEL_PIPE_CRC_SOURCE_DP_B,
1641 INTEL_PIPE_CRC_SOURCE_DP_C,
1642 INTEL_PIPE_CRC_SOURCE_DP_D,
1643 INTEL_PIPE_CRC_SOURCE_AUTO,
1644 INTEL_PIPE_CRC_SOURCE_MAX,
1645};
1646
1647struct intel_pipe_crc_entry {
1648 uint32_t frame;
1649 uint32_t crc[5];
1650};
1651
1652#define INTEL_PIPE_CRC_ENTRIES_NR 128
1653struct intel_pipe_crc {
1654 spinlock_t lock;
1655 bool opened;
1656 struct intel_pipe_crc_entry *entries;
1657 enum intel_pipe_crc_source source;
1658 int head, tail;
1659 wait_queue_head_t wq;
1660};
1661
1662struct i915_frontbuffer_tracking {
1663 struct mutex lock;
1664
1665
1666
1667
1668
1669 unsigned busy_bits;
1670 unsigned flip_bits;
1671};
1672
1673struct i915_wa_reg {
1674 u32 addr;
1675 u32 value;
1676
1677 u32 mask;
1678};
1679
1680#define I915_MAX_WA_REGS 16
1681
1682struct i915_workarounds {
1683 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1684 u32 count;
1685};
1686
1687struct i915_virtual_gpu {
1688 bool active;
1689};
1690
1691struct i915_execbuffer_params {
1692 struct drm_device *dev;
1693 struct drm_file *file;
1694 uint32_t dispatch_flags;
1695 uint32_t args_batch_start_offset;
1696 uint32_t batch_obj_vm_offset;
1697 struct intel_engine_cs *ring;
1698 struct drm_i915_gem_object *batch_obj;
1699 struct intel_context *ctx;
1700 struct drm_i915_gem_request *request;
1701};
1702
1703struct drm_i915_private {
1704 struct drm_device *dev;
1705 struct kmem_cache *objects;
1706 struct kmem_cache *vmas;
1707 struct kmem_cache *requests;
1708
1709 const struct intel_device_info info;
1710
1711 int relative_constants_mode;
1712
1713 void __iomem *regs;
1714
1715 struct intel_uncore uncore;
1716
1717 struct i915_virtual_gpu vgpu;
1718
1719 struct intel_csr csr;
1720
1721
1722 struct mutex csr_lock;
1723
1724 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1725
1726
1727
1728 struct mutex gmbus_mutex;
1729
1730
1731
1732
1733 uint32_t gpio_mmio_base;
1734
1735
1736 uint32_t mipi_mmio_base;
1737
1738 wait_queue_head_t gmbus_wait_queue;
1739
1740 struct pci_dev *bridge_dev;
1741 struct intel_engine_cs ring[I915_NUM_RINGS];
1742 struct drm_i915_gem_object *semaphore_obj;
1743 uint32_t last_seqno, next_seqno;
1744
1745 struct drm_dma_handle *status_page_dmah;
1746 struct resource mch_res;
1747
1748
1749 spinlock_t irq_lock;
1750
1751
1752 spinlock_t mmio_flip_lock;
1753
1754 bool display_irqs_enabled;
1755
1756
1757 struct pm_qos_request pm_qos;
1758
1759
1760 struct mutex sb_lock;
1761
1762
1763 union {
1764 u32 irq_mask;
1765 u32 de_irq_mask[I915_MAX_PIPES];
1766 };
1767 u32 gt_irq_mask;
1768 u32 pm_irq_mask;
1769 u32 pm_rps_events;
1770 u32 pipestat_irq_mask[I915_MAX_PIPES];
1771
1772 struct i915_hotplug hotplug;
1773 struct i915_fbc fbc;
1774 struct i915_drrs drrs;
1775 struct intel_opregion opregion;
1776 struct intel_vbt_data vbt;
1777
1778 bool preserve_bios_swizzle;
1779
1780
1781 struct intel_overlay *overlay;
1782
1783
1784 struct mutex backlight_lock;
1785
1786
1787 bool no_aux_handshake;
1788
1789
1790 struct mutex pps_mutex;
1791
1792 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES];
1793 int fence_reg_start;
1794 int num_fence_regs;
1795
1796 unsigned int fsb_freq, mem_freq, is_ddr3;
1797 unsigned int skl_boot_cdclk;
1798 unsigned int cdclk_freq, max_cdclk_freq;
1799 unsigned int hpll_freq;
1800
1801
1802
1803
1804
1805
1806
1807
1808 struct workqueue_struct *wq;
1809
1810
1811 struct drm_i915_display_funcs display;
1812
1813
1814 enum intel_pch pch_type;
1815 unsigned short pch_id;
1816
1817 unsigned long quirks;
1818
1819 enum modeset_restore modeset_restore;
1820 struct mutex modeset_restore_lock;
1821
1822 struct list_head vm_list;
1823 struct i915_gtt gtt;
1824
1825 struct i915_gem_mm mm;
1826 DECLARE_HASHTABLE(mm_structs, 7);
1827 struct mutex mm_lock;
1828
1829
1830
1831 struct sdvo_device_mapping sdvo_mappings[2];
1832
1833 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1834 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1835 wait_queue_head_t pending_flip_queue;
1836
1837#ifdef CONFIG_DEBUG_FS
1838 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1839#endif
1840
1841 int num_shared_dpll;
1842 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1843 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1844
1845 struct i915_workarounds workarounds;
1846
1847
1848 bool render_reclock_avail;
1849
1850 struct i915_frontbuffer_tracking fb_tracking;
1851
1852 u16 orig_clock;
1853
1854 bool mchbar_need_disable;
1855
1856 struct intel_l3_parity l3_parity;
1857
1858
1859 size_t ellc_size;
1860
1861
1862 struct intel_gen6_power_mgmt rps;
1863
1864
1865
1866 struct intel_ilk_power_mgmt ips;
1867
1868 struct i915_power_domains power_domains;
1869
1870 struct i915_psr psr;
1871
1872 struct i915_gpu_error gpu_error;
1873
1874 struct drm_i915_gem_object *vlv_pctx;
1875
1876#ifdef CONFIG_DRM_FBDEV_EMULATION
1877
1878 struct intel_fbdev *fbdev;
1879 struct work_struct fbdev_suspend_work;
1880#endif
1881
1882 struct drm_property *broadcast_rgb_property;
1883 struct drm_property *force_audio_property;
1884
1885
1886 struct i915_audio_component *audio_component;
1887 bool audio_component_registered;
1888
1889 uint32_t hw_context_size;
1890 struct list_head context_list;
1891
1892 u32 fdi_rx_config;
1893
1894 u32 chv_phy_control;
1895
1896 u32 suspend_count;
1897 struct i915_suspend_saved_registers regfile;
1898 struct vlv_s0ix_state vlv_s0ix_state;
1899
1900 struct {
1901
1902
1903
1904
1905
1906
1907 uint16_t pri_latency[5];
1908
1909 uint16_t spr_latency[5];
1910
1911 uint16_t cur_latency[5];
1912
1913
1914
1915
1916
1917 uint16_t skl_latency[8];
1918
1919
1920
1921
1922
1923
1924 struct skl_wm_values skl_results;
1925
1926
1927 union {
1928 struct ilk_wm_values hw;
1929 struct skl_wm_values skl_hw;
1930 struct vlv_wm_values vlv;
1931 };
1932
1933 uint8_t max_level;
1934 } wm;
1935
1936 struct i915_runtime_pm pm;
1937
1938
1939 struct {
1940 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1941 struct drm_i915_gem_execbuffer2 *args,
1942 struct list_head *vmas);
1943 int (*init_rings)(struct drm_device *dev);
1944 void (*cleanup_ring)(struct intel_engine_cs *ring);
1945 void (*stop_ring)(struct intel_engine_cs *ring);
1946 } gt;
1947
1948 bool edp_low_vswing;
1949
1950
1951
1952
1953
1954};
1955
1956static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1957{
1958 return dev->dev_private;
1959}
1960
1961static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1962{
1963 return to_i915(dev_get_drvdata(dev));
1964}
1965
1966
1967#define for_each_ring(ring__, dev_priv__, i__) \
1968 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1969 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1970
1971enum hdmi_force_audio {
1972 HDMI_AUDIO_OFF_DVI = -2,
1973 HDMI_AUDIO_OFF,
1974 HDMI_AUDIO_AUTO,
1975 HDMI_AUDIO_ON,
1976};
1977
1978#define I915_GTT_OFFSET_NONE ((u32)-1)
1979
1980struct drm_i915_gem_object_ops {
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994 int (*get_pages)(struct drm_i915_gem_object *);
1995 void (*put_pages)(struct drm_i915_gem_object *);
1996 int (*dmabuf_export)(struct drm_i915_gem_object *);
1997 void (*release)(struct drm_i915_gem_object *);
1998};
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
2009#define INTEL_FRONTBUFFER_BITS \
2010 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2011#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2012 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2013#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2014 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2015#define INTEL_FRONTBUFFER_SPRITE(pipe) \
2016 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2017#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2018 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2019#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2020 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2021
2022struct drm_i915_gem_object {
2023 struct drm_gem_object base;
2024
2025 const struct drm_i915_gem_object_ops *ops;
2026
2027
2028 struct list_head vma_list;
2029
2030
2031 struct drm_mm_node *stolen;
2032 struct list_head global_list;
2033
2034 struct list_head ring_list[I915_NUM_RINGS];
2035
2036 struct list_head obj_exec_link;
2037
2038 struct list_head batch_pool_link;
2039
2040
2041
2042
2043
2044
2045 unsigned int active:I915_NUM_RINGS;
2046
2047
2048
2049
2050
2051 unsigned int dirty:1;
2052
2053
2054
2055
2056
2057
2058 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2059
2060
2061
2062
2063 unsigned int madv:2;
2064
2065
2066
2067
2068 unsigned int tiling_mode:2;
2069
2070
2071
2072
2073
2074
2075
2076 unsigned int fence_dirty:1;
2077
2078
2079
2080
2081
2082 unsigned int map_and_fenceable:1;
2083
2084
2085
2086
2087
2088
2089 unsigned int fault_mappable:1;
2090
2091
2092
2093
2094
2095 unsigned long gt_ro:1;
2096 unsigned int cache_level:3;
2097 unsigned int cache_dirty:1;
2098
2099 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2100
2101 unsigned int pin_display;
2102
2103 struct sg_table *pages;
2104 int pages_pin_count;
2105 struct get_page {
2106 struct scatterlist *sg;
2107 int last;
2108 } get_page;
2109
2110
2111 void *dma_buf_vmapping;
2112 int vmapping_count;
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2125 struct drm_i915_gem_request *last_write_req;
2126
2127 struct drm_i915_gem_request *last_fenced_req;
2128
2129
2130 uint32_t stride;
2131
2132
2133 unsigned long framebuffer_references;
2134
2135
2136 unsigned long *bit_17;
2137
2138 union {
2139
2140 struct drm_dma_handle *phys_handle;
2141
2142 struct i915_gem_userptr {
2143 uintptr_t ptr;
2144 unsigned read_only :1;
2145 unsigned workers :4;
2146#define I915_GEM_USERPTR_MAX_WORKERS 15
2147
2148 struct i915_mm_struct *mm;
2149 struct i915_mmu_object *mmu_object;
2150 struct work_struct *work;
2151 } userptr;
2152 };
2153};
2154#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2155
2156void i915_gem_track_fb(struct drm_i915_gem_object *old,
2157 struct drm_i915_gem_object *new,
2158 unsigned frontbuffer_bits);
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174struct drm_i915_gem_request {
2175 struct kref ref;
2176
2177
2178 struct drm_i915_private *i915;
2179 struct intel_engine_cs *ring;
2180
2181
2182 uint32_t seqno;
2183
2184
2185 u32 head;
2186
2187
2188
2189
2190
2191
2192 u32 postfix;
2193
2194
2195 u32 tail;
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207 struct intel_context *ctx;
2208 struct intel_ringbuffer *ringbuf;
2209
2210
2211
2212 struct drm_i915_gem_object *batch_obj;
2213
2214
2215 unsigned long emitted_jiffies;
2216
2217
2218 struct list_head list;
2219
2220 struct drm_i915_file_private *file_priv;
2221
2222 struct list_head client_list;
2223
2224
2225 struct pid *pid;
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241 struct list_head execlist_link;
2242
2243
2244 int elsp_submitted;
2245
2246};
2247
2248int i915_gem_request_alloc(struct intel_engine_cs *ring,
2249 struct intel_context *ctx,
2250 struct drm_i915_gem_request **req_out);
2251void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2252void i915_gem_request_free(struct kref *req_ref);
2253int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2254 struct drm_file *file);
2255
2256static inline uint32_t
2257i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2258{
2259 return req ? req->seqno : 0;
2260}
2261
2262static inline struct intel_engine_cs *
2263i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2264{
2265 return req ? req->ring : NULL;
2266}
2267
2268static inline struct drm_i915_gem_request *
2269i915_gem_request_reference(struct drm_i915_gem_request *req)
2270{
2271 if (req)
2272 kref_get(&req->ref);
2273 return req;
2274}
2275
2276static inline void
2277i915_gem_request_unreference(struct drm_i915_gem_request *req)
2278{
2279 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2280 kref_put(&req->ref, i915_gem_request_free);
2281}
2282
2283static inline void
2284i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2285{
2286 struct drm_device *dev;
2287
2288 if (!req)
2289 return;
2290
2291 dev = req->ring->dev;
2292 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2293 mutex_unlock(&dev->struct_mutex);
2294}
2295
2296static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2297 struct drm_i915_gem_request *src)
2298{
2299 if (src)
2300 i915_gem_request_reference(src);
2301
2302 if (*pdst)
2303 i915_gem_request_unreference(*pdst);
2304
2305 *pdst = src;
2306}
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317struct drm_i915_cmd_descriptor {
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332 u32 flags;
2333#define CMD_DESC_FIXED (1<<0)
2334#define CMD_DESC_SKIP (1<<1)
2335#define CMD_DESC_REJECT (1<<2)
2336#define CMD_DESC_REGISTER (1<<3)
2337#define CMD_DESC_BITMASK (1<<4)
2338#define CMD_DESC_MASTER (1<<5)
2339
2340
2341
2342
2343
2344
2345 struct {
2346 u32 value;
2347 u32 mask;
2348 } cmd;
2349
2350
2351
2352
2353
2354
2355
2356
2357 union {
2358 u32 fixed;
2359 u32 mask;
2360 } length;
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371 struct {
2372 u32 offset;
2373 u32 mask;
2374 u32 step;
2375 } reg;
2376
2377#define MAX_CMD_DESC_BITMASKS 3
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389 struct {
2390 u32 offset;
2391 u32 mask;
2392 u32 expected;
2393 u32 condition_offset;
2394 u32 condition_mask;
2395 } bits[MAX_CMD_DESC_BITMASKS];
2396};
2397
2398
2399
2400
2401
2402
2403
2404struct drm_i915_cmd_table {
2405 const struct drm_i915_cmd_descriptor *table;
2406 int count;
2407};
2408
2409
2410#define __I915__(p) ({ \
2411 struct drm_i915_private *__p; \
2412 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2413 __p = (struct drm_i915_private *)p; \
2414 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2415 __p = to_i915((struct drm_device *)p); \
2416 else \
2417 BUILD_BUG(); \
2418 __p; \
2419})
2420#define INTEL_INFO(p) (&__I915__(p)->info)
2421#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2422#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2423
2424#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2425#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2426#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2427#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2428#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2429#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2430#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2431#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2432#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2433#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2434#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2435#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2436#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2437#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2438#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2439#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2440#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2441#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2442#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2443 INTEL_DEVID(dev) == 0x0152 || \
2444 INTEL_DEVID(dev) == 0x015a)
2445#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2446#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2447#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2448#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2449#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2450#define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2451#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2452#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2453 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2454#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2455 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2456 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2457 (INTEL_DEVID(dev) & 0xf) == 0xe))
2458
2459#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2460 (INTEL_DEVID(dev) & 0xf) == 0xe)
2461#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2462 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2463#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2464 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2465#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2466 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2467
2468#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2469 INTEL_DEVID(dev) == 0x0A1E)
2470#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2471 INTEL_DEVID(dev) == 0x1913 || \
2472 INTEL_DEVID(dev) == 0x1916 || \
2473 INTEL_DEVID(dev) == 0x1921 || \
2474 INTEL_DEVID(dev) == 0x1926)
2475#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2476 INTEL_DEVID(dev) == 0x1915 || \
2477 INTEL_DEVID(dev) == 0x191E)
2478#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2479
2480#define SKL_REVID_A0 (0x0)
2481#define SKL_REVID_B0 (0x1)
2482#define SKL_REVID_C0 (0x2)
2483#define SKL_REVID_D0 (0x3)
2484#define SKL_REVID_E0 (0x4)
2485#define SKL_REVID_F0 (0x5)
2486
2487#define BXT_REVID_A0 (0x0)
2488#define BXT_REVID_B0 (0x3)
2489#define BXT_REVID_C0 (0x6)
2490
2491
2492
2493
2494
2495
2496
2497#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2498#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2499#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2500#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2501#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2502#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2503#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2504#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2505
2506#define RENDER_RING (1<<RCS)
2507#define BSD_RING (1<<VCS)
2508#define BLT_RING (1<<BCS)
2509#define VEBOX_RING (1<<VECS)
2510#define BSD2_RING (1<<VCS2)
2511#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2512#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2513#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2514#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2515#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2516#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2517 __I915__(dev)->ellc_size)
2518#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2519
2520#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2521#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2522#define USES_PPGTT(dev) (i915.enable_ppgtt)
2523#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2524
2525#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2526#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2527
2528
2529#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2530
2531
2532
2533
2534
2535
2536#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2537#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2538
2539
2540
2541
2542#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2543 IS_I915GM(dev)))
2544#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2545#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2546
2547#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2548#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2549#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2550
2551#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2552
2553#define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2554 INTEL_INFO(dev)->gen >= 9)
2555
2556#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2557#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2558#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2559 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2560 IS_SKYLAKE(dev))
2561#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2562 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2563 IS_SKYLAKE(dev))
2564#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2565#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2566
2567#define HAS_CSR(dev) (IS_SKYLAKE(dev))
2568
2569#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2570 INTEL_INFO(dev)->gen >= 8)
2571
2572#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2573 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
2574
2575#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2576#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2577#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2578#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2579#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2580#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2581#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2582#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2583
2584#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2585#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2586#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2587#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2588#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2589#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2590#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2591
2592#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2593
2594
2595#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2596#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2597
2598#define GT_FREQUENCY_MULTIPLIER 50
2599#define GEN9_FREQ_SCALER 3
2600
2601#include "i915_trace.h"
2602
2603extern const struct drm_ioctl_desc i915_ioctls[];
2604extern int i915_max_ioctl;
2605
2606extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2607extern int i915_resume_legacy(struct drm_device *dev);
2608
2609
2610struct i915_params {
2611 int modeset;
2612 int panel_ignore_lid;
2613 int semaphores;
2614 int lvds_channel_mode;
2615 int panel_use_ssc;
2616 int vbt_sdvo_panel_type;
2617 int enable_rc6;
2618 int enable_fbc;
2619 int enable_ppgtt;
2620 int enable_execlists;
2621 int enable_psr;
2622 unsigned int preliminary_hw_support;
2623 int disable_power_well;
2624 int enable_ips;
2625 int invert_brightness;
2626 int enable_cmd_parser;
2627
2628 bool enable_hangcheck;
2629 bool fastboot;
2630 bool prefault_disable;
2631 bool load_detect_test;
2632 bool reset;
2633 bool disable_display;
2634 bool disable_vtd_wa;
2635 bool enable_guc_submission;
2636 int guc_log_level;
2637 int use_mmio_flip;
2638 int mmio_debug;
2639 bool verbose_state_checks;
2640 int edp_vswing;
2641};
2642extern struct i915_params i915 __read_mostly;
2643
2644
2645extern int i915_driver_load(struct drm_device *, unsigned long flags);
2646extern int i915_driver_unload(struct drm_device *);
2647extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2648extern void i915_driver_lastclose(struct drm_device * dev);
2649extern void i915_driver_preclose(struct drm_device *dev,
2650 struct drm_file *file);
2651extern void i915_driver_postclose(struct drm_device *dev,
2652 struct drm_file *file);
2653#ifdef CONFIG_COMPAT
2654extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2655 unsigned long arg);
2656#endif
2657extern int intel_gpu_reset(struct drm_device *dev);
2658extern bool intel_has_gpu_reset(struct drm_device *dev);
2659extern int i915_reset(struct drm_device *dev);
2660extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2661extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2662extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2663extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2664int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2665void i915_firmware_load_error_print(const char *fw_path, int err);
2666
2667
2668void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2669void intel_hpd_init(struct drm_i915_private *dev_priv);
2670void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2671void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2672bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2673
2674
2675void i915_queue_hangcheck(struct drm_device *dev);
2676__printf(3, 4)
2677void i915_handle_error(struct drm_device *dev, bool wedged,
2678 const char *fmt, ...);
2679
2680extern void intel_irq_init(struct drm_i915_private *dev_priv);
2681int intel_irq_install(struct drm_i915_private *dev_priv);
2682void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2683
2684extern void intel_uncore_sanitize(struct drm_device *dev);
2685extern void intel_uncore_early_sanitize(struct drm_device *dev,
2686 bool restore_forcewake);
2687extern void intel_uncore_init(struct drm_device *dev);
2688extern void intel_uncore_check_errors(struct drm_device *dev);
2689extern void intel_uncore_fini(struct drm_device *dev);
2690extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2691const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2692void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2693 enum forcewake_domains domains);
2694void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2695 enum forcewake_domains domains);
2696
2697
2698
2699void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2700 enum forcewake_domains domains);
2701void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2702 enum forcewake_domains domains);
2703void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2704static inline bool intel_vgpu_active(struct drm_device *dev)
2705{
2706 return to_i915(dev)->vgpu.active;
2707}
2708
2709void
2710i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2711 u32 status_mask);
2712
2713void
2714i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2715 u32 status_mask);
2716
2717void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2718void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2719void
2720ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2721void
2722ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2723void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2724 uint32_t interrupt_mask,
2725 uint32_t enabled_irq_mask);
2726#define ibx_enable_display_interrupt(dev_priv, bits) \
2727 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2728#define ibx_disable_display_interrupt(dev_priv, bits) \
2729 ibx_display_interrupt_update((dev_priv), (bits), 0)
2730
2731
2732int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2733 struct drm_file *file_priv);
2734int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2735 struct drm_file *file_priv);
2736int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2737 struct drm_file *file_priv);
2738int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2739 struct drm_file *file_priv);
2740int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2741 struct drm_file *file_priv);
2742int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2743 struct drm_file *file_priv);
2744int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2745 struct drm_file *file_priv);
2746void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2747 struct drm_i915_gem_request *req);
2748void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2749int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2750 struct drm_i915_gem_execbuffer2 *args,
2751 struct list_head *vmas);
2752int i915_gem_execbuffer(struct drm_device *dev, void *data,
2753 struct drm_file *file_priv);
2754int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2755 struct drm_file *file_priv);
2756int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2757 struct drm_file *file_priv);
2758int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2759 struct drm_file *file);
2760int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2761 struct drm_file *file);
2762int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2763 struct drm_file *file_priv);
2764int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2765 struct drm_file *file_priv);
2766int i915_gem_set_tiling(struct drm_device *dev, void *data,
2767 struct drm_file *file_priv);
2768int i915_gem_get_tiling(struct drm_device *dev, void *data,
2769 struct drm_file *file_priv);
2770int i915_gem_init_userptr(struct drm_device *dev);
2771int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2772 struct drm_file *file);
2773int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2774 struct drm_file *file_priv);
2775int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2776 struct drm_file *file_priv);
2777void i915_gem_load(struct drm_device *dev);
2778void *i915_gem_object_alloc(struct drm_device *dev);
2779void i915_gem_object_free(struct drm_i915_gem_object *obj);
2780void i915_gem_object_init(struct drm_i915_gem_object *obj,
2781 const struct drm_i915_gem_object_ops *ops);
2782struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2783 size_t size);
2784struct drm_i915_gem_object *i915_gem_object_create_from_data(
2785 struct drm_device *dev, const void *data, size_t size);
2786void i915_init_vm(struct drm_i915_private *dev_priv,
2787 struct i915_address_space *vm);
2788void i915_gem_free_object(struct drm_gem_object *obj);
2789void i915_gem_vma_destroy(struct i915_vma *vma);
2790
2791
2792#define PIN_MAPPABLE (1<<0)
2793#define PIN_NONBLOCK (1<<1)
2794#define PIN_GLOBAL (1<<2)
2795#define PIN_OFFSET_BIAS (1<<3)
2796#define PIN_USER (1<<4)
2797#define PIN_UPDATE (1<<5)
2798#define PIN_OFFSET_MASK (~4095)
2799int __must_check
2800i915_gem_object_pin(struct drm_i915_gem_object *obj,
2801 struct i915_address_space *vm,
2802 uint32_t alignment,
2803 uint64_t flags);
2804int __must_check
2805i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2806 const struct i915_ggtt_view *view,
2807 uint32_t alignment,
2808 uint64_t flags);
2809
2810int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2811 u32 flags);
2812int __must_check i915_vma_unbind(struct i915_vma *vma);
2813int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2814void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2815void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2816
2817int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2818 int *needs_clflush);
2819
2820int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2821
2822static inline int __sg_page_count(struct scatterlist *sg)
2823{
2824 return sg->length >> PAGE_SHIFT;
2825}
2826
2827static inline struct page *
2828i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2829{
2830 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2831 return NULL;
2832
2833 if (n < obj->get_page.last) {
2834 obj->get_page.sg = obj->pages->sgl;
2835 obj->get_page.last = 0;
2836 }
2837
2838 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2839 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2840 if (unlikely(sg_is_chain(obj->get_page.sg)))
2841 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2842 }
2843
2844 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2845}
2846
2847static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2848{
2849 BUG_ON(obj->pages == NULL);
2850 obj->pages_pin_count++;
2851}
2852static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2853{
2854 BUG_ON(obj->pages_pin_count == 0);
2855 obj->pages_pin_count--;
2856}
2857
2858int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2859int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2860 struct intel_engine_cs *to,
2861 struct drm_i915_gem_request **to_req);
2862void i915_vma_move_to_active(struct i915_vma *vma,
2863 struct drm_i915_gem_request *req);
2864int i915_gem_dumb_create(struct drm_file *file_priv,
2865 struct drm_device *dev,
2866 struct drm_mode_create_dumb *args);
2867int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2868 uint32_t handle, uint64_t *offset);
2869
2870
2871
2872static inline bool
2873i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2874{
2875 return (int32_t)(seq1 - seq2) >= 0;
2876}
2877
2878static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2879 bool lazy_coherency)
2880{
2881 u32 seqno;
2882
2883 BUG_ON(req == NULL);
2884
2885 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2886
2887 return i915_seqno_passed(seqno, req->seqno);
2888}
2889
2890int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2891int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2892
2893struct drm_i915_gem_request *
2894i915_gem_find_active_request(struct intel_engine_cs *ring);
2895
2896bool i915_gem_retire_requests(struct drm_device *dev);
2897void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2898int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2899 bool interruptible);
2900
2901static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2902{
2903 return unlikely(atomic_read(&error->reset_counter)
2904 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2905}
2906
2907static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2908{
2909 return atomic_read(&error->reset_counter) & I915_WEDGED;
2910}
2911
2912static inline u32 i915_reset_count(struct i915_gpu_error *error)
2913{
2914 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2915}
2916
2917static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2918{
2919 return dev_priv->gpu_error.stop_rings == 0 ||
2920 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2921}
2922
2923static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2924{
2925 return dev_priv->gpu_error.stop_rings == 0 ||
2926 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2927}
2928
2929void i915_gem_reset(struct drm_device *dev);
2930bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2931int __must_check i915_gem_init(struct drm_device *dev);
2932int i915_gem_init_rings(struct drm_device *dev);
2933int __must_check i915_gem_init_hw(struct drm_device *dev);
2934int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
2935void i915_gem_init_swizzling(struct drm_device *dev);
2936void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2937int __must_check i915_gpu_idle(struct drm_device *dev);
2938int __must_check i915_gem_suspend(struct drm_device *dev);
2939void __i915_add_request(struct drm_i915_gem_request *req,
2940 struct drm_i915_gem_object *batch_obj,
2941 bool flush_caches);
2942#define i915_add_request(req) \
2943 __i915_add_request(req, NULL, true)
2944#define i915_add_request_no_flush(req) \
2945 __i915_add_request(req, NULL, false)
2946int __i915_wait_request(struct drm_i915_gem_request *req,
2947 unsigned reset_counter,
2948 bool interruptible,
2949 s64 *timeout,
2950 struct intel_rps_client *rps);
2951int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2952int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2953int __must_check
2954i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
2955 bool readonly);
2956int __must_check
2957i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2958 bool write);
2959int __must_check
2960i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2961int __must_check
2962i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2963 u32 alignment,
2964 struct intel_engine_cs *pipelined,
2965 struct drm_i915_gem_request **pipelined_request,
2966 const struct i915_ggtt_view *view);
2967void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2968 const struct i915_ggtt_view *view);
2969int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2970 int align);
2971int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2972void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2973
2974uint32_t
2975i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2976uint32_t
2977i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2978 int tiling_mode, bool fenced);
2979
2980int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2981 enum i915_cache_level cache_level);
2982
2983struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2984 struct dma_buf *dma_buf);
2985
2986struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2987 struct drm_gem_object *gem_obj, int flags);
2988
2989unsigned long
2990i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
2991 const struct i915_ggtt_view *view);
2992unsigned long
2993i915_gem_obj_offset(struct drm_i915_gem_object *o,
2994 struct i915_address_space *vm);
2995static inline unsigned long
2996i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
2997{
2998 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
2999}
3000
3001bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3002bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3003 const struct i915_ggtt_view *view);
3004bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3005 struct i915_address_space *vm);
3006
3007unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3008 struct i915_address_space *vm);
3009struct i915_vma *
3010i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3011 struct i915_address_space *vm);
3012struct i915_vma *
3013i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3014 const struct i915_ggtt_view *view);
3015
3016struct i915_vma *
3017i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3018 struct i915_address_space *vm);
3019struct i915_vma *
3020i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3021 const struct i915_ggtt_view *view);
3022
3023static inline struct i915_vma *
3024i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3025{
3026 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3027}
3028bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3029
3030
3031#define i915_obj_to_ggtt(obj) \
3032 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3033static inline bool i915_is_ggtt(struct i915_address_space *vm)
3034{
3035 struct i915_address_space *ggtt =
3036 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3037 return vm == ggtt;
3038}
3039
3040static inline struct i915_hw_ppgtt *
3041i915_vm_to_ppgtt(struct i915_address_space *vm)
3042{
3043 WARN_ON(i915_is_ggtt(vm));
3044
3045 return container_of(vm, struct i915_hw_ppgtt, base);
3046}
3047
3048
3049static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3050{
3051 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3052}
3053
3054static inline unsigned long
3055i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3056{
3057 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3058}
3059
3060static inline int __must_check
3061i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3062 uint32_t alignment,
3063 unsigned flags)
3064{
3065 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3066 alignment, flags | PIN_GLOBAL);
3067}
3068
3069static inline int
3070i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3071{
3072 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3073}
3074
3075void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3076 const struct i915_ggtt_view *view);
3077static inline void
3078i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3079{
3080 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3081}
3082
3083
3084int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3085int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3086
3087bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3088void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3089
3090void i915_gem_restore_fences(struct drm_device *dev);
3091
3092void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3093void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3094void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3095
3096
3097int __must_check i915_gem_context_init(struct drm_device *dev);
3098void i915_gem_context_fini(struct drm_device *dev);
3099void i915_gem_context_reset(struct drm_device *dev);
3100int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3101int i915_gem_context_enable(struct drm_i915_gem_request *req);
3102void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3103int i915_switch_context(struct drm_i915_gem_request *req);
3104struct intel_context *
3105i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3106void i915_gem_context_free(struct kref *ctx_ref);
3107struct drm_i915_gem_object *
3108i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3109static inline void i915_gem_context_reference(struct intel_context *ctx)
3110{
3111 kref_get(&ctx->ref);
3112}
3113
3114static inline void i915_gem_context_unreference(struct intel_context *ctx)
3115{
3116 kref_put(&ctx->ref, i915_gem_context_free);
3117}
3118
3119static inline bool i915_gem_context_is_default(const struct intel_context *c)
3120{
3121 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3122}
3123
3124int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3125 struct drm_file *file);
3126int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3127 struct drm_file *file);
3128int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3129 struct drm_file *file_priv);
3130int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3131 struct drm_file *file_priv);
3132
3133
3134int __must_check i915_gem_evict_something(struct drm_device *dev,
3135 struct i915_address_space *vm,
3136 int min_size,
3137 unsigned alignment,
3138 unsigned cache_level,
3139 unsigned long start,
3140 unsigned long end,
3141 unsigned flags);
3142int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3143int i915_gem_evict_everything(struct drm_device *dev);
3144
3145
3146static inline void i915_gem_chipset_flush(struct drm_device *dev)
3147{
3148 if (INTEL_INFO(dev)->gen < 6)
3149 intel_gtt_chipset_flush();
3150}
3151
3152
3153int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3154 struct drm_mm_node *node, u64 size,
3155 unsigned alignment);
3156void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3157 struct drm_mm_node *node);
3158int i915_gem_init_stolen(struct drm_device *dev);
3159void i915_gem_cleanup_stolen(struct drm_device *dev);
3160struct drm_i915_gem_object *
3161i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3162struct drm_i915_gem_object *
3163i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3164 u32 stolen_offset,
3165 u32 gtt_offset,
3166 u32 size);
3167
3168
3169unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3170 long target,
3171 unsigned flags);
3172#define I915_SHRINK_PURGEABLE 0x1
3173#define I915_SHRINK_UNBOUND 0x2
3174#define I915_SHRINK_BOUND 0x4
3175unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3176void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3177
3178
3179
3180static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3181{
3182 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3183
3184 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3185 obj->tiling_mode != I915_TILING_NONE;
3186}
3187
3188
3189#if WATCH_LISTS
3190int i915_verify_lists(struct drm_device *dev);
3191#else
3192#define i915_verify_lists(dev) 0
3193#endif
3194
3195
3196int i915_debugfs_init(struct drm_minor *minor);
3197void i915_debugfs_cleanup(struct drm_minor *minor);
3198#ifdef CONFIG_DEBUG_FS
3199int i915_debugfs_connector_add(struct drm_connector *connector);
3200void intel_display_crc_init(struct drm_device *dev);
3201#else
3202static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3203{ return 0; }
3204static inline void intel_display_crc_init(struct drm_device *dev) {}
3205#endif
3206
3207
3208__printf(2, 3)
3209void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3210int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3211 const struct i915_error_state_file_priv *error);
3212int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3213 struct drm_i915_private *i915,
3214 size_t count, loff_t pos);
3215static inline void i915_error_state_buf_release(
3216 struct drm_i915_error_state_buf *eb)
3217{
3218 kfree(eb->buf);
3219}
3220void i915_capture_error_state(struct drm_device *dev, bool wedge,
3221 const char *error_msg);
3222void i915_error_state_get(struct drm_device *dev,
3223 struct i915_error_state_file_priv *error_priv);
3224void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3225void i915_destroy_error_state(struct drm_device *dev);
3226
3227void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3228const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3229
3230
3231int i915_cmd_parser_get_version(void);
3232int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3233void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3234bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3235int i915_parse_cmds(struct intel_engine_cs *ring,
3236 struct drm_i915_gem_object *batch_obj,
3237 struct drm_i915_gem_object *shadow_batch_obj,
3238 u32 batch_start_offset,
3239 u32 batch_len,
3240 bool is_master);
3241
3242
3243extern int i915_save_state(struct drm_device *dev);
3244extern int i915_restore_state(struct drm_device *dev);
3245
3246
3247void i915_setup_sysfs(struct drm_device *dev_priv);
3248void i915_teardown_sysfs(struct drm_device *dev_priv);
3249
3250
3251extern int intel_setup_gmbus(struct drm_device *dev);
3252extern void intel_teardown_gmbus(struct drm_device *dev);
3253extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3254 unsigned int pin);
3255
3256extern struct i2c_adapter *
3257intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3258extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3259extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3260static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3261{
3262 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3263}
3264extern void intel_i2c_reset(struct drm_device *dev);
3265
3266
3267#ifdef CONFIG_ACPI
3268extern int intel_opregion_setup(struct drm_device *dev);
3269extern void intel_opregion_init(struct drm_device *dev);
3270extern void intel_opregion_fini(struct drm_device *dev);
3271extern void intel_opregion_asle_intr(struct drm_device *dev);
3272extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3273 bool enable);
3274extern int intel_opregion_notify_adapter(struct drm_device *dev,
3275 pci_power_t state);
3276#else
3277static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3278static inline void intel_opregion_init(struct drm_device *dev) { return; }
3279static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3280static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3281static inline int
3282intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3283{
3284 return 0;
3285}
3286static inline int
3287intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3288{
3289 return 0;
3290}
3291#endif
3292
3293
3294#ifdef CONFIG_ACPI
3295extern void intel_register_dsm_handler(void);
3296extern void intel_unregister_dsm_handler(void);
3297#else
3298static inline void intel_register_dsm_handler(void) { return; }
3299static inline void intel_unregister_dsm_handler(void) { return; }
3300#endif
3301
3302
3303extern void intel_modeset_init_hw(struct drm_device *dev);
3304extern void intel_modeset_init(struct drm_device *dev);
3305extern void intel_modeset_gem_init(struct drm_device *dev);
3306extern void intel_modeset_cleanup(struct drm_device *dev);
3307extern void intel_connector_unregister(struct intel_connector *);
3308extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3309extern void intel_display_resume(struct drm_device *dev);
3310extern void i915_redisable_vga(struct drm_device *dev);
3311extern void i915_redisable_vga_power_on(struct drm_device *dev);
3312extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3313extern void intel_init_pch_refclk(struct drm_device *dev);
3314extern void intel_set_rps(struct drm_device *dev, u8 val);
3315extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3316 bool enable);
3317extern void intel_detect_pch(struct drm_device *dev);
3318extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3319extern int intel_enable_rc6(const struct drm_device *dev);
3320
3321extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3322int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3323 struct drm_file *file);
3324int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3325 struct drm_file *file);
3326
3327
3328extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3329extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3330 struct intel_overlay_error_state *error);
3331
3332extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3333extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3334 struct drm_device *dev,
3335 struct intel_display_error_state *error);
3336
3337int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3338int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3339
3340
3341u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3342void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3343u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3344u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3345void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3346u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3347void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3348u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3349void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3350u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3351void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3352u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3353void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3354u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3355void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3356u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3357 enum intel_sbi_destination destination);
3358void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3359 enum intel_sbi_destination destination);
3360u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3361void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3362
3363int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3364int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3365
3366#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3367#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3368
3369#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3370#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3371#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3372#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3373
3374#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3375#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3376#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3377#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3378
3379
3380
3381
3382
3383
3384
3385#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3386#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3387
3388#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3389 u32 upper, lower, old_upper, loop = 0; \
3390 upper = I915_READ(upper_reg); \
3391 do { \
3392 old_upper = upper; \
3393 lower = I915_READ(lower_reg); \
3394 upper = I915_READ(upper_reg); \
3395 } while (upper != old_upper && loop++ < 2); \
3396 (u64)upper << 32 | lower; })
3397
3398#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3399#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3400
3401
3402
3403
3404
3405
3406
3407
3408#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3409#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3410#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3411
3412
3413#define INTEL_BROADCAST_RGB_AUTO 0
3414#define INTEL_BROADCAST_RGB_FULL 1
3415#define INTEL_BROADCAST_RGB_LIMITED 2
3416
3417static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3418{
3419 if (IS_VALLEYVIEW(dev))
3420 return VLV_VGACNTRL;
3421 else if (INTEL_INFO(dev)->gen >= 5)
3422 return CPU_VGACNTRL;
3423 else
3424 return VGACNTRL;
3425}
3426
3427static inline void __user *to_user_ptr(u64 address)
3428{
3429 return (void __user *)(uintptr_t)address;
3430}
3431
3432static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3433{
3434 unsigned long j = msecs_to_jiffies(m);
3435
3436 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3437}
3438
3439static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3440{
3441 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3442}
3443
3444static inline unsigned long
3445timespec_to_jiffies_timeout(const struct timespec *value)
3446{
3447 unsigned long j = timespec_to_jiffies(value);
3448
3449 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3450}
3451
3452
3453
3454
3455
3456
3457
3458static inline void
3459wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3460{
3461 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3462
3463
3464
3465
3466
3467 tmp_jiffies = jiffies;
3468 target_jiffies = timestamp_jiffies +
3469 msecs_to_jiffies_timeout(to_wait_ms);
3470
3471 if (time_after(target_jiffies, tmp_jiffies)) {
3472 remaining_jiffies = target_jiffies - tmp_jiffies;
3473 while (remaining_jiffies)
3474 remaining_jiffies =
3475 schedule_timeout_uninterruptible(remaining_jiffies);
3476 }
3477}
3478
3479static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3480 struct drm_i915_gem_request *req)
3481{
3482 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3483 i915_gem_request_assign(&ring->trace_irq_req, req);
3484}
3485
3486#endif
3487