LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#include "nv50.h"
  25#include "outp.h"
  26
  27#include <core/client.h>
  28#include <subdev/timer.h>
  29
  30#include <nvif/class.h>
  31#include <nvif/unpack.h>
  32
  33int
  34nv50_sor_power(NV50_DISP_MTHD_V1)
  35{
  36        struct nvkm_device *device = disp->base.engine.subdev.device;
  37        union {
  38                struct nv50_disp_sor_pwr_v0 v0;
  39        } *args = data;
  40        const u32 soff = outp->or * 0x800;
  41        u32 stat;
  42        int ret;
  43
  44        nvif_ioctl(object, "disp sor pwr size %d\n", size);
  45        if (nvif_unpack(args->v0, 0, 0, false)) {
  46                nvif_ioctl(object, "disp sor pwr vers %d state %d\n",
  47                           args->v0.version, args->v0.state);
  48                stat = !!args->v0.state;
  49        } else
  50                return ret;
  51
  52
  53        nvkm_msec(device, 2000,
  54                if (!(nvkm_rd32(device, 0x61c004 + soff) & 0x80000000))
  55                        break;
  56        );
  57        nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000000 | stat);
  58        nvkm_msec(device, 2000,
  59                if (!(nvkm_rd32(device, 0x61c004 + soff) & 0x80000000))
  60                        break;
  61        );
  62        nvkm_msec(device, 2000,
  63                if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000))
  64                        break;
  65        );
  66        return 0;
  67}
  68
  69static const struct nvkm_output_func
  70nv50_sor_output_func = {
  71};
  72
  73int
  74nv50_sor_output_new(struct nvkm_disp *disp, int index,
  75                    struct dcb_output *dcbE, struct nvkm_output **poutp)
  76{
  77        return nvkm_output_new_(&nv50_sor_output_func, disp,
  78                                index, dcbE, poutp);
  79}
  80