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24#include "ram.h"
25
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30
31
32#define NOTE00(a) 1
33
34int
35nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts)
36{
37 int pd, lf, xd, vh, vr, vo, l3;
38 int WL, CL, WR, at[2], dt, ds;
39 int rq = ram->freq < 1000000;
40
41 switch (ram->next->bios.ramcfg_ver) {
42 case 0x11:
43 pd = ram->next->bios.ramcfg_11_01_80;
44 lf = ram->next->bios.ramcfg_11_01_40;
45 xd = !ram->next->bios.ramcfg_11_01_20;
46 vh = ram->next->bios.ramcfg_11_02_10;
47 vr = ram->next->bios.ramcfg_11_02_04;
48 vo = ram->next->bios.ramcfg_11_06;
49 l3 = !ram->next->bios.ramcfg_11_07_02;
50 break;
51 default:
52 return -ENOSYS;
53 }
54
55 switch (ram->next->bios.timing_ver) {
56 case 0x20:
57 WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
58 CL = (ram->next->bios.timing[1] & 0x0000001f);
59 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
60 at[0] = ram->next->bios.timing_20_2e_c0;
61 at[1] = ram->next->bios.timing_20_2e_30;
62 dt = ram->next->bios.timing_20_2e_03;
63 ds = ram->next->bios.timing_20_2f_03;
64 break;
65 default:
66 return -ENOSYS;
67 }
68
69 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35)
70 return -EINVAL;
71 CL -= 5;
72 WR -= 4;
73
74 ram->mr[0] &= ~0xf7f;
75 ram->mr[0] |= (WR & 0x0f) << 8;
76 ram->mr[0] |= (CL & 0x0f) << 3;
77 ram->mr[0] |= (WL & 0x07) << 0;
78
79 ram->mr[1] &= ~0x0bf;
80 ram->mr[1] |= (xd & 0x01) << 7;
81 ram->mr[1] |= (at[0] & 0x03) << 4;
82 ram->mr[1] |= (dt & 0x03) << 2;
83 ram->mr[1] |= (ds & 0x03) << 0;
84
85
86
87
88 ram->mr1_nuts = ram->mr[1];
89 if (nuts) {
90 ram->mr[1] &= ~0x030;
91 ram->mr[1] |= (at[1] & 0x03) << 4;
92 }
93
94 ram->mr[3] &= ~0x020;
95 ram->mr[3] |= (rq & 0x01) << 5;
96
97 ram->mr[5] &= ~0x004;
98 ram->mr[5] |= (l3 << 2);
99
100 if (!vo)
101 vo = (ram->mr[6] & 0xff0) >> 4;
102 if (ram->mr[6] & 0x001)
103 pd = 1;
104 ram->mr[6] &= ~0xff1;
105 ram->mr[6] |= (vo & 0xff) << 4;
106 ram->mr[6] |= (pd & 0x01) << 0;
107
108 if (NOTE00(vr)) {
109 ram->mr[7] &= ~0x300;
110 ram->mr[7] |= (vr & 0x03) << 8;
111 }
112 ram->mr[7] &= ~0x088;
113 ram->mr[7] |= (vh & 0x01) << 7;
114 ram->mr[7] |= (lf & 0x01) << 3;
115
116 ram->mr[8] &= ~0x003;
117 ram->mr[8] |= (WR & 0x10) >> 3;
118 ram->mr[8] |= (CL & 0x10) >> 4;
119 return 0;
120}
121