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27#include <linux/hdmi.h>
28#include <drm/drmP.h>
29#include <drm/radeon_drm.h>
30#include "radeon.h"
31#include "radeon_asic.h"
32#include "radeon_audio.h"
33#include "evergreend.h"
34#include "atom.h"
35
36
37void dce4_audio_enable(struct radeon_device *rdev,
38 struct r600_audio_pin *pin,
39 u8 enable_mask)
40{
41 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
42
43 if (!pin)
44 return;
45
46 if (enable_mask) {
47 tmp |= AUDIO_ENABLED;
48 if (enable_mask & 1)
49 tmp |= PIN0_AUDIO_ENABLED;
50 if (enable_mask & 2)
51 tmp |= PIN1_AUDIO_ENABLED;
52 if (enable_mask & 4)
53 tmp |= PIN2_AUDIO_ENABLED;
54 if (enable_mask & 8)
55 tmp |= PIN3_AUDIO_ENABLED;
56 } else {
57 tmp &= ~(AUDIO_ENABLED |
58 PIN0_AUDIO_ENABLED |
59 PIN1_AUDIO_ENABLED |
60 PIN2_AUDIO_ENABLED |
61 PIN3_AUDIO_ENABLED);
62 }
63
64 WREG32(AZ_HOT_PLUG_CONTROL, tmp);
65}
66
67void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
68 const struct radeon_hdmi_acr *acr)
69{
70 struct drm_device *dev = encoder->dev;
71 struct radeon_device *rdev = dev->dev_private;
72 int bpc = 8;
73
74 if (encoder->crtc) {
75 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
76 bpc = radeon_crtc->bpc;
77 }
78
79 if (bpc > 8)
80 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
81 HDMI_ACR_AUTO_SEND);
82 else
83 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
84 HDMI_ACR_SOURCE |
85 HDMI_ACR_AUTO_SEND);
86
87 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
88 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
89
90 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
91 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
92
93 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
94 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
95}
96
97void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
98 struct drm_connector *connector, struct drm_display_mode *mode)
99{
100 struct radeon_device *rdev = encoder->dev->dev_private;
101 u32 tmp = 0;
102
103 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
104 if (connector->latency_present[1])
105 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
106 AUDIO_LIPSYNC(connector->audio_latency[1]);
107 else
108 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
109 } else {
110 if (connector->latency_present[0])
111 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
112 AUDIO_LIPSYNC(connector->audio_latency[0]);
113 else
114 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
115 }
116 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
117}
118
119void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
120 u8 *sadb, int sad_count)
121{
122 struct radeon_device *rdev = encoder->dev->dev_private;
123 u32 tmp;
124
125
126 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
127 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
128
129 tmp |= HDMI_CONNECTION;
130 if (sad_count)
131 tmp |= SPEAKER_ALLOCATION(sadb[0]);
132 else
133 tmp |= SPEAKER_ALLOCATION(5);
134 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
135}
136
137void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
138 u8 *sadb, int sad_count)
139{
140 struct radeon_device *rdev = encoder->dev->dev_private;
141 u32 tmp;
142
143
144 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
145 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
146
147 tmp |= DP_CONNECTION;
148 if (sad_count)
149 tmp |= SPEAKER_ALLOCATION(sadb[0]);
150 else
151 tmp |= SPEAKER_ALLOCATION(5);
152 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
153}
154
155void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
156 struct cea_sad *sads, int sad_count)
157{
158 int i;
159 struct radeon_device *rdev = encoder->dev->dev_private;
160 static const u16 eld_reg_to_type[][2] = {
161 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
162 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
163 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
164 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
165 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
166 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
167 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
168 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
169 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
170 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
171 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
172 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
173 };
174
175 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
176 u32 value = 0;
177 u8 stereo_freqs = 0;
178 int max_channels = -1;
179 int j;
180
181 for (j = 0; j < sad_count; j++) {
182 struct cea_sad *sad = &sads[j];
183
184 if (sad->format == eld_reg_to_type[i][1]) {
185 if (sad->channels > max_channels) {
186 value = MAX_CHANNELS(sad->channels) |
187 DESCRIPTOR_BYTE_2(sad->byte2) |
188 SUPPORTED_FREQUENCIES(sad->freq);
189 max_channels = sad->channels;
190 }
191
192 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
193 stereo_freqs |= sad->freq;
194 else
195 break;
196 }
197 }
198
199 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
200
201 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
202 }
203}
204
205
206
207
208void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,
209 unsigned char *buffer, size_t size)
210{
211 uint8_t *frame = buffer + 3;
212
213 WREG32(AFMT_AVI_INFO0 + offset,
214 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
215 WREG32(AFMT_AVI_INFO1 + offset,
216 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
217 WREG32(AFMT_AVI_INFO2 + offset,
218 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
219 WREG32(AFMT_AVI_INFO3 + offset,
220 frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
221
222 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
223 HDMI_AVI_INFO_LINE(2),
224 ~HDMI_AVI_INFO_LINE_MASK);
225}
226
227void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
228 struct radeon_crtc *crtc, unsigned int clock)
229{
230 unsigned int max_ratio = clock / 24000;
231 u32 dto_phase;
232 u32 wallclock_ratio;
233 u32 value;
234
235 if (max_ratio >= 8) {
236 dto_phase = 192 * 1000;
237 wallclock_ratio = 3;
238 } else if (max_ratio >= 4) {
239 dto_phase = 96 * 1000;
240 wallclock_ratio = 2;
241 } else if (max_ratio >= 2) {
242 dto_phase = 48 * 1000;
243 wallclock_ratio = 1;
244 } else {
245 dto_phase = 24 * 1000;
246 wallclock_ratio = 0;
247 }
248
249 value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
250 value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
251 value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;
252 WREG32(DCCG_AUDIO_DTO0_CNTL, value);
253
254
255 value = 0;
256
257 if (crtc)
258 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
259
260 WREG32(DCCG_AUDIO_DTO_SOURCE, value);
261
262
263
264
265
266 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
267 WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
268}
269
270void dce4_dp_audio_set_dto(struct radeon_device *rdev,
271 struct radeon_crtc *crtc, unsigned int clock)
272{
273 u32 value;
274
275 value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
276 value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO;
277 WREG32(DCCG_AUDIO_DTO1_CNTL, value);
278
279
280 value = 0;
281 value |= DCCG_AUDIO_DTO_SEL;
282
283 if (crtc)
284 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
285
286 WREG32(DCCG_AUDIO_DTO_SOURCE, value);
287
288
289
290
291
292 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
293 WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
294}
295
296void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
297{
298 struct drm_device *dev = encoder->dev;
299 struct radeon_device *rdev = dev->dev_private;
300
301 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
302 HDMI_NULL_SEND |
303 HDMI_GC_SEND |
304 HDMI_GC_CONT);
305}
306
307void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)
308{
309 struct drm_device *dev = encoder->dev;
310 struct radeon_device *rdev = dev->dev_private;
311 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
312 uint32_t val;
313
314 val = RREG32(HDMI_CONTROL + offset);
315 val &= ~HDMI_DEEP_COLOR_ENABLE;
316 val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
317
318 switch (bpc) {
319 case 0:
320 case 6:
321 case 8:
322 case 16:
323 default:
324 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
325 connector->name, bpc);
326 break;
327 case 10:
328 val |= HDMI_DEEP_COLOR_ENABLE;
329 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
330 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
331 connector->name);
332 break;
333 case 12:
334 val |= HDMI_DEEP_COLOR_ENABLE;
335 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
336 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
337 connector->name);
338 break;
339 }
340
341 WREG32(HDMI_CONTROL + offset, val);
342}
343
344void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)
345{
346 struct drm_device *dev = encoder->dev;
347 struct radeon_device *rdev = dev->dev_private;
348
349 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
350 AFMT_AUDIO_INFO_UPDATE);
351
352 WREG32(AFMT_60958_0 + offset,
353 AFMT_60958_CS_CHANNEL_NUMBER_L(1));
354
355 WREG32(AFMT_60958_1 + offset,
356 AFMT_60958_CS_CHANNEL_NUMBER_R(2));
357
358 WREG32(AFMT_60958_2 + offset,
359 AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
360 AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
361 AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
362 AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
363 AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
364 AFMT_60958_CS_CHANNEL_NUMBER_7(8));
365
366 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
367 AFMT_AUDIO_CHANNEL_ENABLE(0xff));
368
369 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
370 HDMI_AUDIO_DELAY_EN(1) |
371 HDMI_AUDIO_PACKETS_PER_LINE(3));
372
373
374 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
375 AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE);
376}
377
378
379void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
380{
381 struct drm_device *dev = encoder->dev;
382 struct radeon_device *rdev = dev->dev_private;
383
384 if (mute)
385 WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);
386 else
387 WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);
388}
389
390void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
391{
392 struct drm_device *dev = encoder->dev;
393 struct radeon_device *rdev = dev->dev_private;
394 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
395 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
396
397 if (!dig || !dig->afmt)
398 return;
399
400 if (enable) {
401 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
402
403 if (connector && drm_detect_monitor_audio(radeon_connector_edid(connector))) {
404 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
405 HDMI_AVI_INFO_SEND |
406 HDMI_AVI_INFO_CONT |
407 HDMI_AUDIO_INFO_SEND |
408 HDMI_AUDIO_INFO_CONT);
409 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
410 AFMT_AUDIO_SAMPLE_SEND);
411 } else {
412 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
413 HDMI_AVI_INFO_SEND |
414 HDMI_AVI_INFO_CONT);
415 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
416 ~AFMT_AUDIO_SAMPLE_SEND);
417 }
418 } else {
419 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
420 ~AFMT_AUDIO_SAMPLE_SEND);
421 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);
422 }
423
424 dig->afmt->enabled = enable;
425
426 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
427 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
428}
429
430void evergreen_dp_enable(struct drm_encoder *encoder, bool enable)
431{
432 struct drm_device *dev = encoder->dev;
433 struct radeon_device *rdev = dev->dev_private;
434 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
435 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
436 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
437
438 if (!dig || !dig->afmt)
439 return;
440
441 if (enable && connector &&
442 drm_detect_monitor_audio(radeon_connector_edid(connector))) {
443 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
444 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
445 struct radeon_connector_atom_dig *dig_connector;
446 uint32_t val;
447
448 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
449 AFMT_AUDIO_SAMPLE_SEND);
450
451 WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,
452 EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
453
454 if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) {
455 dig_connector = radeon_connector->con_priv;
456 val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);
457 val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);
458
459 if (dig_connector->dp_clock == 162000)
460 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3);
461 else
462 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);
463
464 WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);
465 }
466
467 WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,
468 EVERGREEN_DP_SEC_ASP_ENABLE |
469 EVERGREEN_DP_SEC_ATP_ENABLE |
470 EVERGREEN_DP_SEC_AIP_ENABLE |
471 EVERGREEN_DP_SEC_STREAM_ENABLE);
472 } else {
473 WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);
474 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
475 ~AFMT_AUDIO_SAMPLE_SEND);
476 }
477
478 dig->afmt->enabled = enable;
479}
480