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28#include <drm/drmP.h>
29#include <drm/drm_crtc_helper.h>
30#include <drm/radeon_drm.h>
31#include "radeon_reg.h"
32#include "radeon.h"
33#include "atom.h"
34
35#include <linux/pm_runtime.h>
36
37#define RADEON_WAIT_IDLE_TIMEOUT 200
38
39
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47
48irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg)
49{
50 struct drm_device *dev = (struct drm_device *) arg;
51 struct radeon_device *rdev = dev->dev_private;
52 irqreturn_t ret;
53
54 ret = radeon_irq_process(rdev);
55 if (ret == IRQ_HANDLED)
56 pm_runtime_mark_last_busy(dev->dev);
57 return ret;
58}
59
60
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71
72
73
74static void radeon_hotplug_work_func(struct work_struct *work)
75{
76 struct radeon_device *rdev = container_of(work, struct radeon_device,
77 hotplug_work);
78 struct drm_device *dev = rdev->ddev;
79 struct drm_mode_config *mode_config = &dev->mode_config;
80 struct drm_connector *connector;
81
82
83
84 if (!rdev->mode_info.mode_config_initialized)
85 return;
86
87 mutex_lock(&mode_config->mutex);
88 if (mode_config->num_connector) {
89 list_for_each_entry(connector, &mode_config->connector_list, head)
90 radeon_connector_hotplug(connector);
91 }
92 mutex_unlock(&mode_config->mutex);
93
94 drm_helper_hpd_irq_event(dev);
95}
96
97static void radeon_dp_work_func(struct work_struct *work)
98{
99 struct radeon_device *rdev = container_of(work, struct radeon_device,
100 dp_work);
101 struct drm_device *dev = rdev->ddev;
102 struct drm_mode_config *mode_config = &dev->mode_config;
103 struct drm_connector *connector;
104
105
106 if (mode_config->num_connector) {
107 list_for_each_entry(connector, &mode_config->connector_list, head)
108 radeon_connector_hotplug(connector);
109 }
110}
111
112
113
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115
116
117
118
119void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
120{
121 struct radeon_device *rdev = dev->dev_private;
122 unsigned long irqflags;
123 unsigned i;
124
125 spin_lock_irqsave(&rdev->irq.lock, irqflags);
126
127 for (i = 0; i < RADEON_NUM_RINGS; i++)
128 atomic_set(&rdev->irq.ring_int[i], 0);
129 rdev->irq.dpm_thermal = false;
130 for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
131 rdev->irq.hpd[i] = false;
132 for (i = 0; i < RADEON_MAX_CRTCS; i++) {
133 rdev->irq.crtc_vblank_int[i] = false;
134 atomic_set(&rdev->irq.pflip[i], 0);
135 rdev->irq.afmt[i] = false;
136 }
137 radeon_irq_set(rdev);
138 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
139
140 radeon_irq_process(rdev);
141}
142
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149
150
151int radeon_driver_irq_postinstall_kms(struct drm_device *dev)
152{
153 struct radeon_device *rdev = dev->dev_private;
154
155 if (ASIC_IS_AVIVO(rdev))
156 dev->max_vblank_count = 0x00ffffff;
157 else
158 dev->max_vblank_count = 0x001fffff;
159
160 return 0;
161}
162
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168
169
170void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
171{
172 struct radeon_device *rdev = dev->dev_private;
173 unsigned long irqflags;
174 unsigned i;
175
176 if (rdev == NULL) {
177 return;
178 }
179 spin_lock_irqsave(&rdev->irq.lock, irqflags);
180
181 for (i = 0; i < RADEON_NUM_RINGS; i++)
182 atomic_set(&rdev->irq.ring_int[i], 0);
183 rdev->irq.dpm_thermal = false;
184 for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
185 rdev->irq.hpd[i] = false;
186 for (i = 0; i < RADEON_MAX_CRTCS; i++) {
187 rdev->irq.crtc_vblank_int[i] = false;
188 atomic_set(&rdev->irq.pflip[i], 0);
189 rdev->irq.afmt[i] = false;
190 }
191 radeon_irq_set(rdev);
192 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
193}
194
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203
204
205static bool radeon_msi_ok(struct radeon_device *rdev)
206{
207
208 if (rdev->family < CHIP_RV380)
209 return false;
210
211
212 if (rdev->flags & RADEON_IS_AGP)
213 return false;
214
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219
220 if (rdev->family < CHIP_BONAIRE) {
221 dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
222 rdev->pdev->no_64bit_msi = 1;
223 }
224
225
226 if (radeon_msi == 1)
227 return true;
228 else if (radeon_msi == 0)
229 return false;
230
231
232
233 if ((rdev->pdev->device == 0x791f) &&
234 (rdev->pdev->subsystem_vendor == 0x103c) &&
235 (rdev->pdev->subsystem_device == 0x30c2))
236 return true;
237
238
239 if ((rdev->pdev->device == 0x791f) &&
240 (rdev->pdev->subsystem_vendor == 0x1028) &&
241 (rdev->pdev->subsystem_device == 0x01fc))
242 return true;
243
244
245 if ((rdev->pdev->device == 0x791f) &&
246 (rdev->pdev->subsystem_vendor == 0x1028) &&
247 (rdev->pdev->subsystem_device == 0x01fd))
248 return true;
249
250
251 if ((rdev->pdev->device == 0x791f) &&
252 (rdev->pdev->subsystem_vendor == 0x107b) &&
253 (rdev->pdev->subsystem_device == 0x0185))
254 return true;
255
256
257 if (rdev->family == CHIP_RS690)
258 return true;
259
260
261
262
263
264 if (rdev->family == CHIP_RV515)
265 return false;
266 if (rdev->flags & RADEON_IS_IGP) {
267
268 if (rdev->family >= CHIP_PALM)
269 return true;
270
271 return false;
272 }
273
274 return true;
275}
276
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283
284
285int radeon_irq_kms_init(struct radeon_device *rdev)
286{
287 int r = 0;
288
289 spin_lock_init(&rdev->irq.lock);
290 r = drm_vblank_init(rdev->ddev, rdev->num_crtc);
291 if (r) {
292 return r;
293 }
294
295 rdev->msi_enabled = 0;
296
297 if (radeon_msi_ok(rdev)) {
298 int ret = pci_enable_msi(rdev->pdev);
299 if (!ret) {
300 rdev->msi_enabled = 1;
301 dev_info(rdev->dev, "radeon: using MSI.\n");
302 }
303 }
304
305 INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func);
306 INIT_WORK(&rdev->dp_work, radeon_dp_work_func);
307 INIT_WORK(&rdev->audio_work, r600_audio_update_hdmi);
308
309 rdev->irq.installed = true;
310 r = drm_irq_install(rdev->ddev, rdev->ddev->pdev->irq);
311 if (r) {
312 rdev->irq.installed = false;
313 flush_work(&rdev->hotplug_work);
314 return r;
315 }
316
317 DRM_INFO("radeon: irq initialized.\n");
318 return 0;
319}
320
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325
326
327
328void radeon_irq_kms_fini(struct radeon_device *rdev)
329{
330 drm_vblank_cleanup(rdev->ddev);
331 if (rdev->irq.installed) {
332 drm_irq_uninstall(rdev->ddev);
333 rdev->irq.installed = false;
334 if (rdev->msi_enabled)
335 pci_disable_msi(rdev->pdev);
336 flush_work(&rdev->hotplug_work);
337 }
338}
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349
350void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring)
351{
352 unsigned long irqflags;
353
354 if (!rdev->ddev->irq_enabled)
355 return;
356
357 if (atomic_inc_return(&rdev->irq.ring_int[ring]) == 1) {
358 spin_lock_irqsave(&rdev->irq.lock, irqflags);
359 radeon_irq_set(rdev);
360 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
361 }
362}
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374bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring)
375{
376 return atomic_inc_return(&rdev->irq.ring_int[ring]) == 1;
377}
378
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388
389void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring)
390{
391 unsigned long irqflags;
392
393 if (!rdev->ddev->irq_enabled)
394 return;
395
396 if (atomic_dec_and_test(&rdev->irq.ring_int[ring])) {
397 spin_lock_irqsave(&rdev->irq.lock, irqflags);
398 radeon_irq_set(rdev);
399 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
400 }
401}
402
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411
412void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc)
413{
414 unsigned long irqflags;
415
416 if (crtc < 0 || crtc >= rdev->num_crtc)
417 return;
418
419 if (!rdev->ddev->irq_enabled)
420 return;
421
422 if (atomic_inc_return(&rdev->irq.pflip[crtc]) == 1) {
423 spin_lock_irqsave(&rdev->irq.lock, irqflags);
424 radeon_irq_set(rdev);
425 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
426 }
427}
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436
437
438void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc)
439{
440 unsigned long irqflags;
441
442 if (crtc < 0 || crtc >= rdev->num_crtc)
443 return;
444
445 if (!rdev->ddev->irq_enabled)
446 return;
447
448 if (atomic_dec_and_test(&rdev->irq.pflip[crtc])) {
449 spin_lock_irqsave(&rdev->irq.lock, irqflags);
450 radeon_irq_set(rdev);
451 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
452 }
453}
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462
463void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block)
464{
465 unsigned long irqflags;
466
467 if (!rdev->ddev->irq_enabled)
468 return;
469
470 spin_lock_irqsave(&rdev->irq.lock, irqflags);
471 rdev->irq.afmt[block] = true;
472 radeon_irq_set(rdev);
473 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
474
475}
476
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484
485void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block)
486{
487 unsigned long irqflags;
488
489 if (!rdev->ddev->irq_enabled)
490 return;
491
492 spin_lock_irqsave(&rdev->irq.lock, irqflags);
493 rdev->irq.afmt[block] = false;
494 radeon_irq_set(rdev);
495 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
496}
497
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505
506void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask)
507{
508 unsigned long irqflags;
509 int i;
510
511 if (!rdev->ddev->irq_enabled)
512 return;
513
514 spin_lock_irqsave(&rdev->irq.lock, irqflags);
515 for (i = 0; i < RADEON_MAX_HPD_PINS; ++i)
516 rdev->irq.hpd[i] |= !!(hpd_mask & (1 << i));
517 radeon_irq_set(rdev);
518 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
519}
520
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527
528
529void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask)
530{
531 unsigned long irqflags;
532 int i;
533
534 if (!rdev->ddev->irq_enabled)
535 return;
536
537 spin_lock_irqsave(&rdev->irq.lock, irqflags);
538 for (i = 0; i < RADEON_MAX_HPD_PINS; ++i)
539 rdev->irq.hpd[i] &= !(hpd_mask & (1 << i));
540 radeon_irq_set(rdev);
541 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
542}
543
544