1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28#include "vmwgfx_drv.h"
29#include "ttm/ttm_bo_api.h"
30
31
32
33
34
35#define VMW_CMDBUF_INLINE_ALIGN 64
36#define VMW_CMDBUF_INLINE_SIZE \
37 (1024 - ALIGN(sizeof(SVGACBHeader), VMW_CMDBUF_INLINE_ALIGN))
38
39
40
41
42
43
44
45
46
47
48struct vmw_cmdbuf_context {
49 struct list_head submitted;
50 struct list_head hw_submitted;
51 struct list_head preempted;
52 unsigned num_hw_submitted;
53};
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101struct vmw_cmdbuf_man {
102 struct mutex cur_mutex;
103 struct mutex space_mutex;
104 struct work_struct work;
105 struct vmw_private *dev_priv;
106 struct vmw_cmdbuf_context ctx[SVGA_CB_CONTEXT_MAX];
107 struct list_head error;
108 struct drm_mm mm;
109 struct ttm_buffer_object *cmd_space;
110 struct ttm_bo_kmap_obj map_obj;
111 u8 *map;
112 struct vmw_cmdbuf_header *cur;
113 size_t cur_pos;
114 size_t default_size;
115 unsigned max_hw_submitted;
116 spinlock_t lock;
117 struct dma_pool *headers;
118 struct dma_pool *dheaders;
119 struct tasklet_struct tasklet;
120 wait_queue_head_t alloc_queue;
121 wait_queue_head_t idle_queue;
122 bool irq_on;
123 bool using_mob;
124 bool has_pool;
125 dma_addr_t handle;
126 size_t size;
127};
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144struct vmw_cmdbuf_header {
145 struct vmw_cmdbuf_man *man;
146 SVGACBHeader *cb_header;
147 SVGACBContext cb_context;
148 struct list_head list;
149 struct drm_mm_node node;
150 dma_addr_t handle;
151 u8 *cmd;
152 size_t size;
153 size_t reserved;
154 bool inline_space;
155};
156
157
158
159
160
161
162
163
164struct vmw_cmdbuf_dheader {
165 SVGACBHeader cb_header;
166 u8 cmd[VMW_CMDBUF_INLINE_SIZE] __aligned(VMW_CMDBUF_INLINE_ALIGN);
167};
168
169
170
171
172
173
174
175
176struct vmw_cmdbuf_alloc_info {
177 size_t page_size;
178 struct drm_mm_node *node;
179 bool done;
180};
181
182
183#define for_each_cmdbuf_ctx(_man, _i, _ctx) \
184 for (_i = 0, _ctx = &(_man)->ctx[0]; (_i) < SVGA_CB_CONTEXT_MAX; \
185 ++(_i), ++(_ctx))
186
187static int vmw_cmdbuf_startstop(struct vmw_cmdbuf_man *man, bool enable);
188
189
190
191
192
193
194
195
196static int vmw_cmdbuf_cur_lock(struct vmw_cmdbuf_man *man, bool interruptible)
197{
198 if (interruptible) {
199 if (mutex_lock_interruptible(&man->cur_mutex))
200 return -ERESTARTSYS;
201 } else {
202 mutex_lock(&man->cur_mutex);
203 }
204
205 return 0;
206}
207
208
209
210
211
212
213static void vmw_cmdbuf_cur_unlock(struct vmw_cmdbuf_man *man)
214{
215 mutex_unlock(&man->cur_mutex);
216}
217
218
219
220
221
222
223
224
225static void vmw_cmdbuf_header_inline_free(struct vmw_cmdbuf_header *header)
226{
227 struct vmw_cmdbuf_dheader *dheader;
228
229 if (WARN_ON_ONCE(!header->inline_space))
230 return;
231
232 dheader = container_of(header->cb_header, struct vmw_cmdbuf_dheader,
233 cb_header);
234 dma_pool_free(header->man->dheaders, dheader, header->handle);
235 kfree(header);
236}
237
238
239
240
241
242
243
244
245
246static void __vmw_cmdbuf_header_free(struct vmw_cmdbuf_header *header)
247{
248 struct vmw_cmdbuf_man *man = header->man;
249
250 BUG_ON(!spin_is_locked(&man->lock));
251
252 if (header->inline_space) {
253 vmw_cmdbuf_header_inline_free(header);
254 return;
255 }
256
257 drm_mm_remove_node(&header->node);
258 wake_up_all(&man->alloc_queue);
259 if (header->cb_header)
260 dma_pool_free(man->headers, header->cb_header,
261 header->handle);
262 kfree(header);
263}
264
265
266
267
268
269
270
271void vmw_cmdbuf_header_free(struct vmw_cmdbuf_header *header)
272{
273 struct vmw_cmdbuf_man *man = header->man;
274
275
276 if (header->inline_space) {
277 vmw_cmdbuf_header_inline_free(header);
278 return;
279 }
280 spin_lock_bh(&man->lock);
281 __vmw_cmdbuf_header_free(header);
282 spin_unlock_bh(&man->lock);
283}
284
285
286
287
288
289
290
291static int vmw_cmdbuf_header_submit(struct vmw_cmdbuf_header *header)
292{
293 struct vmw_cmdbuf_man *man = header->man;
294 u32 val;
295
296 if (sizeof(header->handle) > 4)
297 val = (header->handle >> 32);
298 else
299 val = 0;
300 vmw_write(man->dev_priv, SVGA_REG_COMMAND_HIGH, val);
301
302 val = (header->handle & 0xFFFFFFFFULL);
303 val |= header->cb_context & SVGA_CB_CONTEXT_MASK;
304 vmw_write(man->dev_priv, SVGA_REG_COMMAND_LOW, val);
305
306 return header->cb_header->status;
307}
308
309
310
311
312
313
314static void vmw_cmdbuf_ctx_init(struct vmw_cmdbuf_context *ctx)
315{
316 INIT_LIST_HEAD(&ctx->hw_submitted);
317 INIT_LIST_HEAD(&ctx->submitted);
318 INIT_LIST_HEAD(&ctx->preempted);
319 ctx->num_hw_submitted = 0;
320}
321
322
323
324
325
326
327
328
329
330
331
332static void vmw_cmdbuf_ctx_submit(struct vmw_cmdbuf_man *man,
333 struct vmw_cmdbuf_context *ctx)
334{
335 while (ctx->num_hw_submitted < man->max_hw_submitted &&
336 !list_empty(&ctx->submitted)) {
337 struct vmw_cmdbuf_header *entry;
338 SVGACBStatus status;
339
340 entry = list_first_entry(&ctx->submitted,
341 struct vmw_cmdbuf_header,
342 list);
343
344 status = vmw_cmdbuf_header_submit(entry);
345
346
347 if (WARN_ON_ONCE(status == SVGA_CB_STATUS_QUEUE_FULL)) {
348 entry->cb_header->status = SVGA_CB_STATUS_NONE;
349 break;
350 }
351
352 list_del(&entry->list);
353 list_add_tail(&entry->list, &ctx->hw_submitted);
354 ctx->num_hw_submitted++;
355 }
356
357}
358
359
360
361
362
363
364
365
366
367
368
369static void vmw_cmdbuf_ctx_process(struct vmw_cmdbuf_man *man,
370 struct vmw_cmdbuf_context *ctx,
371 int *notempty)
372{
373 struct vmw_cmdbuf_header *entry, *next;
374
375 vmw_cmdbuf_ctx_submit(man, ctx);
376
377 list_for_each_entry_safe(entry, next, &ctx->hw_submitted, list) {
378 SVGACBStatus status = entry->cb_header->status;
379
380 if (status == SVGA_CB_STATUS_NONE)
381 break;
382
383 list_del(&entry->list);
384 wake_up_all(&man->idle_queue);
385 ctx->num_hw_submitted--;
386 switch (status) {
387 case SVGA_CB_STATUS_COMPLETED:
388 __vmw_cmdbuf_header_free(entry);
389 break;
390 case SVGA_CB_STATUS_COMMAND_ERROR:
391 case SVGA_CB_STATUS_CB_HEADER_ERROR:
392 list_add_tail(&entry->list, &man->error);
393 schedule_work(&man->work);
394 break;
395 case SVGA_CB_STATUS_PREEMPTED:
396 list_add(&entry->list, &ctx->preempted);
397 break;
398 default:
399 WARN_ONCE(true, "Undefined command buffer status.\n");
400 __vmw_cmdbuf_header_free(entry);
401 break;
402 }
403 }
404
405 vmw_cmdbuf_ctx_submit(man, ctx);
406 if (!list_empty(&ctx->submitted))
407 (*notempty)++;
408}
409
410
411
412
413
414
415
416
417
418
419
420static void vmw_cmdbuf_man_process(struct vmw_cmdbuf_man *man)
421{
422 int notempty;
423 struct vmw_cmdbuf_context *ctx;
424 int i;
425
426retry:
427 notempty = 0;
428 for_each_cmdbuf_ctx(man, i, ctx)
429 vmw_cmdbuf_ctx_process(man, ctx, ¬empty);
430
431 if (man->irq_on && !notempty) {
432 vmw_generic_waiter_remove(man->dev_priv,
433 SVGA_IRQFLAG_COMMAND_BUFFER,
434 &man->dev_priv->cmdbuf_waiters);
435 man->irq_on = false;
436 } else if (!man->irq_on && notempty) {
437 vmw_generic_waiter_add(man->dev_priv,
438 SVGA_IRQFLAG_COMMAND_BUFFER,
439 &man->dev_priv->cmdbuf_waiters);
440 man->irq_on = true;
441
442
443 goto retry;
444 }
445}
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460static void vmw_cmdbuf_ctx_add(struct vmw_cmdbuf_man *man,
461 struct vmw_cmdbuf_header *header,
462 SVGACBContext cb_context)
463{
464 if (!(header->cb_header->flags & SVGA_CB_FLAG_DX_CONTEXT))
465 header->cb_header->dxContext = 0;
466 header->cb_context = cb_context;
467 list_add_tail(&header->list, &man->ctx[cb_context].submitted);
468
469 vmw_cmdbuf_man_process(man);
470}
471
472
473
474
475
476
477
478
479
480
481
482
483static void vmw_cmdbuf_man_tasklet(unsigned long data)
484{
485 struct vmw_cmdbuf_man *man = (struct vmw_cmdbuf_man *) data;
486
487 spin_lock(&man->lock);
488 vmw_cmdbuf_man_process(man);
489 spin_unlock(&man->lock);
490}
491
492
493
494
495
496
497
498
499
500
501static void vmw_cmdbuf_work_func(struct work_struct *work)
502{
503 struct vmw_cmdbuf_man *man =
504 container_of(work, struct vmw_cmdbuf_man, work);
505 struct vmw_cmdbuf_header *entry, *next;
506 uint32_t dummy;
507 bool restart = false;
508
509 spin_lock_bh(&man->lock);
510 list_for_each_entry_safe(entry, next, &man->error, list) {
511 restart = true;
512 DRM_ERROR("Command buffer error.\n");
513
514 list_del(&entry->list);
515 __vmw_cmdbuf_header_free(entry);
516 wake_up_all(&man->idle_queue);
517 }
518 spin_unlock_bh(&man->lock);
519
520 if (restart && vmw_cmdbuf_startstop(man, true))
521 DRM_ERROR("Failed restarting command buffer context 0.\n");
522
523
524 vmw_fifo_send_fence(man->dev_priv, &dummy);
525}
526
527
528
529
530
531
532
533
534static bool vmw_cmdbuf_man_idle(struct vmw_cmdbuf_man *man,
535 bool check_preempted)
536{
537 struct vmw_cmdbuf_context *ctx;
538 bool idle = false;
539 int i;
540
541 spin_lock_bh(&man->lock);
542 vmw_cmdbuf_man_process(man);
543 for_each_cmdbuf_ctx(man, i, ctx) {
544 if (!list_empty(&ctx->submitted) ||
545 !list_empty(&ctx->hw_submitted) ||
546 (check_preempted && !list_empty(&ctx->preempted)))
547 goto out_unlock;
548 }
549
550 idle = list_empty(&man->error);
551
552out_unlock:
553 spin_unlock_bh(&man->lock);
554
555 return idle;
556}
557
558
559
560
561
562
563
564
565
566
567static void __vmw_cmdbuf_cur_flush(struct vmw_cmdbuf_man *man)
568{
569 struct vmw_cmdbuf_header *cur = man->cur;
570
571 WARN_ON(!mutex_is_locked(&man->cur_mutex));
572
573 if (!cur)
574 return;
575
576 spin_lock_bh(&man->lock);
577 if (man->cur_pos == 0) {
578 __vmw_cmdbuf_header_free(cur);
579 goto out_unlock;
580 }
581
582 man->cur->cb_header->length = man->cur_pos;
583 vmw_cmdbuf_ctx_add(man, man->cur, SVGA_CB_CONTEXT_0);
584out_unlock:
585 spin_unlock_bh(&man->lock);
586 man->cur = NULL;
587 man->cur_pos = 0;
588}
589
590
591
592
593
594
595
596
597
598
599
600int vmw_cmdbuf_cur_flush(struct vmw_cmdbuf_man *man,
601 bool interruptible)
602{
603 int ret = vmw_cmdbuf_cur_lock(man, interruptible);
604
605 if (ret)
606 return ret;
607
608 __vmw_cmdbuf_cur_flush(man);
609 vmw_cmdbuf_cur_unlock(man);
610
611 return 0;
612}
613
614
615
616
617
618
619
620
621
622
623
624
625int vmw_cmdbuf_idle(struct vmw_cmdbuf_man *man, bool interruptible,
626 unsigned long timeout)
627{
628 int ret;
629
630 ret = vmw_cmdbuf_cur_flush(man, interruptible);
631 vmw_generic_waiter_add(man->dev_priv,
632 SVGA_IRQFLAG_COMMAND_BUFFER,
633 &man->dev_priv->cmdbuf_waiters);
634
635 if (interruptible) {
636 ret = wait_event_interruptible_timeout
637 (man->idle_queue, vmw_cmdbuf_man_idle(man, true),
638 timeout);
639 } else {
640 ret = wait_event_timeout
641 (man->idle_queue, vmw_cmdbuf_man_idle(man, true),
642 timeout);
643 }
644 vmw_generic_waiter_remove(man->dev_priv,
645 SVGA_IRQFLAG_COMMAND_BUFFER,
646 &man->dev_priv->cmdbuf_waiters);
647 if (ret == 0) {
648 if (!vmw_cmdbuf_man_idle(man, true))
649 ret = -EBUSY;
650 else
651 ret = 0;
652 }
653 if (ret > 0)
654 ret = 0;
655
656 return ret;
657}
658
659
660
661
662
663
664
665
666
667
668
669static bool vmw_cmdbuf_try_alloc(struct vmw_cmdbuf_man *man,
670 struct vmw_cmdbuf_alloc_info *info)
671{
672 int ret;
673
674 if (info->done)
675 return true;
676
677 memset(info->node, 0, sizeof(*info->node));
678 spin_lock_bh(&man->lock);
679 ret = drm_mm_insert_node_generic(&man->mm, info->node, info->page_size,
680 0, 0,
681 DRM_MM_SEARCH_DEFAULT,
682 DRM_MM_CREATE_DEFAULT);
683 if (ret) {
684 vmw_cmdbuf_man_process(man);
685 ret = drm_mm_insert_node_generic(&man->mm, info->node,
686 info->page_size, 0, 0,
687 DRM_MM_SEARCH_DEFAULT,
688 DRM_MM_CREATE_DEFAULT);
689 }
690
691 spin_unlock_bh(&man->lock);
692 info->done = !ret;
693
694 return info->done;
695}
696
697
698
699
700
701
702
703
704
705
706
707
708
709static int vmw_cmdbuf_alloc_space(struct vmw_cmdbuf_man *man,
710 struct drm_mm_node *node,
711 size_t size,
712 bool interruptible)
713{
714 struct vmw_cmdbuf_alloc_info info;
715
716 info.page_size = PAGE_ALIGN(size) >> PAGE_SHIFT;
717 info.node = node;
718 info.done = false;
719
720
721
722
723
724 if (interruptible) {
725 if (mutex_lock_interruptible(&man->space_mutex))
726 return -ERESTARTSYS;
727 } else {
728 mutex_lock(&man->space_mutex);
729 }
730
731
732 if (vmw_cmdbuf_try_alloc(man, &info))
733 goto out_unlock;
734
735 vmw_generic_waiter_add(man->dev_priv,
736 SVGA_IRQFLAG_COMMAND_BUFFER,
737 &man->dev_priv->cmdbuf_waiters);
738
739 if (interruptible) {
740 int ret;
741
742 ret = wait_event_interruptible
743 (man->alloc_queue, vmw_cmdbuf_try_alloc(man, &info));
744 if (ret) {
745 vmw_generic_waiter_remove
746 (man->dev_priv, SVGA_IRQFLAG_COMMAND_BUFFER,
747 &man->dev_priv->cmdbuf_waiters);
748 mutex_unlock(&man->space_mutex);
749 return ret;
750 }
751 } else {
752 wait_event(man->alloc_queue, vmw_cmdbuf_try_alloc(man, &info));
753 }
754 vmw_generic_waiter_remove(man->dev_priv,
755 SVGA_IRQFLAG_COMMAND_BUFFER,
756 &man->dev_priv->cmdbuf_waiters);
757
758out_unlock:
759 mutex_unlock(&man->space_mutex);
760
761 return 0;
762}
763
764
765
766
767
768
769
770
771
772
773static int vmw_cmdbuf_space_pool(struct vmw_cmdbuf_man *man,
774 struct vmw_cmdbuf_header *header,
775 size_t size,
776 bool interruptible)
777{
778 SVGACBHeader *cb_hdr;
779 size_t offset;
780 int ret;
781
782 if (!man->has_pool)
783 return -ENOMEM;
784
785 ret = vmw_cmdbuf_alloc_space(man, &header->node, size, interruptible);
786
787 if (ret)
788 return ret;
789
790 header->cb_header = dma_pool_alloc(man->headers, GFP_KERNEL,
791 &header->handle);
792 if (!header->cb_header) {
793 ret = -ENOMEM;
794 goto out_no_cb_header;
795 }
796
797 header->size = header->node.size << PAGE_SHIFT;
798 cb_hdr = header->cb_header;
799 offset = header->node.start << PAGE_SHIFT;
800 header->cmd = man->map + offset;
801 memset(cb_hdr, 0, sizeof(*cb_hdr));
802 if (man->using_mob) {
803 cb_hdr->flags = SVGA_CB_FLAG_MOB;
804 cb_hdr->ptr.mob.mobid = man->cmd_space->mem.start;
805 cb_hdr->ptr.mob.mobOffset = offset;
806 } else {
807 cb_hdr->ptr.pa = (u64)man->handle + (u64)offset;
808 }
809
810 return 0;
811
812out_no_cb_header:
813 spin_lock_bh(&man->lock);
814 drm_mm_remove_node(&header->node);
815 spin_unlock_bh(&man->lock);
816
817 return ret;
818}
819
820
821
822
823
824
825
826
827
828static int vmw_cmdbuf_space_inline(struct vmw_cmdbuf_man *man,
829 struct vmw_cmdbuf_header *header,
830 int size)
831{
832 struct vmw_cmdbuf_dheader *dheader;
833 SVGACBHeader *cb_hdr;
834
835 if (WARN_ON_ONCE(size > VMW_CMDBUF_INLINE_SIZE))
836 return -ENOMEM;
837
838 dheader = dma_pool_alloc(man->dheaders, GFP_KERNEL,
839 &header->handle);
840 if (!dheader)
841 return -ENOMEM;
842
843 header->inline_space = true;
844 header->size = VMW_CMDBUF_INLINE_SIZE;
845 cb_hdr = &dheader->cb_header;
846 header->cb_header = cb_hdr;
847 header->cmd = dheader->cmd;
848 memset(dheader, 0, sizeof(*dheader));
849 cb_hdr->status = SVGA_CB_STATUS_NONE;
850 cb_hdr->flags = SVGA_CB_FLAG_NONE;
851 cb_hdr->ptr.pa = (u64)header->handle +
852 (u64)offsetof(struct vmw_cmdbuf_dheader, cmd);
853
854 return 0;
855}
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870void *vmw_cmdbuf_alloc(struct vmw_cmdbuf_man *man,
871 size_t size, bool interruptible,
872 struct vmw_cmdbuf_header **p_header)
873{
874 struct vmw_cmdbuf_header *header;
875 int ret = 0;
876
877 *p_header = NULL;
878
879 header = kzalloc(sizeof(*header), GFP_KERNEL);
880 if (!header)
881 return ERR_PTR(-ENOMEM);
882
883 if (size <= VMW_CMDBUF_INLINE_SIZE)
884 ret = vmw_cmdbuf_space_inline(man, header, size);
885 else
886 ret = vmw_cmdbuf_space_pool(man, header, size, interruptible);
887
888 if (ret) {
889 kfree(header);
890 return ERR_PTR(ret);
891 }
892
893 header->man = man;
894 INIT_LIST_HEAD(&header->list);
895 header->cb_header->status = SVGA_CB_STATUS_NONE;
896 *p_header = header;
897
898 return header->cmd;
899}
900
901
902
903
904
905
906
907
908
909
910
911
912
913static void *vmw_cmdbuf_reserve_cur(struct vmw_cmdbuf_man *man,
914 size_t size,
915 int ctx_id,
916 bool interruptible)
917{
918 struct vmw_cmdbuf_header *cur;
919 void *ret;
920
921 if (vmw_cmdbuf_cur_lock(man, interruptible))
922 return ERR_PTR(-ERESTARTSYS);
923
924 cur = man->cur;
925 if (cur && (size + man->cur_pos > cur->size ||
926 ((cur->cb_header->flags & SVGA_CB_FLAG_DX_CONTEXT) &&
927 ctx_id != cur->cb_header->dxContext)))
928 __vmw_cmdbuf_cur_flush(man);
929
930 if (!man->cur) {
931 ret = vmw_cmdbuf_alloc(man,
932 max_t(size_t, size, man->default_size),
933 interruptible, &man->cur);
934 if (IS_ERR(ret)) {
935 vmw_cmdbuf_cur_unlock(man);
936 return ret;
937 }
938
939 cur = man->cur;
940 }
941
942 if (ctx_id != SVGA3D_INVALID_ID) {
943 cur->cb_header->flags |= SVGA_CB_FLAG_DX_CONTEXT;
944 cur->cb_header->dxContext = ctx_id;
945 }
946
947 cur->reserved = size;
948
949 return (void *) (man->cur->cmd + man->cur_pos);
950}
951
952
953
954
955
956
957
958
959static void vmw_cmdbuf_commit_cur(struct vmw_cmdbuf_man *man,
960 size_t size, bool flush)
961{
962 struct vmw_cmdbuf_header *cur = man->cur;
963
964 WARN_ON(!mutex_is_locked(&man->cur_mutex));
965
966 WARN_ON(size > cur->reserved);
967 man->cur_pos += size;
968 if (!size)
969 cur->cb_header->flags &= ~SVGA_CB_FLAG_DX_CONTEXT;
970 if (flush)
971 __vmw_cmdbuf_cur_flush(man);
972 vmw_cmdbuf_cur_unlock(man);
973}
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988void *vmw_cmdbuf_reserve(struct vmw_cmdbuf_man *man, size_t size,
989 int ctx_id, bool interruptible,
990 struct vmw_cmdbuf_header *header)
991{
992 if (!header)
993 return vmw_cmdbuf_reserve_cur(man, size, ctx_id, interruptible);
994
995 if (size > header->size)
996 return ERR_PTR(-EINVAL);
997
998 if (ctx_id != SVGA3D_INVALID_ID) {
999 header->cb_header->flags |= SVGA_CB_FLAG_DX_CONTEXT;
1000 header->cb_header->dxContext = ctx_id;
1001 }
1002
1003 header->reserved = size;
1004 return header->cmd;
1005}
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016void vmw_cmdbuf_commit(struct vmw_cmdbuf_man *man, size_t size,
1017 struct vmw_cmdbuf_header *header, bool flush)
1018{
1019 if (!header) {
1020 vmw_cmdbuf_commit_cur(man, size, flush);
1021 return;
1022 }
1023
1024 (void) vmw_cmdbuf_cur_lock(man, false);
1025 __vmw_cmdbuf_cur_flush(man);
1026 WARN_ON(size > header->reserved);
1027 man->cur = header;
1028 man->cur_pos = size;
1029 if (!size)
1030 header->cb_header->flags &= ~SVGA_CB_FLAG_DX_CONTEXT;
1031 if (flush)
1032 __vmw_cmdbuf_cur_flush(man);
1033 vmw_cmdbuf_cur_unlock(man);
1034}
1035
1036
1037
1038
1039
1040
1041void vmw_cmdbuf_tasklet_schedule(struct vmw_cmdbuf_man *man)
1042{
1043 if (!man)
1044 return;
1045
1046 tasklet_schedule(&man->tasklet);
1047}
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058static int vmw_cmdbuf_send_device_command(struct vmw_cmdbuf_man *man,
1059 const void *command,
1060 size_t size)
1061{
1062 struct vmw_cmdbuf_header *header;
1063 int status;
1064 void *cmd = vmw_cmdbuf_alloc(man, size, false, &header);
1065
1066 if (IS_ERR(cmd))
1067 return PTR_ERR(cmd);
1068
1069 memcpy(cmd, command, size);
1070 header->cb_header->length = size;
1071 header->cb_context = SVGA_CB_CONTEXT_DEVICE;
1072 spin_lock_bh(&man->lock);
1073 status = vmw_cmdbuf_header_submit(header);
1074 spin_unlock_bh(&man->lock);
1075 vmw_cmdbuf_header_free(header);
1076
1077 if (status != SVGA_CB_STATUS_COMPLETED) {
1078 DRM_ERROR("Device context command failed with status %d\n",
1079 status);
1080 return -EINVAL;
1081 }
1082
1083 return 0;
1084}
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095static int vmw_cmdbuf_startstop(struct vmw_cmdbuf_man *man,
1096 bool enable)
1097{
1098 struct {
1099 uint32 id;
1100 SVGADCCmdStartStop body;
1101 } __packed cmd;
1102
1103 cmd.id = SVGA_DC_CMD_START_STOP_CONTEXT;
1104 cmd.body.enable = (enable) ? 1 : 0;
1105 cmd.body.context = SVGA_CB_CONTEXT_0;
1106
1107 return vmw_cmdbuf_send_device_command(man, &cmd, sizeof(cmd));
1108}
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man,
1126 size_t size, size_t default_size)
1127{
1128 struct vmw_private *dev_priv = man->dev_priv;
1129 bool dummy;
1130 int ret;
1131
1132 if (man->has_pool)
1133 return -EINVAL;
1134
1135
1136 size = PAGE_ALIGN(size);
1137 man->map = dma_alloc_coherent(&dev_priv->dev->pdev->dev, size,
1138 &man->handle, GFP_KERNEL);
1139 if (man->map) {
1140 man->using_mob = false;
1141 } else {
1142
1143
1144
1145
1146
1147
1148 if (!(dev_priv->capabilities & SVGA_CAP_DX))
1149 return -ENOMEM;
1150
1151 ret = ttm_bo_create(&dev_priv->bdev, size, ttm_bo_type_device,
1152 &vmw_mob_ne_placement, 0, false, NULL,
1153 &man->cmd_space);
1154 if (ret)
1155 return ret;
1156
1157 man->using_mob = true;
1158 ret = ttm_bo_kmap(man->cmd_space, 0, size >> PAGE_SHIFT,
1159 &man->map_obj);
1160 if (ret)
1161 goto out_no_map;
1162
1163 man->map = ttm_kmap_obj_virtual(&man->map_obj, &dummy);
1164 }
1165
1166 man->size = size;
1167 drm_mm_init(&man->mm, 0, size >> PAGE_SHIFT);
1168
1169 man->has_pool = true;
1170
1171
1172
1173
1174
1175
1176
1177 man->default_size = VMW_CMDBUF_INLINE_SIZE;
1178 DRM_INFO("Using command buffers with %s pool.\n",
1179 (man->using_mob) ? "MOB" : "DMA");
1180
1181 return 0;
1182
1183out_no_map:
1184 if (man->using_mob)
1185 ttm_bo_unref(&man->cmd_space);
1186
1187 return ret;
1188}
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200struct vmw_cmdbuf_man *vmw_cmdbuf_man_create(struct vmw_private *dev_priv)
1201{
1202 struct vmw_cmdbuf_man *man;
1203 struct vmw_cmdbuf_context *ctx;
1204 int i;
1205 int ret;
1206
1207 if (!(dev_priv->capabilities & SVGA_CAP_COMMAND_BUFFERS))
1208 return ERR_PTR(-ENOSYS);
1209
1210 man = kzalloc(sizeof(*man), GFP_KERNEL);
1211 if (!man)
1212 return ERR_PTR(-ENOMEM);
1213
1214 man->headers = dma_pool_create("vmwgfx cmdbuf",
1215 &dev_priv->dev->pdev->dev,
1216 sizeof(SVGACBHeader),
1217 64, PAGE_SIZE);
1218 if (!man->headers) {
1219 ret = -ENOMEM;
1220 goto out_no_pool;
1221 }
1222
1223 man->dheaders = dma_pool_create("vmwgfx inline cmdbuf",
1224 &dev_priv->dev->pdev->dev,
1225 sizeof(struct vmw_cmdbuf_dheader),
1226 64, PAGE_SIZE);
1227 if (!man->dheaders) {
1228 ret = -ENOMEM;
1229 goto out_no_dpool;
1230 }
1231
1232 for_each_cmdbuf_ctx(man, i, ctx)
1233 vmw_cmdbuf_ctx_init(ctx);
1234
1235 INIT_LIST_HEAD(&man->error);
1236 spin_lock_init(&man->lock);
1237 mutex_init(&man->cur_mutex);
1238 mutex_init(&man->space_mutex);
1239 tasklet_init(&man->tasklet, vmw_cmdbuf_man_tasklet,
1240 (unsigned long) man);
1241 man->default_size = VMW_CMDBUF_INLINE_SIZE;
1242 init_waitqueue_head(&man->alloc_queue);
1243 init_waitqueue_head(&man->idle_queue);
1244 man->dev_priv = dev_priv;
1245 man->max_hw_submitted = SVGA_CB_MAX_QUEUED_PER_CONTEXT - 1;
1246 INIT_WORK(&man->work, &vmw_cmdbuf_work_func);
1247 vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ERROR,
1248 &dev_priv->error_waiters);
1249 ret = vmw_cmdbuf_startstop(man, true);
1250 if (ret) {
1251 DRM_ERROR("Failed starting command buffer context 0.\n");
1252 vmw_cmdbuf_man_destroy(man);
1253 return ERR_PTR(ret);
1254 }
1255
1256 return man;
1257
1258out_no_dpool:
1259 dma_pool_destroy(man->headers);
1260out_no_pool:
1261 kfree(man);
1262
1263 return ERR_PTR(ret);
1264}
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277void vmw_cmdbuf_remove_pool(struct vmw_cmdbuf_man *man)
1278{
1279 if (!man->has_pool)
1280 return;
1281
1282 man->has_pool = false;
1283 man->default_size = VMW_CMDBUF_INLINE_SIZE;
1284 (void) vmw_cmdbuf_idle(man, false, 10*HZ);
1285 if (man->using_mob) {
1286 (void) ttm_bo_kunmap(&man->map_obj);
1287 ttm_bo_unref(&man->cmd_space);
1288 } else {
1289 dma_free_coherent(&man->dev_priv->dev->pdev->dev,
1290 man->size, man->map, man->handle);
1291 }
1292}
1293
1294
1295
1296
1297
1298
1299
1300
1301void vmw_cmdbuf_man_destroy(struct vmw_cmdbuf_man *man)
1302{
1303 WARN_ON_ONCE(man->has_pool);
1304 (void) vmw_cmdbuf_idle(man, false, 10*HZ);
1305 if (vmw_cmdbuf_startstop(man, false))
1306 DRM_ERROR("Failed stopping command buffer context 0.\n");
1307
1308 vmw_generic_waiter_remove(man->dev_priv, SVGA_IRQFLAG_ERROR,
1309 &man->dev_priv->error_waiters);
1310 tasklet_kill(&man->tasklet);
1311 (void) cancel_work_sync(&man->work);
1312 dma_pool_destroy(man->dheaders);
1313 dma_pool_destroy(man->headers);
1314 mutex_destroy(&man->cur_mutex);
1315 mutex_destroy(&man->space_mutex);
1316 kfree(man);
1317}
1318