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13#include <linux/types.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/spinlock.h>
17#include <linux/bitrev.h>
18#include <linux/io.h>
19#include <linux/err.h>
20#include "ipu-prv.h"
21
22
23#define IC_CONF 0x0000
24#define IC_PRP_ENC_RSC 0x0004
25#define IC_PRP_VF_RSC 0x0008
26#define IC_PP_RSC 0x000C
27#define IC_CMBP_1 0x0010
28#define IC_CMBP_2 0x0014
29#define IC_IDMAC_1 0x0018
30#define IC_IDMAC_2 0x001C
31#define IC_IDMAC_3 0x0020
32#define IC_IDMAC_4 0x0024
33
34
35#define IC_CONF_PRPENC_EN (1 << 0)
36#define IC_CONF_PRPENC_CSC1 (1 << 1)
37#define IC_CONF_PRPENC_ROT_EN (1 << 2)
38#define IC_CONF_PRPVF_EN (1 << 8)
39#define IC_CONF_PRPVF_CSC1 (1 << 9)
40#define IC_CONF_PRPVF_CSC2 (1 << 10)
41#define IC_CONF_PRPVF_CMB (1 << 11)
42#define IC_CONF_PRPVF_ROT_EN (1 << 12)
43#define IC_CONF_PP_EN (1 << 16)
44#define IC_CONF_PP_CSC1 (1 << 17)
45#define IC_CONF_PP_CSC2 (1 << 18)
46#define IC_CONF_PP_CMB (1 << 19)
47#define IC_CONF_PP_ROT_EN (1 << 20)
48#define IC_CONF_IC_GLB_LOC_A (1 << 28)
49#define IC_CONF_KEY_COLOR_EN (1 << 29)
50#define IC_CONF_RWS_EN (1 << 30)
51#define IC_CONF_CSI_MEM_WR_EN (1 << 31)
52
53#define IC_IDMAC_1_CB0_BURST_16 (1 << 0)
54#define IC_IDMAC_1_CB1_BURST_16 (1 << 1)
55#define IC_IDMAC_1_CB2_BURST_16 (1 << 2)
56#define IC_IDMAC_1_CB3_BURST_16 (1 << 3)
57#define IC_IDMAC_1_CB4_BURST_16 (1 << 4)
58#define IC_IDMAC_1_CB5_BURST_16 (1 << 5)
59#define IC_IDMAC_1_CB6_BURST_16 (1 << 6)
60#define IC_IDMAC_1_CB7_BURST_16 (1 << 7)
61#define IC_IDMAC_1_PRPENC_ROT_MASK (0x7 << 11)
62#define IC_IDMAC_1_PRPENC_ROT_OFFSET 11
63#define IC_IDMAC_1_PRPVF_ROT_MASK (0x7 << 14)
64#define IC_IDMAC_1_PRPVF_ROT_OFFSET 14
65#define IC_IDMAC_1_PP_ROT_MASK (0x7 << 17)
66#define IC_IDMAC_1_PP_ROT_OFFSET 17
67#define IC_IDMAC_1_PP_FLIP_RS (1 << 22)
68#define IC_IDMAC_1_PRPVF_FLIP_RS (1 << 21)
69#define IC_IDMAC_1_PRPENC_FLIP_RS (1 << 20)
70
71#define IC_IDMAC_2_PRPENC_HEIGHT_MASK (0x3ff << 0)
72#define IC_IDMAC_2_PRPENC_HEIGHT_OFFSET 0
73#define IC_IDMAC_2_PRPVF_HEIGHT_MASK (0x3ff << 10)
74#define IC_IDMAC_2_PRPVF_HEIGHT_OFFSET 10
75#define IC_IDMAC_2_PP_HEIGHT_MASK (0x3ff << 20)
76#define IC_IDMAC_2_PP_HEIGHT_OFFSET 20
77
78#define IC_IDMAC_3_PRPENC_WIDTH_MASK (0x3ff << 0)
79#define IC_IDMAC_3_PRPENC_WIDTH_OFFSET 0
80#define IC_IDMAC_3_PRPVF_WIDTH_MASK (0x3ff << 10)
81#define IC_IDMAC_3_PRPVF_WIDTH_OFFSET 10
82#define IC_IDMAC_3_PP_WIDTH_MASK (0x3ff << 20)
83#define IC_IDMAC_3_PP_WIDTH_OFFSET 20
84
85struct ic_task_regoffs {
86 u32 rsc;
87 u32 tpmem_csc[2];
88};
89
90struct ic_task_bitfields {
91 u32 ic_conf_en;
92 u32 ic_conf_rot_en;
93 u32 ic_conf_cmb_en;
94 u32 ic_conf_csc1_en;
95 u32 ic_conf_csc2_en;
96 u32 ic_cmb_galpha_bit;
97};
98
99static const struct ic_task_regoffs ic_task_reg[IC_NUM_TASKS] = {
100 [IC_TASK_ENCODER] = {
101 .rsc = IC_PRP_ENC_RSC,
102 .tpmem_csc = {0x2008, 0},
103 },
104 [IC_TASK_VIEWFINDER] = {
105 .rsc = IC_PRP_VF_RSC,
106 .tpmem_csc = {0x4028, 0x4040},
107 },
108 [IC_TASK_POST_PROCESSOR] = {
109 .rsc = IC_PP_RSC,
110 .tpmem_csc = {0x6060, 0x6078},
111 },
112};
113
114static const struct ic_task_bitfields ic_task_bit[IC_NUM_TASKS] = {
115 [IC_TASK_ENCODER] = {
116 .ic_conf_en = IC_CONF_PRPENC_EN,
117 .ic_conf_rot_en = IC_CONF_PRPENC_ROT_EN,
118 .ic_conf_cmb_en = 0,
119 .ic_conf_csc1_en = IC_CONF_PRPENC_CSC1,
120 .ic_conf_csc2_en = 0,
121 .ic_cmb_galpha_bit = 0,
122 },
123 [IC_TASK_VIEWFINDER] = {
124 .ic_conf_en = IC_CONF_PRPVF_EN,
125 .ic_conf_rot_en = IC_CONF_PRPVF_ROT_EN,
126 .ic_conf_cmb_en = IC_CONF_PRPVF_CMB,
127 .ic_conf_csc1_en = IC_CONF_PRPVF_CSC1,
128 .ic_conf_csc2_en = IC_CONF_PRPVF_CSC2,
129 .ic_cmb_galpha_bit = 0,
130 },
131 [IC_TASK_POST_PROCESSOR] = {
132 .ic_conf_en = IC_CONF_PP_EN,
133 .ic_conf_rot_en = IC_CONF_PP_ROT_EN,
134 .ic_conf_cmb_en = IC_CONF_PP_CMB,
135 .ic_conf_csc1_en = IC_CONF_PP_CSC1,
136 .ic_conf_csc2_en = IC_CONF_PP_CSC2,
137 .ic_cmb_galpha_bit = 8,
138 },
139};
140
141struct ipu_ic_priv;
142
143struct ipu_ic {
144 enum ipu_ic_task task;
145 const struct ic_task_regoffs *reg;
146 const struct ic_task_bitfields *bit;
147
148 enum ipu_color_space in_cs, g_in_cs;
149 enum ipu_color_space out_cs;
150 bool graphics;
151 bool rotation;
152 bool in_use;
153
154 struct ipu_ic_priv *priv;
155};
156
157struct ipu_ic_priv {
158 void __iomem *base;
159 void __iomem *tpmem_base;
160 spinlock_t lock;
161 struct ipu_soc *ipu;
162 int use_count;
163 struct ipu_ic task[IC_NUM_TASKS];
164};
165
166static inline u32 ipu_ic_read(struct ipu_ic *ic, unsigned offset)
167{
168 return readl(ic->priv->base + offset);
169}
170
171static inline void ipu_ic_write(struct ipu_ic *ic, u32 value, unsigned offset)
172{
173 writel(value, ic->priv->base + offset);
174}
175
176struct ic_csc_params {
177 s16 coeff[3][3];
178 s16 offset[3];
179 u8 scale:2;
180 bool sat:1;
181};
182
183
184
185
186
187
188static const struct ic_csc_params ic_csc_rgb2ycbcr = {
189 .coeff = {
190 { 77, 150, 29 },
191 { 469, 427, 128 },
192 { 128, 405, 491 },
193 },
194 .offset = { 0, 512, 512 },
195 .scale = 1,
196};
197
198
199static const struct ic_csc_params ic_csc_rgb2rgb = {
200 .coeff = {
201 { 128, 0, 0 },
202 { 0, 128, 0 },
203 { 0, 0, 128 },
204 },
205 .scale = 2,
206};
207
208
209
210
211
212
213static const struct ic_csc_params ic_csc_ycbcr2rgb = {
214 .coeff = {
215 { 149, 0, 204 },
216 { 149, 462, 408 },
217 { 149, 255, 0 },
218 },
219 .offset = { -446, 266, -554 },
220 .scale = 2,
221};
222
223static int init_csc(struct ipu_ic *ic,
224 enum ipu_color_space inf,
225 enum ipu_color_space outf,
226 int csc_index)
227{
228 struct ipu_ic_priv *priv = ic->priv;
229 const struct ic_csc_params *params;
230 u32 __iomem *base;
231 const u16 (*c)[3];
232 const u16 *a;
233 u32 param;
234
235 base = (u32 __iomem *)
236 (priv->tpmem_base + ic->reg->tpmem_csc[csc_index]);
237
238 if (inf == IPUV3_COLORSPACE_YUV && outf == IPUV3_COLORSPACE_RGB)
239 params = &ic_csc_ycbcr2rgb;
240 else if (inf == IPUV3_COLORSPACE_RGB && outf == IPUV3_COLORSPACE_YUV)
241 params = &ic_csc_rgb2ycbcr;
242 else if (inf == IPUV3_COLORSPACE_RGB && outf == IPUV3_COLORSPACE_RGB)
243 params = &ic_csc_rgb2rgb;
244 else {
245 dev_err(priv->ipu->dev, "Unsupported color space conversion\n");
246 return -EINVAL;
247 }
248
249
250 c = (const u16 (*)[3])params->coeff;
251 a = (const u16 *)params->offset;
252
253 param = ((a[0] & 0x1f) << 27) | ((c[0][0] & 0x1ff) << 18) |
254 ((c[1][1] & 0x1ff) << 9) | (c[2][2] & 0x1ff);
255 writel(param, base++);
256
257 param = ((a[0] & 0x1fe0) >> 5) | (params->scale << 8) |
258 (params->sat << 9);
259 writel(param, base++);
260
261 param = ((a[1] & 0x1f) << 27) | ((c[0][1] & 0x1ff) << 18) |
262 ((c[1][0] & 0x1ff) << 9) | (c[2][0] & 0x1ff);
263 writel(param, base++);
264
265 param = ((a[1] & 0x1fe0) >> 5);
266 writel(param, base++);
267
268 param = ((a[2] & 0x1f) << 27) | ((c[0][2] & 0x1ff) << 18) |
269 ((c[1][2] & 0x1ff) << 9) | (c[2][1] & 0x1ff);
270 writel(param, base++);
271
272 param = ((a[2] & 0x1fe0) >> 5);
273 writel(param, base++);
274
275 return 0;
276}
277
278static int calc_resize_coeffs(struct ipu_ic *ic,
279 u32 in_size, u32 out_size,
280 u32 *resize_coeff,
281 u32 *downsize_coeff)
282{
283 struct ipu_ic_priv *priv = ic->priv;
284 struct ipu_soc *ipu = priv->ipu;
285 u32 temp_size, temp_downsize;
286
287
288
289
290
291 if (in_size > 4096) {
292 dev_err(ipu->dev, "Unsupported resize (in_size > 4096)\n");
293 return -EINVAL;
294 }
295 if (out_size > 1024) {
296 dev_err(ipu->dev, "Unsupported resize (out_size > 1024)\n");
297 return -EINVAL;
298 }
299
300
301 if ((out_size << 2) < in_size) {
302 dev_err(ipu->dev, "Unsupported downsize\n");
303 return -EINVAL;
304 }
305
306
307 temp_downsize = 0;
308 temp_size = in_size;
309 while (((temp_size > 1024) || (temp_size >= out_size * 2)) &&
310 (temp_downsize < 2)) {
311 temp_size >>= 1;
312 temp_downsize++;
313 }
314 *downsize_coeff = temp_downsize;
315
316
317
318
319
320
321 *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
322 if (*resize_coeff >= 16384L) {
323 dev_err(ipu->dev, "Warning! Overflow on resize coeff.\n");
324 *resize_coeff = 0x3FFF;
325 }
326
327 return 0;
328}
329
330void ipu_ic_task_enable(struct ipu_ic *ic)
331{
332 struct ipu_ic_priv *priv = ic->priv;
333 unsigned long flags;
334 u32 ic_conf;
335
336 spin_lock_irqsave(&priv->lock, flags);
337
338 ic_conf = ipu_ic_read(ic, IC_CONF);
339
340 ic_conf |= ic->bit->ic_conf_en;
341
342 if (ic->rotation)
343 ic_conf |= ic->bit->ic_conf_rot_en;
344
345 if (ic->in_cs != ic->out_cs)
346 ic_conf |= ic->bit->ic_conf_csc1_en;
347
348 if (ic->graphics) {
349 ic_conf |= ic->bit->ic_conf_cmb_en;
350 ic_conf |= ic->bit->ic_conf_csc1_en;
351
352 if (ic->g_in_cs != ic->out_cs)
353 ic_conf |= ic->bit->ic_conf_csc2_en;
354 }
355
356 ipu_ic_write(ic, ic_conf, IC_CONF);
357
358 spin_unlock_irqrestore(&priv->lock, flags);
359}
360EXPORT_SYMBOL_GPL(ipu_ic_task_enable);
361
362void ipu_ic_task_disable(struct ipu_ic *ic)
363{
364 struct ipu_ic_priv *priv = ic->priv;
365 unsigned long flags;
366 u32 ic_conf;
367
368 spin_lock_irqsave(&priv->lock, flags);
369
370 ic_conf = ipu_ic_read(ic, IC_CONF);
371
372 ic_conf &= ~(ic->bit->ic_conf_en |
373 ic->bit->ic_conf_csc1_en |
374 ic->bit->ic_conf_rot_en);
375 if (ic->bit->ic_conf_csc2_en)
376 ic_conf &= ~ic->bit->ic_conf_csc2_en;
377 if (ic->bit->ic_conf_cmb_en)
378 ic_conf &= ~ic->bit->ic_conf_cmb_en;
379
380 ipu_ic_write(ic, ic_conf, IC_CONF);
381
382 ic->rotation = ic->graphics = false;
383
384 spin_unlock_irqrestore(&priv->lock, flags);
385}
386EXPORT_SYMBOL_GPL(ipu_ic_task_disable);
387
388int ipu_ic_task_graphics_init(struct ipu_ic *ic,
389 enum ipu_color_space in_g_cs,
390 bool galpha_en, u32 galpha,
391 bool colorkey_en, u32 colorkey)
392{
393 struct ipu_ic_priv *priv = ic->priv;
394 unsigned long flags;
395 u32 reg, ic_conf;
396 int ret = 0;
397
398 if (ic->task == IC_TASK_ENCODER)
399 return -EINVAL;
400
401 spin_lock_irqsave(&priv->lock, flags);
402
403 ic_conf = ipu_ic_read(ic, IC_CONF);
404
405 if (!(ic_conf & ic->bit->ic_conf_csc1_en)) {
406
407 ret = init_csc(ic, IPUV3_COLORSPACE_RGB,
408 IPUV3_COLORSPACE_RGB, 0);
409 if (ret)
410 goto unlock;
411 }
412
413 ic->g_in_cs = in_g_cs;
414
415 if (ic->g_in_cs != ic->out_cs) {
416 ret = init_csc(ic, ic->g_in_cs, ic->out_cs, 1);
417 if (ret)
418 goto unlock;
419 }
420
421 if (galpha_en) {
422 ic_conf |= IC_CONF_IC_GLB_LOC_A;
423 reg = ipu_ic_read(ic, IC_CMBP_1);
424 reg &= ~(0xff << ic->bit->ic_cmb_galpha_bit);
425 reg |= (galpha << ic->bit->ic_cmb_galpha_bit);
426 ipu_ic_write(ic, reg, IC_CMBP_1);
427 } else
428 ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
429
430 if (colorkey_en) {
431 ic_conf |= IC_CONF_KEY_COLOR_EN;
432 ipu_ic_write(ic, colorkey, IC_CMBP_2);
433 } else
434 ic_conf &= ~IC_CONF_KEY_COLOR_EN;
435
436 ipu_ic_write(ic, ic_conf, IC_CONF);
437
438 ic->graphics = true;
439unlock:
440 spin_unlock_irqrestore(&priv->lock, flags);
441 return ret;
442}
443EXPORT_SYMBOL_GPL(ipu_ic_task_graphics_init);
444
445int ipu_ic_task_init(struct ipu_ic *ic,
446 int in_width, int in_height,
447 int out_width, int out_height,
448 enum ipu_color_space in_cs,
449 enum ipu_color_space out_cs)
450{
451 struct ipu_ic_priv *priv = ic->priv;
452 u32 reg, downsize_coeff, resize_coeff;
453 unsigned long flags;
454 int ret = 0;
455
456
457 ret = calc_resize_coeffs(ic, in_height, out_height,
458 &resize_coeff, &downsize_coeff);
459 if (ret)
460 return ret;
461
462 reg = (downsize_coeff << 30) | (resize_coeff << 16);
463
464
465 ret = calc_resize_coeffs(ic, in_width, out_width,
466 &resize_coeff, &downsize_coeff);
467 if (ret)
468 return ret;
469
470 reg |= (downsize_coeff << 14) | resize_coeff;
471
472 spin_lock_irqsave(&priv->lock, flags);
473
474 ipu_ic_write(ic, reg, ic->reg->rsc);
475
476
477 ic->in_cs = in_cs;
478 ic->out_cs = out_cs;
479
480 if (ic->in_cs != ic->out_cs) {
481 ret = init_csc(ic, ic->in_cs, ic->out_cs, 0);
482 if (ret)
483 goto unlock;
484 }
485
486unlock:
487 spin_unlock_irqrestore(&priv->lock, flags);
488 return ret;
489}
490EXPORT_SYMBOL_GPL(ipu_ic_task_init);
491
492int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
493 u32 width, u32 height, int burst_size,
494 enum ipu_rotate_mode rot)
495{
496 struct ipu_ic_priv *priv = ic->priv;
497 struct ipu_soc *ipu = priv->ipu;
498 u32 ic_idmac_1, ic_idmac_2, ic_idmac_3;
499 u32 temp_rot = bitrev8(rot) >> 5;
500 bool need_hor_flip = false;
501 unsigned long flags;
502 int ret = 0;
503
504 if ((burst_size != 8) && (burst_size != 16)) {
505 dev_err(ipu->dev, "Illegal burst length for IC\n");
506 return -EINVAL;
507 }
508
509 width--;
510 height--;
511
512 if (temp_rot & 0x2)
513 need_hor_flip = true;
514
515 spin_lock_irqsave(&priv->lock, flags);
516
517 ic_idmac_1 = ipu_ic_read(ic, IC_IDMAC_1);
518 ic_idmac_2 = ipu_ic_read(ic, IC_IDMAC_2);
519 ic_idmac_3 = ipu_ic_read(ic, IC_IDMAC_3);
520
521 switch (channel->num) {
522 case IPUV3_CHANNEL_IC_PP_MEM:
523 if (burst_size == 16)
524 ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16;
525 else
526 ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16;
527
528 if (need_hor_flip)
529 ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS;
530 else
531 ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS;
532
533 ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK;
534 ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET;
535
536 ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK;
537 ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET;
538 break;
539 case IPUV3_CHANNEL_MEM_IC_PP:
540 if (burst_size == 16)
541 ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16;
542 else
543 ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16;
544 break;
545 case IPUV3_CHANNEL_MEM_ROT_PP:
546 ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK;
547 ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET;
548 break;
549 case IPUV3_CHANNEL_MEM_IC_PRP_VF:
550 if (burst_size == 16)
551 ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16;
552 else
553 ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16;
554 break;
555 case IPUV3_CHANNEL_IC_PRP_ENC_MEM:
556 if (burst_size == 16)
557 ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16;
558 else
559 ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16;
560
561 if (need_hor_flip)
562 ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS;
563 else
564 ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS;
565
566 ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK;
567 ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET;
568
569 ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK;
570 ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET;
571 break;
572 case IPUV3_CHANNEL_MEM_ROT_ENC:
573 ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK;
574 ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET;
575 break;
576 case IPUV3_CHANNEL_IC_PRP_VF_MEM:
577 if (burst_size == 16)
578 ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16;
579 else
580 ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16;
581
582 if (need_hor_flip)
583 ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS;
584 else
585 ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS;
586
587 ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK;
588 ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET;
589
590 ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK;
591 ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET;
592 break;
593 case IPUV3_CHANNEL_MEM_ROT_VF:
594 ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK;
595 ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET;
596 break;
597 case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
598 if (burst_size == 16)
599 ic_idmac_1 |= IC_IDMAC_1_CB3_BURST_16;
600 else
601 ic_idmac_1 &= ~IC_IDMAC_1_CB3_BURST_16;
602 break;
603 case IPUV3_CHANNEL_G_MEM_IC_PP:
604 if (burst_size == 16)
605 ic_idmac_1 |= IC_IDMAC_1_CB4_BURST_16;
606 else
607 ic_idmac_1 &= ~IC_IDMAC_1_CB4_BURST_16;
608 break;
609 case IPUV3_CHANNEL_VDI_MEM_IC_VF:
610 if (burst_size == 16)
611 ic_idmac_1 |= IC_IDMAC_1_CB7_BURST_16;
612 else
613 ic_idmac_1 &= ~IC_IDMAC_1_CB7_BURST_16;
614 break;
615 default:
616 goto unlock;
617 }
618
619 ipu_ic_write(ic, ic_idmac_1, IC_IDMAC_1);
620 ipu_ic_write(ic, ic_idmac_2, IC_IDMAC_2);
621 ipu_ic_write(ic, ic_idmac_3, IC_IDMAC_3);
622
623 if (rot >= IPU_ROTATE_90_RIGHT)
624 ic->rotation = true;
625
626unlock:
627 spin_unlock_irqrestore(&priv->lock, flags);
628 return ret;
629}
630EXPORT_SYMBOL_GPL(ipu_ic_task_idma_init);
631
632int ipu_ic_enable(struct ipu_ic *ic)
633{
634 struct ipu_ic_priv *priv = ic->priv;
635 unsigned long flags;
636 u32 module = IPU_CONF_IC_EN;
637
638 spin_lock_irqsave(&priv->lock, flags);
639
640 if (ic->rotation)
641 module |= IPU_CONF_ROT_EN;
642
643 if (!priv->use_count)
644 ipu_module_enable(priv->ipu, module);
645
646 priv->use_count++;
647
648 spin_unlock_irqrestore(&priv->lock, flags);
649
650 return 0;
651}
652EXPORT_SYMBOL_GPL(ipu_ic_enable);
653
654int ipu_ic_disable(struct ipu_ic *ic)
655{
656 struct ipu_ic_priv *priv = ic->priv;
657 unsigned long flags;
658 u32 module = IPU_CONF_IC_EN | IPU_CONF_ROT_EN;
659
660 spin_lock_irqsave(&priv->lock, flags);
661
662 priv->use_count--;
663
664 if (!priv->use_count)
665 ipu_module_disable(priv->ipu, module);
666
667 if (priv->use_count < 0)
668 priv->use_count = 0;
669
670 spin_unlock_irqrestore(&priv->lock, flags);
671
672 return 0;
673}
674EXPORT_SYMBOL_GPL(ipu_ic_disable);
675
676struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task)
677{
678 struct ipu_ic_priv *priv = ipu->ic_priv;
679 unsigned long flags;
680 struct ipu_ic *ic, *ret;
681
682 if (task >= IC_NUM_TASKS)
683 return ERR_PTR(-EINVAL);
684
685 ic = &priv->task[task];
686
687 spin_lock_irqsave(&priv->lock, flags);
688
689 if (ic->in_use) {
690 ret = ERR_PTR(-EBUSY);
691 goto unlock;
692 }
693
694 ic->in_use = true;
695 ret = ic;
696
697unlock:
698 spin_unlock_irqrestore(&priv->lock, flags);
699 return ret;
700}
701EXPORT_SYMBOL_GPL(ipu_ic_get);
702
703void ipu_ic_put(struct ipu_ic *ic)
704{
705 struct ipu_ic_priv *priv = ic->priv;
706 unsigned long flags;
707
708 spin_lock_irqsave(&priv->lock, flags);
709 ic->in_use = false;
710 spin_unlock_irqrestore(&priv->lock, flags);
711}
712EXPORT_SYMBOL_GPL(ipu_ic_put);
713
714int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
715 unsigned long base, unsigned long tpmem_base)
716{
717 struct ipu_ic_priv *priv;
718 int i;
719
720 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
721 if (!priv)
722 return -ENOMEM;
723
724 ipu->ic_priv = priv;
725
726 spin_lock_init(&priv->lock);
727 priv->base = devm_ioremap(dev, base, PAGE_SIZE);
728 if (!priv->base)
729 return -ENOMEM;
730 priv->tpmem_base = devm_ioremap(dev, tpmem_base, SZ_64K);
731 if (!priv->tpmem_base)
732 return -ENOMEM;
733
734 dev_dbg(dev, "IC base: 0x%08lx remapped to %p\n", base, priv->base);
735
736 priv->ipu = ipu;
737
738 for (i = 0; i < IC_NUM_TASKS; i++) {
739 priv->task[i].task = i;
740 priv->task[i].priv = priv;
741 priv->task[i].reg = &ic_task_reg[i];
742 priv->task[i].bit = &ic_task_bit[i];
743 }
744
745 return 0;
746}
747
748void ipu_ic_exit(struct ipu_soc *ipu)
749{
750}
751
752void ipu_ic_dump(struct ipu_ic *ic)
753{
754 struct ipu_ic_priv *priv = ic->priv;
755 struct ipu_soc *ipu = priv->ipu;
756
757 dev_dbg(ipu->dev, "IC_CONF = \t0x%08X\n",
758 ipu_ic_read(ic, IC_CONF));
759 dev_dbg(ipu->dev, "IC_PRP_ENC_RSC = \t0x%08X\n",
760 ipu_ic_read(ic, IC_PRP_ENC_RSC));
761 dev_dbg(ipu->dev, "IC_PRP_VF_RSC = \t0x%08X\n",
762 ipu_ic_read(ic, IC_PRP_VF_RSC));
763 dev_dbg(ipu->dev, "IC_PP_RSC = \t0x%08X\n",
764 ipu_ic_read(ic, IC_PP_RSC));
765 dev_dbg(ipu->dev, "IC_CMBP_1 = \t0x%08X\n",
766 ipu_ic_read(ic, IC_CMBP_1));
767 dev_dbg(ipu->dev, "IC_CMBP_2 = \t0x%08X\n",
768 ipu_ic_read(ic, IC_CMBP_2));
769 dev_dbg(ipu->dev, "IC_IDMAC_1 = \t0x%08X\n",
770 ipu_ic_read(ic, IC_IDMAC_1));
771 dev_dbg(ipu->dev, "IC_IDMAC_2 = \t0x%08X\n",
772 ipu_ic_read(ic, IC_IDMAC_2));
773 dev_dbg(ipu->dev, "IC_IDMAC_3 = \t0x%08X\n",
774 ipu_ic_read(ic, IC_IDMAC_3));
775 dev_dbg(ipu->dev, "IC_IDMAC_4 = \t0x%08X\n",
776 ipu_ic_read(ic, IC_IDMAC_4));
777}
778EXPORT_SYMBOL_GPL(ipu_ic_dump);
779
