1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#include <linux/clk.h>
21#include <linux/completion.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/err.h>
25#include <linux/i2c.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/module.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/platform_device.h>
32#include <linux/slab.h>
33#include <linux/platform_data/dma-atmel.h>
34#include <linux/pm_runtime.h>
35#include <linux/pinctrl/consumer.h>
36
37#define DEFAULT_TWI_CLK_HZ 100000
38#define AT91_I2C_TIMEOUT msecs_to_jiffies(100)
39#define AT91_I2C_DMA_THRESHOLD 8
40#define AUTOSUSPEND_TIMEOUT 2000
41
42
43#define AT91_TWI_CR 0x0000
44#define AT91_TWI_START BIT(0)
45#define AT91_TWI_STOP BIT(1)
46#define AT91_TWI_MSEN BIT(2)
47#define AT91_TWI_MSDIS BIT(3)
48#define AT91_TWI_SVEN BIT(4)
49#define AT91_TWI_SVDIS BIT(5)
50#define AT91_TWI_QUICK BIT(6)
51#define AT91_TWI_SWRST BIT(7)
52#define AT91_TWI_ACMEN BIT(16)
53#define AT91_TWI_ACMDIS BIT(17)
54#define AT91_TWI_THRCLR BIT(24)
55#define AT91_TWI_RHRCLR BIT(25)
56#define AT91_TWI_LOCKCLR BIT(26)
57#define AT91_TWI_FIFOEN BIT(28)
58#define AT91_TWI_FIFODIS BIT(29)
59
60#define AT91_TWI_MMR 0x0004
61#define AT91_TWI_IADRSZ_1 0x0100
62#define AT91_TWI_MREAD BIT(12)
63
64#define AT91_TWI_IADR 0x000c
65
66#define AT91_TWI_CWGR 0x0010
67
68#define AT91_TWI_SR 0x0020
69#define AT91_TWI_TXCOMP BIT(0)
70#define AT91_TWI_RXRDY BIT(1)
71#define AT91_TWI_TXRDY BIT(2)
72#define AT91_TWI_OVRE BIT(6)
73#define AT91_TWI_UNRE BIT(7)
74#define AT91_TWI_NACK BIT(8)
75#define AT91_TWI_LOCK BIT(23)
76
77#define AT91_TWI_INT_MASK \
78 (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK)
79
80#define AT91_TWI_IER 0x0024
81#define AT91_TWI_IDR 0x0028
82#define AT91_TWI_IMR 0x002c
83#define AT91_TWI_RHR 0x0030
84#define AT91_TWI_THR 0x0034
85
86#define AT91_TWI_ACR 0x0040
87#define AT91_TWI_ACR_DATAL(len) ((len) & 0xff)
88#define AT91_TWI_ACR_DIR BIT(8)
89
90#define AT91_TWI_FMR 0x0050
91#define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0)
92#define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0)
93#define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4)
94#define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4)
95#define AT91_TWI_ONE_DATA 0x0
96#define AT91_TWI_TWO_DATA 0x1
97#define AT91_TWI_FOUR_DATA 0x2
98
99#define AT91_TWI_FLR 0x0054
100
101#define AT91_TWI_FSR 0x0060
102#define AT91_TWI_FIER 0x0064
103#define AT91_TWI_FIDR 0x0068
104#define AT91_TWI_FIMR 0x006c
105
106#define AT91_TWI_VER 0x00fc
107
108struct at91_twi_pdata {
109 unsigned clk_max_div;
110 unsigned clk_offset;
111 bool has_unre_flag;
112 bool has_alt_cmd;
113 struct at_dma_slave dma_slave;
114};
115
116struct at91_twi_dma {
117 struct dma_chan *chan_rx;
118 struct dma_chan *chan_tx;
119 struct scatterlist sg[2];
120 struct dma_async_tx_descriptor *data_desc;
121 enum dma_data_direction direction;
122 bool buf_mapped;
123 bool xfer_in_progress;
124};
125
126struct at91_twi_dev {
127 struct device *dev;
128 void __iomem *base;
129 struct completion cmd_complete;
130 struct clk *clk;
131 u8 *buf;
132 size_t buf_len;
133 struct i2c_msg *msg;
134 int irq;
135 unsigned imr;
136 unsigned transfer_status;
137 struct i2c_adapter adapter;
138 unsigned twi_cwgr_reg;
139 struct at91_twi_pdata *pdata;
140 bool use_dma;
141 bool recv_len_abort;
142 u32 fifo_size;
143 struct at91_twi_dma dma;
144};
145
146static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
147{
148 return readl_relaxed(dev->base + reg);
149}
150
151static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
152{
153 writel_relaxed(val, dev->base + reg);
154}
155
156static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
157{
158 at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_INT_MASK);
159}
160
161static void at91_twi_irq_save(struct at91_twi_dev *dev)
162{
163 dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & AT91_TWI_INT_MASK;
164 at91_disable_twi_interrupts(dev);
165}
166
167static void at91_twi_irq_restore(struct at91_twi_dev *dev)
168{
169 at91_twi_write(dev, AT91_TWI_IER, dev->imr);
170}
171
172static void at91_init_twi_bus(struct at91_twi_dev *dev)
173{
174 at91_disable_twi_interrupts(dev);
175 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
176
177 if (dev->fifo_size)
178 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_FIFOEN);
179 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
180 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
181 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
182}
183
184
185
186
187
188static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
189{
190 int ckdiv, cdiv, div;
191 struct at91_twi_pdata *pdata = dev->pdata;
192 int offset = pdata->clk_offset;
193 int max_ckdiv = pdata->clk_max_div;
194
195 div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
196 2 * twi_clk) - offset);
197 ckdiv = fls(div >> 8);
198 cdiv = div >> ckdiv;
199
200 if (ckdiv > max_ckdiv) {
201 dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
202 ckdiv, max_ckdiv);
203 ckdiv = max_ckdiv;
204 cdiv = 255;
205 }
206
207 dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
208 dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
209}
210
211static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
212{
213 struct at91_twi_dma *dma = &dev->dma;
214
215 at91_twi_irq_save(dev);
216
217 if (dma->xfer_in_progress) {
218 if (dma->direction == DMA_FROM_DEVICE)
219 dmaengine_terminate_all(dma->chan_rx);
220 else
221 dmaengine_terminate_all(dma->chan_tx);
222 dma->xfer_in_progress = false;
223 }
224 if (dma->buf_mapped) {
225 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg[0]),
226 dev->buf_len, dma->direction);
227 dma->buf_mapped = false;
228 }
229
230 at91_twi_irq_restore(dev);
231}
232
233static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
234{
235 if (!dev->buf_len)
236 return;
237
238
239 writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR);
240
241
242 if (--dev->buf_len == 0)
243 if (!dev->pdata->has_alt_cmd)
244 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
245
246 dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len);
247
248 ++dev->buf;
249}
250
251static void at91_twi_write_data_dma_callback(void *data)
252{
253 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
254
255 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
256 dev->buf_len, DMA_TO_DEVICE);
257
258
259
260
261
262
263
264
265 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
266 if (!dev->pdata->has_alt_cmd)
267 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
268}
269
270static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
271{
272 dma_addr_t dma_addr;
273 struct dma_async_tx_descriptor *txdesc;
274 struct at91_twi_dma *dma = &dev->dma;
275 struct dma_chan *chan_tx = dma->chan_tx;
276 unsigned int sg_len = 1;
277
278 if (!dev->buf_len)
279 return;
280
281 dma->direction = DMA_TO_DEVICE;
282
283 at91_twi_irq_save(dev);
284 dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
285 DMA_TO_DEVICE);
286 if (dma_mapping_error(dev->dev, dma_addr)) {
287 dev_err(dev->dev, "dma map failed\n");
288 return;
289 }
290 dma->buf_mapped = true;
291 at91_twi_irq_restore(dev);
292
293 if (dev->fifo_size) {
294 size_t part1_len, part2_len;
295 struct scatterlist *sg;
296 unsigned fifo_mr;
297
298 sg_len = 0;
299
300 part1_len = dev->buf_len & ~0x3;
301 if (part1_len) {
302 sg = &dma->sg[sg_len++];
303 sg_dma_len(sg) = part1_len;
304 sg_dma_address(sg) = dma_addr;
305 }
306
307 part2_len = dev->buf_len & 0x3;
308 if (part2_len) {
309 sg = &dma->sg[sg_len++];
310 sg_dma_len(sg) = part2_len;
311 sg_dma_address(sg) = dma_addr + part1_len;
312 }
313
314
315
316
317
318 fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
319 fifo_mr &= ~AT91_TWI_FMR_TXRDYM_MASK;
320 fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_FOUR_DATA);
321 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
322 } else {
323 sg_dma_len(&dma->sg[0]) = dev->buf_len;
324 sg_dma_address(&dma->sg[0]) = dma_addr;
325 }
326
327 txdesc = dmaengine_prep_slave_sg(chan_tx, dma->sg, sg_len,
328 DMA_MEM_TO_DEV,
329 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
330 if (!txdesc) {
331 dev_err(dev->dev, "dma prep slave sg failed\n");
332 goto error;
333 }
334
335 txdesc->callback = at91_twi_write_data_dma_callback;
336 txdesc->callback_param = dev;
337
338 dma->xfer_in_progress = true;
339 dmaengine_submit(txdesc);
340 dma_async_issue_pending(chan_tx);
341
342 return;
343
344error:
345 at91_twi_dma_cleanup(dev);
346}
347
348static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
349{
350 if (!dev->buf_len)
351 return;
352
353
354 *dev->buf = readb_relaxed(dev->base + AT91_TWI_RHR);
355 --dev->buf_len;
356
357
358 if (dev->recv_len_abort)
359 return;
360
361
362 if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
363
364 if (*dev->buf <= I2C_SMBUS_BLOCK_MAX && *dev->buf > 0) {
365 dev->msg->flags &= ~I2C_M_RECV_LEN;
366 dev->buf_len += *dev->buf;
367 dev->msg->len = dev->buf_len + 1;
368 dev_dbg(dev->dev, "received block length %d\n",
369 dev->buf_len);
370 } else {
371
372 dev->recv_len_abort = true;
373 dev->buf_len = 1;
374 }
375 }
376
377
378 if (!dev->pdata->has_alt_cmd && dev->buf_len == 1)
379 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
380
381 dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len);
382
383 ++dev->buf;
384}
385
386static void at91_twi_read_data_dma_callback(void *data)
387{
388 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
389 unsigned ier = AT91_TWI_TXCOMP;
390
391 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
392 dev->buf_len, DMA_FROM_DEVICE);
393
394 if (!dev->pdata->has_alt_cmd) {
395
396 dev->buf += dev->buf_len - 2;
397 dev->buf_len = 2;
398 ier |= AT91_TWI_RXRDY;
399 }
400 at91_twi_write(dev, AT91_TWI_IER, ier);
401}
402
403static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
404{
405 dma_addr_t dma_addr;
406 struct dma_async_tx_descriptor *rxdesc;
407 struct at91_twi_dma *dma = &dev->dma;
408 struct dma_chan *chan_rx = dma->chan_rx;
409 size_t buf_len;
410
411 buf_len = (dev->pdata->has_alt_cmd) ? dev->buf_len : dev->buf_len - 2;
412 dma->direction = DMA_FROM_DEVICE;
413
414
415 at91_twi_irq_save(dev);
416 dma_addr = dma_map_single(dev->dev, dev->buf, buf_len, DMA_FROM_DEVICE);
417 if (dma_mapping_error(dev->dev, dma_addr)) {
418 dev_err(dev->dev, "dma map failed\n");
419 return;
420 }
421 dma->buf_mapped = true;
422 at91_twi_irq_restore(dev);
423
424 if (dev->fifo_size && IS_ALIGNED(buf_len, 4)) {
425 unsigned fifo_mr;
426
427
428
429
430
431 fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
432 fifo_mr &= ~AT91_TWI_FMR_RXRDYM_MASK;
433 fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_FOUR_DATA);
434 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
435 }
436
437 sg_dma_len(&dma->sg[0]) = buf_len;
438 sg_dma_address(&dma->sg[0]) = dma_addr;
439
440 rxdesc = dmaengine_prep_slave_sg(chan_rx, dma->sg, 1, DMA_DEV_TO_MEM,
441 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
442 if (!rxdesc) {
443 dev_err(dev->dev, "dma prep slave sg failed\n");
444 goto error;
445 }
446
447 rxdesc->callback = at91_twi_read_data_dma_callback;
448 rxdesc->callback_param = dev;
449
450 dma->xfer_in_progress = true;
451 dmaengine_submit(rxdesc);
452 dma_async_issue_pending(dma->chan_rx);
453
454 return;
455
456error:
457 at91_twi_dma_cleanup(dev);
458}
459
460static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
461{
462 struct at91_twi_dev *dev = dev_id;
463 const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
464 const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
465
466 if (!irqstatus)
467 return IRQ_NONE;
468 else if (irqstatus & AT91_TWI_RXRDY)
469 at91_twi_read_next_byte(dev);
470 else if (irqstatus & AT91_TWI_TXRDY)
471 at91_twi_write_next_byte(dev);
472
473
474 dev->transfer_status |= status;
475
476 if (irqstatus & (AT91_TWI_TXCOMP | AT91_TWI_NACK)) {
477 at91_disable_twi_interrupts(dev);
478 complete(&dev->cmd_complete);
479 }
480
481 return IRQ_HANDLED;
482}
483
484static int at91_do_twi_transfer(struct at91_twi_dev *dev)
485{
486 int ret;
487 unsigned long time_left;
488 bool has_unre_flag = dev->pdata->has_unre_flag;
489 bool has_alt_cmd = dev->pdata->has_alt_cmd;
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534 dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
535 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
536
537 reinit_completion(&dev->cmd_complete);
538 dev->transfer_status = 0;
539
540 if (dev->fifo_size) {
541 unsigned fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
542
543
544 fifo_mr &= ~(AT91_TWI_FMR_TXRDYM_MASK |
545 AT91_TWI_FMR_RXRDYM_MASK);
546 fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_ONE_DATA);
547 fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_ONE_DATA);
548 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
549
550
551 at91_twi_write(dev, AT91_TWI_CR,
552 AT91_TWI_THRCLR | AT91_TWI_RHRCLR);
553 }
554
555 if (!dev->buf_len) {
556 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
557 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
558 } else if (dev->msg->flags & I2C_M_RD) {
559 unsigned start_flags = AT91_TWI_START;
560
561 if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
562 dev_err(dev->dev, "RXRDY still set!");
563 at91_twi_read(dev, AT91_TWI_RHR);
564 }
565
566
567 if (!has_alt_cmd && dev->buf_len <= 1 &&
568 !(dev->msg->flags & I2C_M_RECV_LEN))
569 start_flags |= AT91_TWI_STOP;
570 at91_twi_write(dev, AT91_TWI_CR, start_flags);
571
572
573
574
575
576
577
578
579
580 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
581 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
582 at91_twi_read_data_dma(dev);
583 } else {
584 at91_twi_write(dev, AT91_TWI_IER,
585 AT91_TWI_TXCOMP |
586 AT91_TWI_NACK |
587 AT91_TWI_RXRDY);
588 }
589 } else {
590 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
591 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
592 at91_twi_write_data_dma(dev);
593 } else {
594 at91_twi_write_next_byte(dev);
595 at91_twi_write(dev, AT91_TWI_IER,
596 AT91_TWI_TXCOMP |
597 AT91_TWI_NACK |
598 AT91_TWI_TXRDY);
599 }
600 }
601
602 time_left = wait_for_completion_timeout(&dev->cmd_complete,
603 dev->adapter.timeout);
604 if (time_left == 0) {
605 dev->transfer_status |= at91_twi_read(dev, AT91_TWI_SR);
606 dev_err(dev->dev, "controller timed out\n");
607 at91_init_twi_bus(dev);
608 ret = -ETIMEDOUT;
609 goto error;
610 }
611 if (dev->transfer_status & AT91_TWI_NACK) {
612 dev_dbg(dev->dev, "received nack\n");
613 ret = -EREMOTEIO;
614 goto error;
615 }
616 if (dev->transfer_status & AT91_TWI_OVRE) {
617 dev_err(dev->dev, "overrun while reading\n");
618 ret = -EIO;
619 goto error;
620 }
621 if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
622 dev_err(dev->dev, "underrun while writing\n");
623 ret = -EIO;
624 goto error;
625 }
626 if ((has_alt_cmd || dev->fifo_size) &&
627 (dev->transfer_status & AT91_TWI_LOCK)) {
628 dev_err(dev->dev, "tx locked\n");
629 ret = -EIO;
630 goto error;
631 }
632 if (dev->recv_len_abort) {
633 dev_err(dev->dev, "invalid smbus block length recvd\n");
634 ret = -EPROTO;
635 goto error;
636 }
637
638 dev_dbg(dev->dev, "transfer complete\n");
639
640 return 0;
641
642error:
643
644 at91_twi_dma_cleanup(dev);
645
646 if ((has_alt_cmd || dev->fifo_size) &&
647 (dev->transfer_status & AT91_TWI_LOCK)) {
648 dev_dbg(dev->dev, "unlock tx\n");
649 at91_twi_write(dev, AT91_TWI_CR,
650 AT91_TWI_THRCLR | AT91_TWI_LOCKCLR);
651 }
652 return ret;
653}
654
655static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
656{
657 struct at91_twi_dev *dev = i2c_get_adapdata(adap);
658 int ret;
659 unsigned int_addr_flag = 0;
660 struct i2c_msg *m_start = msg;
661 bool is_read, use_alt_cmd = false;
662
663 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
664
665 ret = pm_runtime_get_sync(dev->dev);
666 if (ret < 0)
667 goto out;
668
669 if (num == 2) {
670 int internal_address = 0;
671 int i;
672
673
674 m_start = &msg[1];
675 for (i = 0; i < msg->len; ++i) {
676 const unsigned addr = msg->buf[msg->len - 1 - i];
677
678 internal_address |= addr << (8 * i);
679 int_addr_flag += AT91_TWI_IADRSZ_1;
680 }
681 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
682 }
683
684 is_read = (m_start->flags & I2C_M_RD);
685 if (dev->pdata->has_alt_cmd) {
686 if (m_start->len > 0) {
687 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMEN);
688 at91_twi_write(dev, AT91_TWI_ACR,
689 AT91_TWI_ACR_DATAL(m_start->len) |
690 ((is_read) ? AT91_TWI_ACR_DIR : 0));
691 use_alt_cmd = true;
692 } else {
693 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMDIS);
694 }
695 }
696
697 at91_twi_write(dev, AT91_TWI_MMR,
698 (m_start->addr << 16) |
699 int_addr_flag |
700 ((!use_alt_cmd && is_read) ? AT91_TWI_MREAD : 0));
701
702 dev->buf_len = m_start->len;
703 dev->buf = m_start->buf;
704 dev->msg = m_start;
705 dev->recv_len_abort = false;
706
707 ret = at91_do_twi_transfer(dev);
708
709 ret = (ret < 0) ? ret : num;
710out:
711 pm_runtime_mark_last_busy(dev->dev);
712 pm_runtime_put_autosuspend(dev->dev);
713
714 return ret;
715}
716
717
718
719
720
721static struct i2c_adapter_quirks at91_twi_quirks = {
722 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR,
723 .max_comb_1st_msg_len = 3,
724};
725
726static u32 at91_twi_func(struct i2c_adapter *adapter)
727{
728 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
729 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
730}
731
732static struct i2c_algorithm at91_twi_algorithm = {
733 .master_xfer = at91_twi_xfer,
734 .functionality = at91_twi_func,
735};
736
737static struct at91_twi_pdata at91rm9200_config = {
738 .clk_max_div = 5,
739 .clk_offset = 3,
740 .has_unre_flag = true,
741 .has_alt_cmd = false,
742};
743
744static struct at91_twi_pdata at91sam9261_config = {
745 .clk_max_div = 5,
746 .clk_offset = 4,
747 .has_unre_flag = false,
748 .has_alt_cmd = false,
749};
750
751static struct at91_twi_pdata at91sam9260_config = {
752 .clk_max_div = 7,
753 .clk_offset = 4,
754 .has_unre_flag = false,
755 .has_alt_cmd = false,
756};
757
758static struct at91_twi_pdata at91sam9g20_config = {
759 .clk_max_div = 7,
760 .clk_offset = 4,
761 .has_unre_flag = false,
762 .has_alt_cmd = false,
763};
764
765static struct at91_twi_pdata at91sam9g10_config = {
766 .clk_max_div = 7,
767 .clk_offset = 4,
768 .has_unre_flag = false,
769 .has_alt_cmd = false,
770};
771
772static const struct platform_device_id at91_twi_devtypes[] = {
773 {
774 .name = "i2c-at91rm9200",
775 .driver_data = (unsigned long) &at91rm9200_config,
776 }, {
777 .name = "i2c-at91sam9261",
778 .driver_data = (unsigned long) &at91sam9261_config,
779 }, {
780 .name = "i2c-at91sam9260",
781 .driver_data = (unsigned long) &at91sam9260_config,
782 }, {
783 .name = "i2c-at91sam9g20",
784 .driver_data = (unsigned long) &at91sam9g20_config,
785 }, {
786 .name = "i2c-at91sam9g10",
787 .driver_data = (unsigned long) &at91sam9g10_config,
788 }, {
789
790 }
791};
792
793#if defined(CONFIG_OF)
794static struct at91_twi_pdata at91sam9x5_config = {
795 .clk_max_div = 7,
796 .clk_offset = 4,
797 .has_unre_flag = false,
798 .has_alt_cmd = false,
799};
800
801static struct at91_twi_pdata sama5d2_config = {
802 .clk_max_div = 7,
803 .clk_offset = 4,
804 .has_unre_flag = true,
805 .has_alt_cmd = true,
806};
807
808static const struct of_device_id atmel_twi_dt_ids[] = {
809 {
810 .compatible = "atmel,at91rm9200-i2c",
811 .data = &at91rm9200_config,
812 } , {
813 .compatible = "atmel,at91sam9260-i2c",
814 .data = &at91sam9260_config,
815 } , {
816 .compatible = "atmel,at91sam9261-i2c",
817 .data = &at91sam9261_config,
818 } , {
819 .compatible = "atmel,at91sam9g20-i2c",
820 .data = &at91sam9g20_config,
821 } , {
822 .compatible = "atmel,at91sam9g10-i2c",
823 .data = &at91sam9g10_config,
824 }, {
825 .compatible = "atmel,at91sam9x5-i2c",
826 .data = &at91sam9x5_config,
827 }, {
828 .compatible = "atmel,sama5d2-i2c",
829 .data = &sama5d2_config,
830 }, {
831
832 }
833};
834MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
835#endif
836
837static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
838{
839 int ret = 0;
840 struct dma_slave_config slave_config;
841 struct at91_twi_dma *dma = &dev->dma;
842 enum dma_slave_buswidth addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859 if (dev->fifo_size)
860 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
861
862 memset(&slave_config, 0, sizeof(slave_config));
863 slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
864 slave_config.src_addr_width = addr_width;
865 slave_config.src_maxburst = 1;
866 slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
867 slave_config.dst_addr_width = addr_width;
868 slave_config.dst_maxburst = 1;
869 slave_config.device_fc = false;
870
871 dma->chan_tx = dma_request_slave_channel_reason(dev->dev, "tx");
872 if (IS_ERR(dma->chan_tx)) {
873 ret = PTR_ERR(dma->chan_tx);
874 dma->chan_tx = NULL;
875 goto error;
876 }
877
878 dma->chan_rx = dma_request_slave_channel_reason(dev->dev, "rx");
879 if (IS_ERR(dma->chan_rx)) {
880 ret = PTR_ERR(dma->chan_rx);
881 dma->chan_rx = NULL;
882 goto error;
883 }
884
885 slave_config.direction = DMA_MEM_TO_DEV;
886 if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
887 dev_err(dev->dev, "failed to configure tx channel\n");
888 ret = -EINVAL;
889 goto error;
890 }
891
892 slave_config.direction = DMA_DEV_TO_MEM;
893 if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
894 dev_err(dev->dev, "failed to configure rx channel\n");
895 ret = -EINVAL;
896 goto error;
897 }
898
899 sg_init_table(dma->sg, 2);
900 dma->buf_mapped = false;
901 dma->xfer_in_progress = false;
902 dev->use_dma = true;
903
904 dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
905 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
906
907 return ret;
908
909error:
910 if (ret != -EPROBE_DEFER)
911 dev_info(dev->dev, "can't use DMA, error %d\n", ret);
912 if (dma->chan_rx)
913 dma_release_channel(dma->chan_rx);
914 if (dma->chan_tx)
915 dma_release_channel(dma->chan_tx);
916 return ret;
917}
918
919static struct at91_twi_pdata *at91_twi_get_driver_data(
920 struct platform_device *pdev)
921{
922 if (pdev->dev.of_node) {
923 const struct of_device_id *match;
924 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
925 if (!match)
926 return NULL;
927 return (struct at91_twi_pdata *)match->data;
928 }
929 return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
930}
931
932static int at91_twi_probe(struct platform_device *pdev)
933{
934 struct at91_twi_dev *dev;
935 struct resource *mem;
936 int rc;
937 u32 phy_addr;
938 u32 bus_clk_rate;
939
940 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
941 if (!dev)
942 return -ENOMEM;
943 init_completion(&dev->cmd_complete);
944 dev->dev = &pdev->dev;
945
946 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
947 if (!mem)
948 return -ENODEV;
949 phy_addr = mem->start;
950
951 dev->pdata = at91_twi_get_driver_data(pdev);
952 if (!dev->pdata)
953 return -ENODEV;
954
955 dev->base = devm_ioremap_resource(&pdev->dev, mem);
956 if (IS_ERR(dev->base))
957 return PTR_ERR(dev->base);
958
959 dev->irq = platform_get_irq(pdev, 0);
960 if (dev->irq < 0)
961 return dev->irq;
962
963 rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
964 dev_name(dev->dev), dev);
965 if (rc) {
966 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
967 return rc;
968 }
969
970 platform_set_drvdata(pdev, dev);
971
972 dev->clk = devm_clk_get(dev->dev, NULL);
973 if (IS_ERR(dev->clk)) {
974 dev_err(dev->dev, "no clock defined\n");
975 return -ENODEV;
976 }
977 clk_prepare_enable(dev->clk);
978
979 if (dev->dev->of_node) {
980 rc = at91_twi_configure_dma(dev, phy_addr);
981 if (rc == -EPROBE_DEFER)
982 return rc;
983 }
984
985 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
986 &dev->fifo_size)) {
987 dev_info(dev->dev, "Using FIFO (%u data)\n", dev->fifo_size);
988 }
989
990 rc = of_property_read_u32(dev->dev->of_node, "clock-frequency",
991 &bus_clk_rate);
992 if (rc)
993 bus_clk_rate = DEFAULT_TWI_CLK_HZ;
994
995 at91_calc_twi_clock(dev, bus_clk_rate);
996 at91_init_twi_bus(dev);
997
998 snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
999 i2c_set_adapdata(&dev->adapter, dev);
1000 dev->adapter.owner = THIS_MODULE;
1001 dev->adapter.class = I2C_CLASS_DEPRECATED;
1002 dev->adapter.algo = &at91_twi_algorithm;
1003 dev->adapter.quirks = &at91_twi_quirks;
1004 dev->adapter.dev.parent = dev->dev;
1005 dev->adapter.nr = pdev->id;
1006 dev->adapter.timeout = AT91_I2C_TIMEOUT;
1007 dev->adapter.dev.of_node = pdev->dev.of_node;
1008
1009 pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT);
1010 pm_runtime_use_autosuspend(dev->dev);
1011 pm_runtime_set_active(dev->dev);
1012 pm_runtime_enable(dev->dev);
1013
1014 rc = i2c_add_numbered_adapter(&dev->adapter);
1015 if (rc) {
1016 dev_err(dev->dev, "Adapter %s registration failed\n",
1017 dev->adapter.name);
1018 clk_disable_unprepare(dev->clk);
1019
1020 pm_runtime_disable(dev->dev);
1021 pm_runtime_set_suspended(dev->dev);
1022
1023 return rc;
1024 }
1025
1026 dev_info(dev->dev, "AT91 i2c bus driver (hw version: %#x).\n",
1027 at91_twi_read(dev, AT91_TWI_VER));
1028 return 0;
1029}
1030
1031static int at91_twi_remove(struct platform_device *pdev)
1032{
1033 struct at91_twi_dev *dev = platform_get_drvdata(pdev);
1034
1035 i2c_del_adapter(&dev->adapter);
1036 clk_disable_unprepare(dev->clk);
1037
1038 pm_runtime_disable(dev->dev);
1039 pm_runtime_set_suspended(dev->dev);
1040
1041 return 0;
1042}
1043
1044#ifdef CONFIG_PM
1045
1046static int at91_twi_runtime_suspend(struct device *dev)
1047{
1048 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1049
1050 clk_disable_unprepare(twi_dev->clk);
1051
1052 pinctrl_pm_select_sleep_state(dev);
1053
1054 return 0;
1055}
1056
1057static int at91_twi_runtime_resume(struct device *dev)
1058{
1059 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1060
1061 pinctrl_pm_select_default_state(dev);
1062
1063 return clk_prepare_enable(twi_dev->clk);
1064}
1065
1066static int at91_twi_suspend_noirq(struct device *dev)
1067{
1068 if (!pm_runtime_status_suspended(dev))
1069 at91_twi_runtime_suspend(dev);
1070
1071 return 0;
1072}
1073
1074static int at91_twi_resume_noirq(struct device *dev)
1075{
1076 int ret;
1077
1078 if (!pm_runtime_status_suspended(dev)) {
1079 ret = at91_twi_runtime_resume(dev);
1080 if (ret)
1081 return ret;
1082 }
1083
1084 pm_runtime_mark_last_busy(dev);
1085 pm_request_autosuspend(dev);
1086
1087 return 0;
1088}
1089
1090static const struct dev_pm_ops at91_twi_pm = {
1091 .suspend_noirq = at91_twi_suspend_noirq,
1092 .resume_noirq = at91_twi_resume_noirq,
1093 .runtime_suspend = at91_twi_runtime_suspend,
1094 .runtime_resume = at91_twi_runtime_resume,
1095};
1096
1097#define at91_twi_pm_ops (&at91_twi_pm)
1098#else
1099#define at91_twi_pm_ops NULL
1100#endif
1101
1102static struct platform_driver at91_twi_driver = {
1103 .probe = at91_twi_probe,
1104 .remove = at91_twi_remove,
1105 .id_table = at91_twi_devtypes,
1106 .driver = {
1107 .name = "at91_i2c",
1108 .of_match_table = of_match_ptr(atmel_twi_dt_ids),
1109 .pm = at91_twi_pm_ops,
1110 },
1111};
1112
1113static int __init at91_twi_init(void)
1114{
1115 return platform_driver_register(&at91_twi_driver);
1116}
1117
1118static void __exit at91_twi_exit(void)
1119{
1120 platform_driver_unregister(&at91_twi_driver);
1121}
1122
1123subsys_initcall(at91_twi_init);
1124module_exit(at91_twi_exit);
1125
1126MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
1127MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
1128MODULE_LICENSE("GPL");
1129MODULE_ALIAS("platform:at91_i2c");
1130