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13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/i2c.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/of.h>
21
22
23#define CDNS_I2C_CR_OFFSET 0x00
24#define CDNS_I2C_SR_OFFSET 0x04
25#define CDNS_I2C_ADDR_OFFSET 0x08
26#define CDNS_I2C_DATA_OFFSET 0x0C
27#define CDNS_I2C_ISR_OFFSET 0x10
28#define CDNS_I2C_XFER_SIZE_OFFSET 0x14
29#define CDNS_I2C_TIME_OUT_OFFSET 0x1C
30#define CDNS_I2C_IER_OFFSET 0x24
31#define CDNS_I2C_IDR_OFFSET 0x28
32
33
34#define CDNS_I2C_CR_HOLD BIT(4)
35#define CDNS_I2C_CR_ACK_EN BIT(3)
36#define CDNS_I2C_CR_NEA BIT(2)
37#define CDNS_I2C_CR_MS BIT(1)
38
39#define CDNS_I2C_CR_RW BIT(0)
40
41#define CDNS_I2C_CR_CLR_FIFO BIT(6)
42#define CDNS_I2C_CR_DIVA_SHIFT 14
43#define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT)
44#define CDNS_I2C_CR_DIVB_SHIFT 8
45#define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
46
47
48#define CDNS_I2C_SR_BA BIT(8)
49#define CDNS_I2C_SR_RXDV BIT(5)
50
51
52
53
54
55
56
57#define CDNS_I2C_ADDR_MASK 0x000003FF
58
59
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61
62
63
64#define CDNS_I2C_IXR_ARB_LOST BIT(9)
65#define CDNS_I2C_IXR_RX_UNF BIT(7)
66#define CDNS_I2C_IXR_TX_OVF BIT(6)
67#define CDNS_I2C_IXR_RX_OVF BIT(5)
68#define CDNS_I2C_IXR_SLV_RDY BIT(4)
69#define CDNS_I2C_IXR_TO BIT(3)
70#define CDNS_I2C_IXR_NACK BIT(2)
71#define CDNS_I2C_IXR_DATA BIT(1)
72#define CDNS_I2C_IXR_COMP BIT(0)
73
74#define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
75 CDNS_I2C_IXR_RX_UNF | \
76 CDNS_I2C_IXR_TX_OVF | \
77 CDNS_I2C_IXR_RX_OVF | \
78 CDNS_I2C_IXR_SLV_RDY | \
79 CDNS_I2C_IXR_TO | \
80 CDNS_I2C_IXR_NACK | \
81 CDNS_I2C_IXR_DATA | \
82 CDNS_I2C_IXR_COMP)
83
84#define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
85 CDNS_I2C_IXR_RX_UNF | \
86 CDNS_I2C_IXR_TX_OVF | \
87 CDNS_I2C_IXR_RX_OVF | \
88 CDNS_I2C_IXR_NACK)
89
90#define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
91 CDNS_I2C_IXR_RX_UNF | \
92 CDNS_I2C_IXR_TX_OVF | \
93 CDNS_I2C_IXR_RX_OVF | \
94 CDNS_I2C_IXR_NACK | \
95 CDNS_I2C_IXR_DATA | \
96 CDNS_I2C_IXR_COMP)
97
98#define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000)
99
100#define CDNS_I2C_FIFO_DEPTH 16
101
102#define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2)
103#define CDNS_I2C_MAX_TRANSFER_SIZE 255
104
105#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
106
107#define DRIVER_NAME "cdns-i2c"
108
109#define CDNS_I2C_SPEED_MAX 400000
110#define CDNS_I2C_SPEED_DEFAULT 100000
111
112#define CDNS_I2C_DIVA_MAX 4
113#define CDNS_I2C_DIVB_MAX 64
114
115#define CDNS_I2C_TIMEOUT_MAX 0xFF
116
117#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
118
119#define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
120#define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
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143struct cdns_i2c {
144 void __iomem *membase;
145 struct i2c_adapter adap;
146 struct i2c_msg *p_msg;
147 int err_status;
148 struct completion xfer_done;
149 unsigned char *p_send_buf;
150 unsigned char *p_recv_buf;
151 u8 suspended;
152 unsigned int send_count;
153 unsigned int recv_count;
154 unsigned int curr_recv_count;
155 int irq;
156 unsigned long input_clk;
157 unsigned int i2c_clk;
158 unsigned int bus_hold_flag;
159 struct clk *clk;
160 struct notifier_block clk_rate_change_nb;
161 u32 quirks;
162};
163
164struct cdns_platform_data {
165 u32 quirks;
166};
167
168#define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \
169 clk_rate_change_nb)
170
171
172
173
174
175
176
177static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
178{
179 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
180 if (reg & CDNS_I2C_CR_HOLD)
181 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
182}
183
184static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
185{
186 return (hold_wrkaround &&
187 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
188}
189
190
191
192
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194
195
196
197
198
199
200static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
201{
202 unsigned int isr_status, avail_bytes, updatetx;
203 unsigned int bytes_to_send;
204 bool hold_quirk;
205 struct cdns_i2c *id = ptr;
206
207 int done_flag = 0;
208 irqreturn_t status = IRQ_NONE;
209
210 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
211 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
212
213
214 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
215 done_flag = 1;
216 status = IRQ_HANDLED;
217 }
218
219
220
221
222
223 updatetx = 0;
224 if (id->recv_count > id->curr_recv_count)
225 updatetx = 1;
226
227 hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
228
229
230 if (id->p_recv_buf &&
231 ((isr_status & CDNS_I2C_IXR_COMP) ||
232 (isr_status & CDNS_I2C_IXR_DATA))) {
233
234 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
235 CDNS_I2C_SR_RXDV) {
236
237
238
239
240
241 if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) &&
242 !id->bus_hold_flag)
243 cdns_i2c_clear_bus_hold(id);
244
245 *(id->p_recv_buf)++ =
246 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
247 id->recv_count--;
248 id->curr_recv_count--;
249
250 if (cdns_is_holdquirk(id, hold_quirk))
251 break;
252 }
253
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257
258
259
260
261 if (cdns_is_holdquirk(id, hold_quirk)) {
262
263 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
264 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
265 ;
266
267
268
269
270
271 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) >
272 CDNS_I2C_TRANSFER_SIZE) {
273 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
274 CDNS_I2C_XFER_SIZE_OFFSET);
275 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
276 CDNS_I2C_FIFO_DEPTH;
277 } else {
278 cdns_i2c_writereg(id->recv_count -
279 CDNS_I2C_FIFO_DEPTH,
280 CDNS_I2C_XFER_SIZE_OFFSET);
281 id->curr_recv_count = id->recv_count;
282 }
283 } else if (id->recv_count && !hold_quirk &&
284 !id->curr_recv_count) {
285
286
287 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
288 CDNS_I2C_ADDR_OFFSET);
289
290 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
291 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
292 CDNS_I2C_XFER_SIZE_OFFSET);
293 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
294 } else {
295 cdns_i2c_writereg(id->recv_count,
296 CDNS_I2C_XFER_SIZE_OFFSET);
297 id->curr_recv_count = id->recv_count;
298 }
299 }
300
301
302 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
303 if (!id->bus_hold_flag)
304 cdns_i2c_clear_bus_hold(id);
305 done_flag = 1;
306 }
307
308 status = IRQ_HANDLED;
309 }
310
311
312 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
313
314
315
316
317 if (id->send_count) {
318 avail_bytes = CDNS_I2C_FIFO_DEPTH -
319 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
320 if (id->send_count > avail_bytes)
321 bytes_to_send = avail_bytes;
322 else
323 bytes_to_send = id->send_count;
324
325 while (bytes_to_send--) {
326 cdns_i2c_writereg(
327 (*(id->p_send_buf)++),
328 CDNS_I2C_DATA_OFFSET);
329 id->send_count--;
330 }
331 } else {
332
333
334
335
336
337 done_flag = 1;
338 }
339 if (!id->send_count && !id->bus_hold_flag)
340 cdns_i2c_clear_bus_hold(id);
341
342 status = IRQ_HANDLED;
343 }
344
345
346 id->err_status = isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
347 if (id->err_status)
348 status = IRQ_HANDLED;
349
350 if (done_flag)
351 complete(&id->xfer_done);
352
353 return status;
354}
355
356
357
358
359
360static void cdns_i2c_mrecv(struct cdns_i2c *id)
361{
362 unsigned int ctrl_reg;
363 unsigned int isr_status;
364
365 id->p_recv_buf = id->p_msg->buf;
366 id->recv_count = id->p_msg->len;
367
368
369 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
370 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
371
372 if (id->p_msg->flags & I2C_M_RECV_LEN)
373 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1;
374
375 id->curr_recv_count = id->recv_count;
376
377
378
379
380
381 if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
382 ctrl_reg |= CDNS_I2C_CR_HOLD;
383
384 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
385
386
387 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
388 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
389
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396 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
397 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
398 CDNS_I2C_XFER_SIZE_OFFSET);
399 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
400 } else {
401 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
402 }
403
404
405 if (!id->bus_hold_flag &&
406 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
407 (id->recv_count <= CDNS_I2C_FIFO_DEPTH))
408 cdns_i2c_clear_bus_hold(id);
409
410 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
411 CDNS_I2C_ADDR_OFFSET);
412 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
413}
414
415
416
417
418
419static void cdns_i2c_msend(struct cdns_i2c *id)
420{
421 unsigned int avail_bytes;
422 unsigned int bytes_to_send;
423 unsigned int ctrl_reg;
424 unsigned int isr_status;
425
426 id->p_recv_buf = NULL;
427 id->p_send_buf = id->p_msg->buf;
428 id->send_count = id->p_msg->len;
429
430
431 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
432 ctrl_reg &= ~CDNS_I2C_CR_RW;
433 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
434
435
436
437
438
439 if (id->send_count > CDNS_I2C_FIFO_DEPTH)
440 ctrl_reg |= CDNS_I2C_CR_HOLD;
441 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
442
443
444 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
445 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
446
447
448
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450
451
452 avail_bytes = CDNS_I2C_FIFO_DEPTH -
453 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
454
455 if (id->send_count > avail_bytes)
456 bytes_to_send = avail_bytes;
457 else
458 bytes_to_send = id->send_count;
459
460 while (bytes_to_send--) {
461 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
462 id->send_count--;
463 }
464
465
466
467
468
469 if (!id->bus_hold_flag && !id->send_count)
470 cdns_i2c_clear_bus_hold(id);
471
472 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
473 CDNS_I2C_ADDR_OFFSET);
474
475 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
476}
477
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483
484
485static void cdns_i2c_master_reset(struct i2c_adapter *adap)
486{
487 struct cdns_i2c *id = adap->algo_data;
488 u32 regval;
489
490
491 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
492
493 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
494 regval &= ~CDNS_I2C_CR_HOLD;
495 regval |= CDNS_I2C_CR_CLR_FIFO;
496 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
497
498 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
499
500 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
501 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
502
503 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
504 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
505}
506
507static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
508 struct i2c_adapter *adap)
509{
510 unsigned long time_left;
511 u32 reg;
512
513 id->p_msg = msg;
514 id->err_status = 0;
515 reinit_completion(&id->xfer_done);
516
517
518 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
519 if (msg->flags & I2C_M_TEN) {
520 if (reg & CDNS_I2C_CR_NEA)
521 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
522 CDNS_I2C_CR_OFFSET);
523 } else {
524 if (!(reg & CDNS_I2C_CR_NEA))
525 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
526 CDNS_I2C_CR_OFFSET);
527 }
528
529
530 if (msg->flags & I2C_M_RD)
531 cdns_i2c_mrecv(id);
532 else
533 cdns_i2c_msend(id);
534
535
536 time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout);
537 if (time_left == 0) {
538 cdns_i2c_master_reset(adap);
539 dev_err(id->adap.dev.parent,
540 "timeout waiting on completion\n");
541 return -ETIMEDOUT;
542 }
543
544 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
545 CDNS_I2C_IDR_OFFSET);
546
547
548 if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
549 return -EAGAIN;
550
551 return 0;
552}
553
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562
563
564static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
565 int num)
566{
567 int ret, count;
568 u32 reg;
569 struct cdns_i2c *id = adap->algo_data;
570 bool hold_quirk;
571
572
573 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA)
574 return -EAGAIN;
575
576 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
577
578
579
580
581 if (num > 1) {
582
583
584
585
586
587
588
589 for (count = 0; (count < num - 1 && hold_quirk); count++) {
590 if (msgs[count].flags & I2C_M_RD) {
591 dev_warn(adap->dev.parent,
592 "Can't do repeated start after a receive message\n");
593 return -EOPNOTSUPP;
594 }
595 }
596 id->bus_hold_flag = 1;
597 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
598 reg |= CDNS_I2C_CR_HOLD;
599 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
600 } else {
601 id->bus_hold_flag = 0;
602 }
603
604
605 for (count = 0; count < num; count++, msgs++) {
606 if (count == (num - 1))
607 id->bus_hold_flag = 0;
608
609 ret = cdns_i2c_process_msg(id, msgs, adap);
610 if (ret)
611 return ret;
612
613
614 if (id->err_status) {
615 cdns_i2c_master_reset(adap);
616
617 if (id->err_status & CDNS_I2C_IXR_NACK)
618 return -ENXIO;
619
620 return -EIO;
621 }
622 }
623
624 return num;
625}
626
627
628
629
630
631
632
633static u32 cdns_i2c_func(struct i2c_adapter *adap)
634{
635 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
636 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
637 I2C_FUNC_SMBUS_BLOCK_DATA;
638}
639
640static const struct i2c_algorithm cdns_i2c_algo = {
641 .master_xfer = cdns_i2c_master_xfer,
642 .functionality = cdns_i2c_func,
643};
644
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655
656
657static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
658 unsigned int *a, unsigned int *b)
659{
660 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
661 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
662 unsigned int last_error, current_error;
663
664
665 temp = input_clk / (22 * fscl);
666
667
668
669
670
671 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
672 return -EINVAL;
673
674 last_error = -1;
675 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
676 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
677
678 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
679 continue;
680 div_b--;
681
682 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
683
684 if (actual_fscl > fscl)
685 continue;
686
687 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
688 (fscl - actual_fscl));
689
690 if (last_error > current_error) {
691 calc_div_a = div_a;
692 calc_div_b = div_b;
693 best_fscl = actual_fscl;
694 last_error = current_error;
695 }
696 }
697
698 *a = calc_div_a;
699 *b = calc_div_b;
700 *f = best_fscl;
701
702 return 0;
703}
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719
720
721static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
722{
723 unsigned int div_a, div_b;
724 unsigned int ctrl_reg;
725 int ret = 0;
726 unsigned long fscl = id->i2c_clk;
727
728 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
729 if (ret)
730 return ret;
731
732 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
733 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
734 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
735 (div_b << CDNS_I2C_CR_DIVB_SHIFT));
736 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
737
738 return 0;
739}
740
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749
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755
756
757static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
758 event, void *data)
759{
760 struct clk_notifier_data *ndata = data;
761 struct cdns_i2c *id = to_cdns_i2c(nb);
762
763 if (id->suspended)
764 return NOTIFY_OK;
765
766 switch (event) {
767 case PRE_RATE_CHANGE:
768 {
769 unsigned long input_clk = ndata->new_rate;
770 unsigned long fscl = id->i2c_clk;
771 unsigned int div_a, div_b;
772 int ret;
773
774 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
775 if (ret) {
776 dev_warn(id->adap.dev.parent,
777 "clock rate change rejected\n");
778 return NOTIFY_STOP;
779 }
780
781
782 if (ndata->new_rate > ndata->old_rate)
783 cdns_i2c_setclk(ndata->new_rate, id);
784
785 return NOTIFY_OK;
786 }
787 case POST_RATE_CHANGE:
788 id->input_clk = ndata->new_rate;
789
790 if (ndata->new_rate < ndata->old_rate)
791 cdns_i2c_setclk(ndata->new_rate, id);
792 return NOTIFY_OK;
793 case ABORT_RATE_CHANGE:
794
795 if (ndata->new_rate > ndata->old_rate)
796 cdns_i2c_setclk(ndata->old_rate, id);
797 return NOTIFY_OK;
798 default:
799 return NOTIFY_DONE;
800 }
801}
802
803
804
805
806
807
808
809
810
811static int __maybe_unused cdns_i2c_suspend(struct device *_dev)
812{
813 struct platform_device *pdev = container_of(_dev,
814 struct platform_device, dev);
815 struct cdns_i2c *xi2c = platform_get_drvdata(pdev);
816
817 clk_disable(xi2c->clk);
818 xi2c->suspended = 1;
819
820 return 0;
821}
822
823
824
825
826
827
828
829
830
831static int __maybe_unused cdns_i2c_resume(struct device *_dev)
832{
833 struct platform_device *pdev = container_of(_dev,
834 struct platform_device, dev);
835 struct cdns_i2c *xi2c = platform_get_drvdata(pdev);
836 int ret;
837
838 ret = clk_enable(xi2c->clk);
839 if (ret) {
840 dev_err(_dev, "Cannot enable clock.\n");
841 return ret;
842 }
843
844 xi2c->suspended = 0;
845
846 return 0;
847}
848
849static SIMPLE_DEV_PM_OPS(cdns_i2c_dev_pm_ops, cdns_i2c_suspend,
850 cdns_i2c_resume);
851
852static const struct cdns_platform_data r1p10_i2c_def = {
853 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
854};
855
856static const struct of_device_id cdns_i2c_of_match[] = {
857 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
858 { .compatible = "cdns,i2c-r1p14",},
859 { }
860};
861MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
862
863
864
865
866
867
868
869
870
871
872
873static int cdns_i2c_probe(struct platform_device *pdev)
874{
875 struct resource *r_mem;
876 struct cdns_i2c *id;
877 int ret;
878 const struct of_device_id *match;
879
880 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
881 if (!id)
882 return -ENOMEM;
883
884 platform_set_drvdata(pdev, id);
885
886 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
887 if (match && match->data) {
888 const struct cdns_platform_data *data = match->data;
889 id->quirks = data->quirks;
890 }
891
892 r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
893 id->membase = devm_ioremap_resource(&pdev->dev, r_mem);
894 if (IS_ERR(id->membase))
895 return PTR_ERR(id->membase);
896
897 id->irq = platform_get_irq(pdev, 0);
898
899 id->adap.owner = THIS_MODULE;
900 id->adap.dev.of_node = pdev->dev.of_node;
901 id->adap.algo = &cdns_i2c_algo;
902 id->adap.timeout = CDNS_I2C_TIMEOUT;
903 id->adap.retries = 3;
904 id->adap.algo_data = id;
905 id->adap.dev.parent = &pdev->dev;
906 init_completion(&id->xfer_done);
907 snprintf(id->adap.name, sizeof(id->adap.name),
908 "Cadence I2C at %08lx", (unsigned long)r_mem->start);
909
910 id->clk = devm_clk_get(&pdev->dev, NULL);
911 if (IS_ERR(id->clk)) {
912 dev_err(&pdev->dev, "input clock not found.\n");
913 return PTR_ERR(id->clk);
914 }
915 ret = clk_prepare_enable(id->clk);
916 if (ret) {
917 dev_err(&pdev->dev, "Unable to enable clock.\n");
918 return ret;
919 }
920 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
921 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
922 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
923 id->input_clk = clk_get_rate(id->clk);
924
925 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
926 &id->i2c_clk);
927 if (ret || (id->i2c_clk > CDNS_I2C_SPEED_MAX))
928 id->i2c_clk = CDNS_I2C_SPEED_DEFAULT;
929
930 cdns_i2c_writereg(CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS,
931 CDNS_I2C_CR_OFFSET);
932
933 ret = cdns_i2c_setclk(id->input_clk, id);
934 if (ret) {
935 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
936 ret = -EINVAL;
937 goto err_clk_dis;
938 }
939
940 ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
941 DRIVER_NAME, id);
942 if (ret) {
943 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
944 goto err_clk_dis;
945 }
946
947 ret = i2c_add_adapter(&id->adap);
948 if (ret < 0) {
949 dev_err(&pdev->dev, "reg adap failed: %d\n", ret);
950 goto err_clk_dis;
951 }
952
953
954
955
956
957
958
959
960 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
961
962 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
963 id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
964
965 return 0;
966
967err_clk_dis:
968 clk_disable_unprepare(id->clk);
969 return ret;
970}
971
972
973
974
975
976
977
978
979
980static int cdns_i2c_remove(struct platform_device *pdev)
981{
982 struct cdns_i2c *id = platform_get_drvdata(pdev);
983
984 i2c_del_adapter(&id->adap);
985 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
986 clk_disable_unprepare(id->clk);
987
988 return 0;
989}
990
991static struct platform_driver cdns_i2c_drv = {
992 .driver = {
993 .name = DRIVER_NAME,
994 .of_match_table = cdns_i2c_of_match,
995 .pm = &cdns_i2c_dev_pm_ops,
996 },
997 .probe = cdns_i2c_probe,
998 .remove = cdns_i2c_remove,
999};
1000
1001module_platform_driver(cdns_i2c_drv);
1002
1003MODULE_AUTHOR("Xilinx Inc.");
1004MODULE_DESCRIPTION("Cadence I2C bus driver");
1005MODULE_LICENSE("GPL");
1006