LXR linux/drivers/i2c/busses/i2c-davinci.c

   1/*
   2 * TI DAVINCI I2C adapter driver.
   3 *
   4 * Copyright (C) 2006 Texas Instruments.
   5 * Copyright (C) 2007 MontaVista Software Inc.
   6 *
   7 * Updated by Vinod & Sudhakar Feb 2005
   8 *
   9 * ----------------------------------------------------------------------------
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2 of the License, or
  14 * (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 * ----------------------------------------------------------------------------
  21 *
  22 */
  23#include <linux/kernel.h>
  24#include <linux/module.h>
  25#include <linux/delay.h>
  26#include <linux/i2c.h>
  27#include <linux/clk.h>
  28#include <linux/errno.h>
  29#include <linux/sched.h>
  30#include <linux/err.h>
  31#include <linux/interrupt.h>
  32#include <linux/platform_device.h>
  33#include <linux/io.h>
  34#include <linux/slab.h>
  35#include <linux/cpufreq.h>
  36#include <linux/gpio.h>
  37#include <linux/of_device.h>
  38#include <linux/platform_data/i2c-davinci.h>
  39
  40/* ----- global defines ----------------------------------------------- */
  41
  42#define DAVINCI_I2C_TIMEOUT     (1*HZ)
  43#define DAVINCI_I2C_MAX_TRIES   2
  44#define DAVINCI_I2C_OWN_ADDRESS 0x08
  45#define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_SCD | \
  46                                 DAVINCI_I2C_IMR_ARDY | \
  47                                 DAVINCI_I2C_IMR_NACK | \
  48                                 DAVINCI_I2C_IMR_AL)
  49
  50#define DAVINCI_I2C_OAR_REG     0x00
  51#define DAVINCI_I2C_IMR_REG     0x04
  52#define DAVINCI_I2C_STR_REG     0x08
  53#define DAVINCI_I2C_CLKL_REG    0x0c
  54#define DAVINCI_I2C_CLKH_REG    0x10
  55#define DAVINCI_I2C_CNT_REG     0x14
  56#define DAVINCI_I2C_DRR_REG     0x18
  57#define DAVINCI_I2C_SAR_REG     0x1c
  58#define DAVINCI_I2C_DXR_REG     0x20
  59#define DAVINCI_I2C_MDR_REG     0x24
  60#define DAVINCI_I2C_IVR_REG     0x28
  61#define DAVINCI_I2C_EMDR_REG    0x2c
  62#define DAVINCI_I2C_PSC_REG     0x30
  63#define DAVINCI_I2C_FUNC_REG    0x48
  64#define DAVINCI_I2C_DIR_REG     0x4c
  65#define DAVINCI_I2C_DIN_REG     0x50
  66#define DAVINCI_I2C_DOUT_REG    0x54
  67#define DAVINCI_I2C_DSET_REG    0x58
  68#define DAVINCI_I2C_DCLR_REG    0x5c
  69
  70#define DAVINCI_I2C_IVR_AAS     0x07
  71#define DAVINCI_I2C_IVR_SCD     0x06
  72#define DAVINCI_I2C_IVR_XRDY    0x05
  73#define DAVINCI_I2C_IVR_RDR     0x04
  74#define DAVINCI_I2C_IVR_ARDY    0x03
  75#define DAVINCI_I2C_IVR_NACK    0x02
  76#define DAVINCI_I2C_IVR_AL      0x01
  77
  78#define DAVINCI_I2C_STR_BB      BIT(12)
  79#define DAVINCI_I2C_STR_RSFULL  BIT(11)
  80#define DAVINCI_I2C_STR_SCD     BIT(5)
  81#define DAVINCI_I2C_STR_ARDY    BIT(2)
  82#define DAVINCI_I2C_STR_NACK    BIT(1)
  83#define DAVINCI_I2C_STR_AL      BIT(0)
  84
  85#define DAVINCI_I2C_MDR_NACK    BIT(15)
  86#define DAVINCI_I2C_MDR_STT     BIT(13)
  87#define DAVINCI_I2C_MDR_STP     BIT(11)
  88#define DAVINCI_I2C_MDR_MST     BIT(10)
  89#define DAVINCI_I2C_MDR_TRX     BIT(9)
  90#define DAVINCI_I2C_MDR_XA      BIT(8)
  91#define DAVINCI_I2C_MDR_RM      BIT(7)
  92#define DAVINCI_I2C_MDR_IRS     BIT(5)
  93
  94#define DAVINCI_I2C_IMR_AAS     BIT(6)
  95#define DAVINCI_I2C_IMR_SCD     BIT(5)
  96#define DAVINCI_I2C_IMR_XRDY    BIT(4)
  97#define DAVINCI_I2C_IMR_RRDY    BIT(3)
  98#define DAVINCI_I2C_IMR_ARDY    BIT(2)
  99#define DAVINCI_I2C_IMR_NACK    BIT(1)
 100#define DAVINCI_I2C_IMR_AL      BIT(0)
 101
 102/* set SDA and SCL as GPIO */
 103#define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
 104
 105/* set SCL as output when used as GPIO*/
 106#define DAVINCI_I2C_DIR_PDIR0   BIT(0)
 107/* set SDA as output when used as GPIO*/
 108#define DAVINCI_I2C_DIR_PDIR1   BIT(1)
 109
 110/* read SCL GPIO level */
 111#define DAVINCI_I2C_DIN_PDIN0 BIT(0)
 112/* read SDA GPIO level */
 113#define DAVINCI_I2C_DIN_PDIN1 BIT(1)
 114
 115/*set the SCL GPIO high */
 116#define DAVINCI_I2C_DSET_PDSET0 BIT(0)
 117/*set the SDA GPIO high */
 118#define DAVINCI_I2C_DSET_PDSET1 BIT(1)
 119
 120/* set the SCL GPIO low */
 121#define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
 122/* set the SDA GPIO low */
 123#define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
 124
 125struct davinci_i2c_dev {
 126        struct device           *dev;
 127        void __iomem            *base;
 128        struct completion       cmd_complete;
 129        struct clk              *clk;
 130        int                     cmd_err;
 131        u8                      *buf;
 132        size_t                  buf_len;
 133        int                     irq;
 134        int                     stop;
 135        u8                      terminate;
 136        struct i2c_adapter      adapter;
 137#ifdef CONFIG_CPU_FREQ
 138        struct completion       xfr_complete;
 139        struct notifier_block   freq_transition;
 140#endif
 141        struct davinci_i2c_platform_data *pdata;
 142};
 143
 144/* default platform data to use if not supplied in the platform_device */
 145static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
 146        .bus_freq       = 100,
 147        .bus_delay      = 0,
 148};
 149
 150static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
 151                                         int reg, u16 val)
 152{
 153        writew_relaxed(val, i2c_dev->base + reg);
 154}
 155
 156static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
 157{
 158        return readw_relaxed(i2c_dev->base + reg);
 159}
 160
 161static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
 162                                                                int val)
 163{
 164        u16 w;
 165
 166        w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
 167        if (!val)       /* put I2C into reset */
 168                w &= ~DAVINCI_I2C_MDR_IRS;
 169        else            /* take I2C out of reset */
 170                w |= DAVINCI_I2C_MDR_IRS;
 171
 172        davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
 173}
 174
 175static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
 176{
 177        struct davinci_i2c_platform_data *pdata = dev->pdata;
 178        u16 psc;
 179        u32 clk;
 180        u32 d;
 181        u32 clkh;
 182        u32 clkl;
 183        u32 input_clock = clk_get_rate(dev->clk);
 184
 185        /* NOTE: I2C Clock divider programming info
 186         * As per I2C specs the following formulas provide prescaler
 187         * and low/high divider values
 188         * input clk --> PSC Div -----------> ICCL/H Div --> output clock
 189         *                       module clk
 190         *
 191         * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
 192         *
 193         * Thus,
 194         * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
 195         *
 196         * where if PSC == 0, d = 7,
 197         *       if PSC == 1, d = 6
 198         *       if PSC > 1 , d = 5
 199         */
 200
 201        /* get minimum of 7 MHz clock, but max of 12 MHz */
 202        psc = (input_clock / 7000000) - 1;
 203        if ((input_clock / (psc + 1)) > 12000000)
 204                psc++;  /* better to run under spec than over */
 205        d = (psc >= 2) ? 5 : 7 - psc;
 206
 207        clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
 208        /* Avoid driving the bus too fast because of rounding errors above */
 209        if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
 210                clk++;
 211        /*
 212         * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at
 213         * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH
 214         * to LOW ratio as 1 to 2 is more safe.
 215         */
 216        if (pdata->bus_freq > 100)
 217                clkl = (clk << 1) / 3;
 218        else
 219                clkl = (clk >> 1);
 220        /*
 221         * It's not always possible to have 1 to 2 ratio when d=7, so fall back
 222         * to minimal possible clkh in this case.
 223         */
 224        if (clk >= clkl + d) {
 225                clkh = clk - clkl - d;
 226                clkl -= d;
 227        } else {
 228                clkh = 0;
 229                clkl = clk - (d << 1);
 230        }
 231
 232        davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
 233        davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
 234        davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
 235
 236        dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
 237}
 238
 239/*
 240 * This function configures I2C and brings I2C out of reset.
 241 * This function is called during I2C init function. This function
 242 * also gets called if I2C encounters any errors.
 243 */
 244static int i2c_davinci_init(struct davinci_i2c_dev *dev)
 245{
 246        struct davinci_i2c_platform_data *pdata = dev->pdata;
 247
 248        /* put I2C into reset */
 249        davinci_i2c_reset_ctrl(dev, 0);
 250
 251        /* compute clock dividers */
 252        i2c_davinci_calc_clk_dividers(dev);
 253
 254        /* Respond at reserved "SMBus Host" slave address" (and zero);
 255         * we seem to have no option to not respond...
 256         */
 257        davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
 258
 259        dev_dbg(dev->dev, "PSC  = %d\n",
 260                davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
 261        dev_dbg(dev->dev, "CLKL = %d\n",
 262                davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
 263        dev_dbg(dev->dev, "CLKH = %d\n",
 264                davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
 265        dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
 266                pdata->bus_freq, pdata->bus_delay);
 267
 268
 269        /* Take the I2C module out of reset: */
 270        davinci_i2c_reset_ctrl(dev, 1);
 271
 272        /* Enable interrupts */
 273        davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
 274
 275        return 0;
 276}
 277
 278/*
 279 * This routine does i2c bus recovery by using i2c_generic_gpio_recovery
 280 * which is provided by I2C Bus recovery infrastructure.
 281 */
 282static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
 283{
 284        struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 285
 286        /* Disable interrupts */
 287        davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
 288
 289        /* put I2C into reset */
 290        davinci_i2c_reset_ctrl(dev, 0);
 291}
 292
 293static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
 294{
 295        struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 296
 297        i2c_davinci_init(dev);
 298}
 299
 300static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
 301        .recover_bus = i2c_generic_gpio_recovery,
 302        .prepare_recovery = davinci_i2c_prepare_recovery,
 303        .unprepare_recovery = davinci_i2c_unprepare_recovery,
 304};
 305
 306static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
 307{
 308        struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 309
 310        if (val)
 311                davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
 312                                      DAVINCI_I2C_DSET_PDSET0);
 313        else
 314                davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
 315                                      DAVINCI_I2C_DCLR_PDCLR0);
 316}
 317
 318static int davinci_i2c_get_scl(struct i2c_adapter *adap)
 319{
 320        struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 321        int val;
 322
 323        /* read the state of SCL */
 324        val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
 325        return val & DAVINCI_I2C_DIN_PDIN0;
 326}
 327
 328static int davinci_i2c_get_sda(struct i2c_adapter *adap)
 329{
 330        struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 331        int val;
 332
 333        /* read the state of SDA */
 334        val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
 335        return val & DAVINCI_I2C_DIN_PDIN1;
 336}
 337
 338static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
 339{
 340        struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 341
 342        davinci_i2c_prepare_recovery(adap);
 343
 344        /* SCL output, SDA input */
 345        davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
 346
 347        /* change to GPIO mode */
 348        davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
 349                              DAVINCI_I2C_FUNC_PFUNC0);
 350}
 351
 352static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
 353{
 354        struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 355
 356        /* change back to I2C mode */
 357        davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
 358
 359        davinci_i2c_unprepare_recovery(adap);
 360}
 361
 362static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
 363        .recover_bus = i2c_generic_scl_recovery,
 364        .set_scl = davinci_i2c_set_scl,
 365        .get_scl = davinci_i2c_get_scl,
 366        .get_sda = davinci_i2c_get_sda,
 367        .prepare_recovery = davinci_i2c_scl_prepare_recovery,
 368        .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
 369};
 370
 371/*
 372 * Waiting for bus not busy
 373 */
 374static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
 375{
 376        unsigned long timeout = jiffies + dev->adapter.timeout;
 377
 378        do {
 379                if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
 380                        return 0;
 381                schedule_timeout_uninterruptible(1);
 382        } while (time_before_eq(jiffies, timeout));
 383
 384        dev_warn(dev->dev, "timeout waiting for bus ready\n");
 385        i2c_recover_bus(&dev->adapter);
 386
 387        /*
 388         * if bus is still "busy" here, it's most probably a HW problem like
 389         * short-circuit
 390         */
 391        if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
 392                return -EIO;
 393
 394        return 0;
 395}
 396
 397/*
 398 * Low level master read/write transaction. This function is called
 399 * from i2c_davinci_xfer.
 400 */
 401static int
 402i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
 403{
 404        struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 405        struct davinci_i2c_platform_data *pdata = dev->pdata;
 406        u32 flag;
 407        u16 w;
 408        unsigned long time_left;
 409
 410        if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
 411                dev_warn(dev->dev, "transfer to own address aborted\n");
 412                return -EADDRNOTAVAIL;
 413        }
 414
 415        /* Introduce a delay, required for some boards (e.g Davinci EVM) */
 416        if (pdata->bus_delay)
 417                udelay(pdata->bus_delay);
 418
 419        /* set the slave address */
 420        davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
 421
 422        dev->buf = msg->buf;
 423        dev->buf_len = msg->len;
 424        dev->stop = stop;
 425
 426        davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
 427
 428        reinit_completion(&dev->cmd_complete);
 429        dev->cmd_err = 0;
 430
 431        /* Take I2C out of reset and configure it as master */
 432        flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
 433
 434        /* if the slave address is ten bit address, enable XA bit */
 435        if (msg->flags & I2C_M_TEN)
 436                flag |= DAVINCI_I2C_MDR_XA;
 437        if (!(msg->flags & I2C_M_RD))
 438                flag |= DAVINCI_I2C_MDR_TRX;
 439        if (msg->len == 0)
 440                flag |= DAVINCI_I2C_MDR_RM;
 441
 442        /* Enable receive or transmit interrupts */
 443        w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
 444        if (msg->flags & I2C_M_RD)
 445                w |= DAVINCI_I2C_IMR_RRDY;
 446        else
 447                w |= DAVINCI_I2C_IMR_XRDY;
 448        davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
 449
 450        dev->terminate = 0;
 451
 452        /*
 453         * Write mode register first as needed for correct behaviour
 454         * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
 455         * occurring before we have loaded DXR
 456         */
 457        davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 458
 459        /*
 460         * First byte should be set here, not after interrupt,
 461         * because transmit-data-ready interrupt can come before
 462         * NACK-interrupt during sending of previous message and
 463         * ICDXR may have wrong data
 464         * It also saves us one interrupt, slightly faster
 465         */
 466        if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
 467                davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
 468                dev->buf_len--;
 469        }
 470
 471        /* Set STT to begin transmit now DXR is loaded */
 472        flag |= DAVINCI_I2C_MDR_STT;
 473        if (stop && msg->len != 0)
 474                flag |= DAVINCI_I2C_MDR_STP;
 475        davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 476
 477        time_left = wait_for_completion_timeout(&dev->cmd_complete,
 478                                                dev->adapter.timeout);
 479        if (!time_left) {
 480                dev_err(dev->dev, "controller timed out\n");
 481                i2c_recover_bus(adap);
 482                dev->buf_len = 0;
 483                return -ETIMEDOUT;
 484        }
 485        if (dev->buf_len) {
 486                /* This should be 0 if all bytes were transferred
 487                 * or dev->cmd_err denotes an error.
 488                 */
 489                dev_err(dev->dev, "abnormal termination buf_len=%i\n",
 490                        dev->buf_len);
 491                dev->terminate = 1;
 492                wmb();
 493                dev->buf_len = 0;
 494                return -EREMOTEIO;
 495        }
 496
 497        /* no error */
 498        if (likely(!dev->cmd_err))
 499                return msg->len;
 500
 501        /* We have an error */
 502        if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
 503                i2c_davinci_init(dev);
 504                return -EIO;
 505        }
 506
 507        if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
 508                if (msg->flags & I2C_M_IGNORE_NAK)
 509                        return msg->len;
 510                w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 511                w |= DAVINCI_I2C_MDR_STP;
 512                davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 513                return -EREMOTEIO;
 514        }
 515        return -EIO;
 516}
 517
 518/*
 519 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
 520 */
 521static int
 522i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 523{
 524        struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 525        int i;
 526        int ret;
 527
 528        dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 529
 530        ret = i2c_davinci_wait_bus_not_busy(dev);
 531        if (ret < 0) {
 532                dev_warn(dev->dev, "timeout waiting for bus ready\n");
 533                return ret;
 534        }
 535
 536        for (i = 0; i < num; i++) {
 537                ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 538                dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
 539                        ret);
 540                if (ret < 0)
 541                        return ret;
 542        }
 543
 544#ifdef CONFIG_CPU_FREQ
 545        complete(&dev->xfr_complete);
 546#endif
 547
 548        return num;
 549}
 550
 551static u32 i2c_davinci_func(struct i2c_adapter *adap)
 552{
 553        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 554}
 555
 556static void terminate_read(struct davinci_i2c_dev *dev)
 557{
 558        u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 559        w |= DAVINCI_I2C_MDR_NACK;
 560        davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 561
 562        /* Throw away data */
 563        davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
 564        if (!dev->terminate)
 565                dev_err(dev->dev, "RDR IRQ while no data requested\n");
 566}
 567static void terminate_write(struct davinci_i2c_dev *dev)
 568{
 569        u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 570        w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
 571        davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 572
 573        if (!dev->terminate)
 574                dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
 575}
 576
 577/*
 578 * Interrupt service routine. This gets called whenever an I2C interrupt
 579 * occurs.
 580 */
 581static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
 582{
 583        struct davinci_i2c_dev *dev = dev_id;
 584        u32 stat;
 585        int count = 0;
 586        u16 w;
 587
 588        while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
 589                dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
 590                if (count++ == 100) {
 591                        dev_warn(dev->dev, "Too much work in one IRQ\n");
 592                        break;
 593                }
 594
 595                switch (stat) {
 596                case DAVINCI_I2C_IVR_AL:
 597                        /* Arbitration lost, must retry */
 598                        dev->cmd_err |= DAVINCI_I2C_STR_AL;
 599                        dev->buf_len = 0;
 600                        complete(&dev->cmd_complete);
 601                        break;
 602
 603                case DAVINCI_I2C_IVR_NACK:
 604                        dev->cmd_err |= DAVINCI_I2C_STR_NACK;
 605                        dev->buf_len = 0;
 606                        complete(&dev->cmd_complete);
 607                        break;
 608
 609                case DAVINCI_I2C_IVR_ARDY:
 610                        davinci_i2c_write_reg(dev,
 611                                DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
 612                        if (((dev->buf_len == 0) && (dev->stop != 0)) ||
 613                            (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
 614                                w = davinci_i2c_read_reg(dev,
 615                                                         DAVINCI_I2C_MDR_REG);
 616                                w |= DAVINCI_I2C_MDR_STP;
 617                                davinci_i2c_write_reg(dev,
 618                                                      DAVINCI_I2C_MDR_REG, w);
 619                        }
 620                        complete(&dev->cmd_complete);
 621                        break;
 622
 623                case DAVINCI_I2C_IVR_RDR:
 624                        if (dev->buf_len) {
 625                                *dev->buf++ =
 626                                    davinci_i2c_read_reg(dev,
 627                                                         DAVINCI_I2C_DRR_REG);
 628                                dev->buf_len--;
 629                                if (dev->buf_len)
 630                                        continue;
 631
 632                                davinci_i2c_write_reg(dev,
 633                                        DAVINCI_I2C_STR_REG,
 634                                        DAVINCI_I2C_IMR_RRDY);
 635                        } else {
 636                                /* signal can terminate transfer */
 637                                terminate_read(dev);
 638                        }
 639                        break;
 640
 641                case DAVINCI_I2C_IVR_XRDY:
 642                        if (dev->buf_len) {
 643                                davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
 644                                                      *dev->buf++);
 645                                dev->buf_len--;
 646                                if (dev->buf_len)
 647                                        continue;
 648
 649                                w = davinci_i2c_read_reg(dev,
 650                                                         DAVINCI_I2C_IMR_REG);
 651                                w &= ~DAVINCI_I2C_IMR_XRDY;
 652                                davinci_i2c_write_reg(dev,
 653                                                      DAVINCI_I2C_IMR_REG,
 654                                                      w);
 655                        } else {
 656                                /* signal can terminate transfer */
 657                                terminate_write(dev);
 658                        }
 659                        break;
 660
 661                case DAVINCI_I2C_IVR_SCD:
 662                        davinci_i2c_write_reg(dev,
 663                                DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
 664                        complete(&dev->cmd_complete);
 665                        break;
 666
 667                case DAVINCI_I2C_IVR_AAS:
 668                        dev_dbg(dev->dev, "Address as slave interrupt\n");
 669                        break;
 670
 671                default:
 672                        dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
 673                        break;
 674                }
 675        }
 676
 677        return count ? IRQ_HANDLED : IRQ_NONE;
 678}
 679
 680#ifdef CONFIG_CPU_FREQ
 681static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
 682                                     unsigned long val, void *data)
 683{
 684        struct davinci_i2c_dev *dev;
 685
 686        dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
 687        if (val == CPUFREQ_PRECHANGE) {
 688                wait_for_completion(&dev->xfr_complete);
 689                davinci_i2c_reset_ctrl(dev, 0);
 690        } else if (val == CPUFREQ_POSTCHANGE) {
 691                i2c_davinci_calc_clk_dividers(dev);
 692                davinci_i2c_reset_ctrl(dev, 1);
 693        }
 694
 695        return 0;
 696}
 697
 698static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
 699{
 700        dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
 701
 702        return cpufreq_register_notifier(&dev->freq_transition,
 703                                         CPUFREQ_TRANSITION_NOTIFIER);
 704}
 705
 706static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
 707{
 708        cpufreq_unregister_notifier(&dev->freq_transition,
 709                                    CPUFREQ_TRANSITION_NOTIFIER);
 710}
 711#else
 712static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
 713{
 714        return 0;
 715}
 716
 717static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
 718{
 719}
 720#endif
 721
 722static struct i2c_algorithm i2c_davinci_algo = {
 723        .master_xfer    = i2c_davinci_xfer,
 724        .functionality  = i2c_davinci_func,
 725};
 726
 727static const struct of_device_id davinci_i2c_of_match[] = {
 728        {.compatible = "ti,davinci-i2c", },
 729        {},
 730};
 731MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
 732
 733static int davinci_i2c_probe(struct platform_device *pdev)
 734{
 735        struct davinci_i2c_dev *dev;
 736        struct i2c_adapter *adap;
 737        struct resource *mem;
 738        int r, irq;
 739
 740        irq = platform_get_irq(pdev, 0);
 741        if (irq <= 0) {
 742                if (!irq)
 743                        irq = -ENXIO;
 744                if (irq != -EPROBE_DEFER)
 745                        dev_err(&pdev->dev,
 746                                "can't get irq resource ret=%d\n", irq);
 747                return irq;
 748        }
 749
 750        dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
 751                        GFP_KERNEL);
 752        if (!dev) {
 753                dev_err(&pdev->dev, "Memory allocation failed\n");
 754                return -ENOMEM;
 755        }
 756
 757        init_completion(&dev->cmd_complete);
 758#ifdef CONFIG_CPU_FREQ
 759        init_completion(&dev->xfr_complete);
 760#endif
 761        dev->dev = &pdev->dev;
 762        dev->irq = irq;
 763        dev->pdata = dev_get_platdata(&pdev->dev);
 764        platform_set_drvdata(pdev, dev);
 765
 766        if (!dev->pdata && pdev->dev.of_node) {
 767                u32 prop;
 768
 769                dev->pdata = devm_kzalloc(&pdev->dev,
 770                        sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
 771                if (!dev->pdata)
 772                        return -ENOMEM;
 773
 774                memcpy(dev->pdata, &davinci_i2c_platform_data_default,
 775                        sizeof(struct davinci_i2c_platform_data));
 776                if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 777                        &prop))
 778                        dev->pdata->bus_freq = prop / 1000;
 779
 780                dev->pdata->has_pfunc =
 781                        of_property_read_bool(pdev->dev.of_node,
 782                                              "ti,has-pfunc");
 783        } else if (!dev->pdata) {
 784                dev->pdata = &davinci_i2c_platform_data_default;
 785        }
 786
 787        dev->clk = devm_clk_get(&pdev->dev, NULL);
 788        if (IS_ERR(dev->clk))
 789                return -ENODEV;
 790        clk_prepare_enable(dev->clk);
 791
 792        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 793        dev->base = devm_ioremap_resource(&pdev->dev, mem);
 794        if (IS_ERR(dev->base)) {
 795                r = PTR_ERR(dev->base);
 796                goto err_unuse_clocks;
 797        }
 798
 799        i2c_davinci_init(dev);
 800
 801        r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
 802                        pdev->name, dev);
 803        if (r) {
 804                dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
 805                goto err_unuse_clocks;
 806        }
 807
 808        r = i2c_davinci_cpufreq_register(dev);
 809        if (r) {
 810                dev_err(&pdev->dev, "failed to register cpufreq\n");
 811                goto err_unuse_clocks;
 812        }
 813
 814        adap = &dev->adapter;
 815        i2c_set_adapdata(adap, dev);
 816        adap->owner = THIS_MODULE;
 817        adap->class = I2C_CLASS_DEPRECATED;
 818        strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
 819        adap->algo = &i2c_davinci_algo;
 820        adap->dev.parent = &pdev->dev;
 821        adap->timeout = DAVINCI_I2C_TIMEOUT;
 822        adap->dev.of_node = pdev->dev.of_node;
 823
 824        if (dev->pdata->has_pfunc)
 825                adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
 826        else if (dev->pdata->scl_pin) {
 827                adap->bus_recovery_info = &davinci_i2c_gpio_recovery_info;
 828                adap->bus_recovery_info->scl_gpio = dev->pdata->scl_pin;
 829                adap->bus_recovery_info->sda_gpio = dev->pdata->sda_pin;
 830        }
 831
 832        adap->nr = pdev->id;
 833        r = i2c_add_numbered_adapter(adap);
 834        if (r) {
 835                dev_err(&pdev->dev, "failure adding adapter\n");
 836                goto err_unuse_clocks;
 837        }
 838
 839        return 0;
 840
 841err_unuse_clocks:
 842        clk_disable_unprepare(dev->clk);
 843        dev->clk = NULL;
 844        return r;
 845}
 846
 847static int davinci_i2c_remove(struct platform_device *pdev)
 848{
 849        struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
 850
 851        i2c_davinci_cpufreq_deregister(dev);
 852
 853        i2c_del_adapter(&dev->adapter);
 854
 855        clk_disable_unprepare(dev->clk);
 856        dev->clk = NULL;
 857
 858        davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
 859
 860        return 0;
 861}
 862
 863#ifdef CONFIG_PM
 864static int davinci_i2c_suspend(struct device *dev)
 865{
 866        struct platform_device *pdev = to_platform_device(dev);
 867        struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 868
 869        /* put I2C into reset */
 870        davinci_i2c_reset_ctrl(i2c_dev, 0);
 871        clk_disable_unprepare(i2c_dev->clk);
 872
 873        return 0;
 874}
 875
 876static int davinci_i2c_resume(struct device *dev)
 877{
 878        struct platform_device *pdev = to_platform_device(dev);
 879        struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 880
 881        clk_prepare_enable(i2c_dev->clk);
 882        /* take I2C out of reset */
 883        davinci_i2c_reset_ctrl(i2c_dev, 1);
 884
 885        return 0;
 886}
 887
 888static const struct dev_pm_ops davinci_i2c_pm = {
 889        .suspend        = davinci_i2c_suspend,
 890        .resume         = davinci_i2c_resume,
 891};
 892
 893#define davinci_i2c_pm_ops (&davinci_i2c_pm)
 894#else
 895#define davinci_i2c_pm_ops NULL
 896#endif
 897
 898/* work with hotplug and coldplug */
 899MODULE_ALIAS("platform:i2c_davinci");
 900
 901static struct platform_driver davinci_i2c_driver = {
 902        .probe          = davinci_i2c_probe,
 903        .remove         = davinci_i2c_remove,
 904        .driver         = {
 905                .name   = "i2c_davinci",
 906                .pm     = davinci_i2c_pm_ops,
 907                .of_match_table = davinci_i2c_of_match,
 908        },
 909};
 910
 911/* I2C may be needed to bring up other drivers */
 912static int __init davinci_i2c_init_driver(void)
 913{
 914        return platform_driver_register(&davinci_i2c_driver);
 915}
 916subsys_initcall(davinci_i2c_init_driver);
 917
 918static void __exit davinci_i2c_exit_driver(void)
 919{
 920        platform_driver_unregister(&davinci_i2c_driver);
 921}
 922module_exit(davinci_i2c_exit_driver);
 923
 924MODULE_AUTHOR("Texas Instruments India");
 925MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
 926MODULE_LICENSE("GPL");
 927