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76#include <linux/interrupt.h>
77#include <linux/module.h>
78#include <linux/pci.h>
79#include <linux/kernel.h>
80#include <linux/stddef.h>
81#include <linux/delay.h>
82#include <linux/ioport.h>
83#include <linux/init.h>
84#include <linux/i2c.h>
85#include <linux/acpi.h>
86#include <linux/io.h>
87#include <linux/dmi.h>
88#include <linux/slab.h>
89#include <linux/wait.h>
90#include <linux/err.h>
91#include <linux/platform_device.h>
92#include <linux/platform_data/itco_wdt.h>
93
94#if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
95 defined CONFIG_DMI
96#include <linux/gpio.h>
97#include <linux/i2c-mux-gpio.h>
98#endif
99
100
101#define SMBHSTSTS(p) (0 + (p)->smba)
102#define SMBHSTCNT(p) (2 + (p)->smba)
103#define SMBHSTCMD(p) (3 + (p)->smba)
104#define SMBHSTADD(p) (4 + (p)->smba)
105#define SMBHSTDAT0(p) (5 + (p)->smba)
106#define SMBHSTDAT1(p) (6 + (p)->smba)
107#define SMBBLKDAT(p) (7 + (p)->smba)
108#define SMBPEC(p) (8 + (p)->smba)
109#define SMBAUXSTS(p) (12 + (p)->smba)
110#define SMBAUXCTL(p) (13 + (p)->smba)
111
112
113#define SMBBAR 4
114#define SMBPCICTL 0x004
115#define SMBPCISTS 0x006
116#define SMBHSTCFG 0x040
117#define TCOBASE 0x050
118#define TCOCTL 0x054
119
120#define ACPIBASE 0x040
121#define ACPIBASE_SMI_OFF 0x030
122#define ACPICTRL 0x044
123#define ACPICTRL_EN 0x080
124
125#define SBREG_BAR 0x10
126#define SBREG_SMBCTRL 0xc6000c
127
128
129#define SMBPCISTS_INTS 0x08
130
131
132#define SMBPCICTL_INTDIS 0x0400
133
134
135#define SMBHSTCFG_HST_EN 1
136#define SMBHSTCFG_SMB_SMI_EN 2
137#define SMBHSTCFG_I2C_EN 4
138
139
140#define TCOCTL_EN 0x0100
141
142
143#define SMBAUXCTL_CRC 1
144#define SMBAUXCTL_E32B 2
145
146
147#define MAX_RETRIES 400
148
149
150#define I801_QUICK 0x00
151#define I801_BYTE 0x04
152#define I801_BYTE_DATA 0x08
153#define I801_WORD_DATA 0x0C
154#define I801_PROC_CALL 0x10
155#define I801_BLOCK_DATA 0x14
156#define I801_I2C_BLOCK_DATA 0x18
157
158
159#define SMBHSTCNT_INTREN 0x01
160#define SMBHSTCNT_KILL 0x02
161#define SMBHSTCNT_LAST_BYTE 0x20
162#define SMBHSTCNT_START 0x40
163#define SMBHSTCNT_PEC_EN 0x80
164
165
166#define SMBHSTSTS_BYTE_DONE 0x80
167#define SMBHSTSTS_INUSE_STS 0x40
168#define SMBHSTSTS_SMBALERT_STS 0x20
169#define SMBHSTSTS_FAILED 0x10
170#define SMBHSTSTS_BUS_ERR 0x08
171#define SMBHSTSTS_DEV_ERR 0x04
172#define SMBHSTSTS_INTR 0x02
173#define SMBHSTSTS_HOST_BUSY 0x01
174
175#define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
176 SMBHSTSTS_DEV_ERR)
177
178#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
179 STATUS_ERROR_FLAGS)
180
181
182#define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
183#define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
184#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
185#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
186
187#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
188#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
189#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
190#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
191#define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
192#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
193#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
194#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
195#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
196#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
197#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
198#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
199#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
200#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
201#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
202#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
203#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
204#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
205
206struct i801_mux_config {
207 char *gpio_chip;
208 unsigned values[3];
209 int n_values;
210 unsigned classes[3];
211 unsigned gpios[2];
212 int n_gpios;
213};
214
215struct i801_priv {
216 struct i2c_adapter adapter;
217 unsigned long smba;
218 unsigned char original_hstcfg;
219 struct pci_dev *pci_dev;
220 unsigned int features;
221
222
223 wait_queue_head_t waitq;
224 u8 status;
225
226
227 u8 cmd;
228 bool is_read;
229 int count;
230 int len;
231 u8 *data;
232
233#if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
234 defined CONFIG_DMI
235 const struct i801_mux_config *mux_drvdata;
236 struct platform_device *mux_pdev;
237#endif
238 struct platform_device *tco_pdev;
239};
240
241#define FEATURE_SMBUS_PEC (1 << 0)
242#define FEATURE_BLOCK_BUFFER (1 << 1)
243#define FEATURE_BLOCK_PROC (1 << 2)
244#define FEATURE_I2C_BLOCK_READ (1 << 3)
245#define FEATURE_IRQ (1 << 4)
246
247#define FEATURE_IDF (1 << 15)
248#define FEATURE_TCO (1 << 16)
249
250static const char *i801_feature_names[] = {
251 "SMBus PEC",
252 "Block buffer",
253 "Block process call",
254 "I2C block read",
255 "Interrupt",
256};
257
258static unsigned int disable_features;
259module_param(disable_features, uint, S_IRUGO | S_IWUSR);
260MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
261 "\t\t 0x01 disable SMBus PEC\n"
262 "\t\t 0x02 disable the block buffer\n"
263 "\t\t 0x08 disable the I2C block read functionality\n"
264 "\t\t 0x10 don't use interrupts ");
265
266
267
268static int i801_check_pre(struct i801_priv *priv)
269{
270 int status;
271
272 status = inb_p(SMBHSTSTS(priv));
273 if (status & SMBHSTSTS_HOST_BUSY) {
274 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
275 return -EBUSY;
276 }
277
278 status &= STATUS_FLAGS;
279 if (status) {
280 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
281 status);
282 outb_p(status, SMBHSTSTS(priv));
283 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
284 if (status) {
285 dev_err(&priv->pci_dev->dev,
286 "Failed clearing status flags (%02x)\n",
287 status);
288 return -EBUSY;
289 }
290 }
291
292 return 0;
293}
294
295
296
297
298
299
300static int i801_check_post(struct i801_priv *priv, int status)
301{
302 int result = 0;
303
304
305
306
307
308
309
310 if (unlikely(status < 0)) {
311 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
312
313 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
314 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
315 SMBHSTCNT(priv));
316 usleep_range(1000, 2000);
317 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
318 SMBHSTCNT(priv));
319
320
321 status = inb_p(SMBHSTSTS(priv));
322 if ((status & SMBHSTSTS_HOST_BUSY) ||
323 !(status & SMBHSTSTS_FAILED))
324 dev_err(&priv->pci_dev->dev,
325 "Failed terminating the transaction\n");
326 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
327 return -ETIMEDOUT;
328 }
329
330 if (status & SMBHSTSTS_FAILED) {
331 result = -EIO;
332 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
333 }
334 if (status & SMBHSTSTS_DEV_ERR) {
335 result = -ENXIO;
336 dev_dbg(&priv->pci_dev->dev, "No response\n");
337 }
338 if (status & SMBHSTSTS_BUS_ERR) {
339 result = -EAGAIN;
340 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
341 }
342
343
344 outb_p(status, SMBHSTSTS(priv));
345
346 return result;
347}
348
349
350static int i801_wait_intr(struct i801_priv *priv)
351{
352 int timeout = 0;
353 int status;
354
355
356 do {
357 usleep_range(250, 500);
358 status = inb_p(SMBHSTSTS(priv));
359 } while (((status & SMBHSTSTS_HOST_BUSY) ||
360 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
361 (timeout++ < MAX_RETRIES));
362
363 if (timeout > MAX_RETRIES) {
364 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
365 return -ETIMEDOUT;
366 }
367 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
368}
369
370
371static int i801_wait_byte_done(struct i801_priv *priv)
372{
373 int timeout = 0;
374 int status;
375
376
377 do {
378 usleep_range(250, 500);
379 status = inb_p(SMBHSTSTS(priv));
380 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
381 (timeout++ < MAX_RETRIES));
382
383 if (timeout > MAX_RETRIES) {
384 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
385 return -ETIMEDOUT;
386 }
387 return status & STATUS_ERROR_FLAGS;
388}
389
390static int i801_transaction(struct i801_priv *priv, int xact)
391{
392 int status;
393 int result;
394 const struct i2c_adapter *adap = &priv->adapter;
395
396 result = i801_check_pre(priv);
397 if (result < 0)
398 return result;
399
400 if (priv->features & FEATURE_IRQ) {
401 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
402 SMBHSTCNT(priv));
403 result = wait_event_timeout(priv->waitq,
404 (status = priv->status),
405 adap->timeout);
406 if (!result) {
407 status = -ETIMEDOUT;
408 dev_warn(&priv->pci_dev->dev,
409 "Timeout waiting for interrupt!\n");
410 }
411 priv->status = 0;
412 return i801_check_post(priv, status);
413 }
414
415
416
417 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
418
419 status = i801_wait_intr(priv);
420 return i801_check_post(priv, status);
421}
422
423static int i801_block_transaction_by_block(struct i801_priv *priv,
424 union i2c_smbus_data *data,
425 char read_write, int hwpec)
426{
427 int i, len;
428 int status;
429
430 inb_p(SMBHSTCNT(priv));
431
432
433 if (read_write == I2C_SMBUS_WRITE) {
434 len = data->block[0];
435 outb_p(len, SMBHSTDAT0(priv));
436 for (i = 0; i < len; i++)
437 outb_p(data->block[i+1], SMBBLKDAT(priv));
438 }
439
440 status = i801_transaction(priv, I801_BLOCK_DATA |
441 (hwpec ? SMBHSTCNT_PEC_EN : 0));
442 if (status)
443 return status;
444
445 if (read_write == I2C_SMBUS_READ) {
446 len = inb_p(SMBHSTDAT0(priv));
447 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
448 return -EPROTO;
449
450 data->block[0] = len;
451 for (i = 0; i < len; i++)
452 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
453 }
454 return 0;
455}
456
457static void i801_isr_byte_done(struct i801_priv *priv)
458{
459 if (priv->is_read) {
460
461 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
462 (priv->count == 0)) {
463 priv->len = inb_p(SMBHSTDAT0(priv));
464 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
465 dev_err(&priv->pci_dev->dev,
466 "Illegal SMBus block read size %d\n",
467 priv->len);
468
469 priv->len = I2C_SMBUS_BLOCK_MAX;
470 } else {
471 dev_dbg(&priv->pci_dev->dev,
472 "SMBus block read size is %d\n",
473 priv->len);
474 }
475 priv->data[-1] = priv->len;
476 }
477
478
479 if (priv->count < priv->len)
480 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
481 else
482 dev_dbg(&priv->pci_dev->dev,
483 "Discarding extra byte on block read\n");
484
485
486 if (priv->count == priv->len - 1)
487 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
488 SMBHSTCNT(priv));
489 } else if (priv->count < priv->len - 1) {
490
491 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
492 }
493
494
495 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
496}
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512static irqreturn_t i801_isr(int irq, void *dev_id)
513{
514 struct i801_priv *priv = dev_id;
515 u16 pcists;
516 u8 status;
517
518
519 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
520 if (!(pcists & SMBPCISTS_INTS))
521 return IRQ_NONE;
522
523 status = inb_p(SMBHSTSTS(priv));
524 if (status & SMBHSTSTS_BYTE_DONE)
525 i801_isr_byte_done(priv);
526
527
528
529
530
531 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
532 if (status) {
533 outb_p(status, SMBHSTSTS(priv));
534 priv->status |= status;
535 wake_up(&priv->waitq);
536 }
537
538 return IRQ_HANDLED;
539}
540
541
542
543
544
545
546static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
547 union i2c_smbus_data *data,
548 char read_write, int command,
549 int hwpec)
550{
551 int i, len;
552 int smbcmd;
553 int status;
554 int result;
555 const struct i2c_adapter *adap = &priv->adapter;
556
557 result = i801_check_pre(priv);
558 if (result < 0)
559 return result;
560
561 len = data->block[0];
562
563 if (read_write == I2C_SMBUS_WRITE) {
564 outb_p(len, SMBHSTDAT0(priv));
565 outb_p(data->block[1], SMBBLKDAT(priv));
566 }
567
568 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
569 read_write == I2C_SMBUS_READ)
570 smbcmd = I801_I2C_BLOCK_DATA;
571 else
572 smbcmd = I801_BLOCK_DATA;
573
574 if (priv->features & FEATURE_IRQ) {
575 priv->is_read = (read_write == I2C_SMBUS_READ);
576 if (len == 1 && priv->is_read)
577 smbcmd |= SMBHSTCNT_LAST_BYTE;
578 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
579 priv->len = len;
580 priv->count = 0;
581 priv->data = &data->block[1];
582
583 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
584 result = wait_event_timeout(priv->waitq,
585 (status = priv->status),
586 adap->timeout);
587 if (!result) {
588 status = -ETIMEDOUT;
589 dev_warn(&priv->pci_dev->dev,
590 "Timeout waiting for interrupt!\n");
591 }
592 priv->status = 0;
593 return i801_check_post(priv, status);
594 }
595
596 for (i = 1; i <= len; i++) {
597 if (i == len && read_write == I2C_SMBUS_READ)
598 smbcmd |= SMBHSTCNT_LAST_BYTE;
599 outb_p(smbcmd, SMBHSTCNT(priv));
600
601 if (i == 1)
602 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
603 SMBHSTCNT(priv));
604
605 status = i801_wait_byte_done(priv);
606 if (status)
607 goto exit;
608
609 if (i == 1 && read_write == I2C_SMBUS_READ
610 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
611 len = inb_p(SMBHSTDAT0(priv));
612 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
613 dev_err(&priv->pci_dev->dev,
614 "Illegal SMBus block read size %d\n",
615 len);
616
617 while (inb_p(SMBHSTSTS(priv)) &
618 SMBHSTSTS_HOST_BUSY)
619 outb_p(SMBHSTSTS_BYTE_DONE,
620 SMBHSTSTS(priv));
621 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
622 return -EPROTO;
623 }
624 data->block[0] = len;
625 }
626
627
628 if (read_write == I2C_SMBUS_READ)
629 data->block[i] = inb_p(SMBBLKDAT(priv));
630 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
631 outb_p(data->block[i+1], SMBBLKDAT(priv));
632
633
634 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
635 }
636
637 status = i801_wait_intr(priv);
638exit:
639 return i801_check_post(priv, status);
640}
641
642static int i801_set_block_buffer_mode(struct i801_priv *priv)
643{
644 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
645 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
646 return -EIO;
647 return 0;
648}
649
650
651static int i801_block_transaction(struct i801_priv *priv,
652 union i2c_smbus_data *data, char read_write,
653 int command, int hwpec)
654{
655 int result = 0;
656 unsigned char hostc;
657
658 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
659 if (read_write == I2C_SMBUS_WRITE) {
660
661 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
662 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
663 hostc | SMBHSTCFG_I2C_EN);
664 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
665 dev_err(&priv->pci_dev->dev,
666 "I2C block read is unsupported!\n");
667 return -EOPNOTSUPP;
668 }
669 }
670
671 if (read_write == I2C_SMBUS_WRITE
672 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
673 if (data->block[0] < 1)
674 data->block[0] = 1;
675 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
676 data->block[0] = I2C_SMBUS_BLOCK_MAX;
677 } else {
678 data->block[0] = 32;
679 }
680
681
682
683
684 if ((priv->features & FEATURE_BLOCK_BUFFER)
685 && command != I2C_SMBUS_I2C_BLOCK_DATA
686 && i801_set_block_buffer_mode(priv) == 0)
687 result = i801_block_transaction_by_block(priv, data,
688 read_write, hwpec);
689 else
690 result = i801_block_transaction_byte_by_byte(priv, data,
691 read_write,
692 command, hwpec);
693
694 if (command == I2C_SMBUS_I2C_BLOCK_DATA
695 && read_write == I2C_SMBUS_WRITE) {
696
697 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
698 }
699 return result;
700}
701
702
703static s32 i801_access(struct i2c_adapter *adap, u16 addr,
704 unsigned short flags, char read_write, u8 command,
705 int size, union i2c_smbus_data *data)
706{
707 int hwpec;
708 int block = 0;
709 int ret, xact = 0;
710 struct i801_priv *priv = i2c_get_adapdata(adap);
711
712 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
713 && size != I2C_SMBUS_QUICK
714 && size != I2C_SMBUS_I2C_BLOCK_DATA;
715
716 switch (size) {
717 case I2C_SMBUS_QUICK:
718 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
719 SMBHSTADD(priv));
720 xact = I801_QUICK;
721 break;
722 case I2C_SMBUS_BYTE:
723 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
724 SMBHSTADD(priv));
725 if (read_write == I2C_SMBUS_WRITE)
726 outb_p(command, SMBHSTCMD(priv));
727 xact = I801_BYTE;
728 break;
729 case I2C_SMBUS_BYTE_DATA:
730 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
731 SMBHSTADD(priv));
732 outb_p(command, SMBHSTCMD(priv));
733 if (read_write == I2C_SMBUS_WRITE)
734 outb_p(data->byte, SMBHSTDAT0(priv));
735 xact = I801_BYTE_DATA;
736 break;
737 case I2C_SMBUS_WORD_DATA:
738 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
739 SMBHSTADD(priv));
740 outb_p(command, SMBHSTCMD(priv));
741 if (read_write == I2C_SMBUS_WRITE) {
742 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
743 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
744 }
745 xact = I801_WORD_DATA;
746 break;
747 case I2C_SMBUS_BLOCK_DATA:
748 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
749 SMBHSTADD(priv));
750 outb_p(command, SMBHSTCMD(priv));
751 block = 1;
752 break;
753 case I2C_SMBUS_I2C_BLOCK_DATA:
754
755
756 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
757 if (read_write == I2C_SMBUS_READ) {
758
759
760 outb_p(command, SMBHSTDAT1(priv));
761 } else
762 outb_p(command, SMBHSTCMD(priv));
763 block = 1;
764 break;
765 default:
766 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
767 size);
768 return -EOPNOTSUPP;
769 }
770
771 if (hwpec)
772 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
773 else
774 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
775 SMBAUXCTL(priv));
776
777 if (block)
778 ret = i801_block_transaction(priv, data, read_write, size,
779 hwpec);
780 else
781 ret = i801_transaction(priv, xact);
782
783
784
785
786 if (hwpec || block)
787 outb_p(inb_p(SMBAUXCTL(priv)) &
788 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
789
790 if (block)
791 return ret;
792 if (ret)
793 return ret;
794 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
795 return 0;
796
797 switch (xact & 0x7f) {
798 case I801_BYTE:
799 case I801_BYTE_DATA:
800 data->byte = inb_p(SMBHSTDAT0(priv));
801 break;
802 case I801_WORD_DATA:
803 data->word = inb_p(SMBHSTDAT0(priv)) +
804 (inb_p(SMBHSTDAT1(priv)) << 8);
805 break;
806 }
807 return 0;
808}
809
810
811static u32 i801_func(struct i2c_adapter *adapter)
812{
813 struct i801_priv *priv = i2c_get_adapdata(adapter);
814
815 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
816 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
817 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
818 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
819 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
820 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
821}
822
823static const struct i2c_algorithm smbus_algorithm = {
824 .smbus_xfer = i801_access,
825 .functionality = i801_func,
826};
827
828static const struct pci_device_id i801_ids[] = {
829 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
830 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
831 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
832 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
833 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
834 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
835 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
836 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
837 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
838 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
839 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
840 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
841 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
842 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
843 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
844 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
845 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
846 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
847 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
848 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
849 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
850 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
851 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
852 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
853 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
854 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
855 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
856 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
857 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
858 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
859 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
860 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
861 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
862 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
863 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
864 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
865 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
866 { 0, }
867};
868
869MODULE_DEVICE_TABLE(pci, i801_ids);
870
871#if defined CONFIG_X86 && defined CONFIG_DMI
872static unsigned char apanel_addr;
873
874
875static __init const void __iomem *bios_signature(const void __iomem *bios)
876{
877 ssize_t offset;
878 const unsigned char signature[] = "FJKEYINF";
879
880 for (offset = 0; offset < 0x10000; offset += 0x10) {
881 if (check_signature(bios + offset, signature,
882 sizeof(signature)-1))
883 return bios + offset;
884 }
885 return NULL;
886}
887
888static void __init input_apanel_init(void)
889{
890 void __iomem *bios;
891 const void __iomem *p;
892
893 bios = ioremap(0xF0000, 0x10000);
894 p = bios_signature(bios);
895 if (p) {
896
897 apanel_addr = readb(p + 8 + 3) >> 1;
898 }
899 iounmap(bios);
900}
901
902struct dmi_onboard_device_info {
903 const char *name;
904 u8 type;
905 unsigned short i2c_addr;
906 const char *i2c_type;
907};
908
909static const struct dmi_onboard_device_info dmi_devices[] = {
910 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
911 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
912 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
913};
914
915static void dmi_check_onboard_device(u8 type, const char *name,
916 struct i2c_adapter *adap)
917{
918 int i;
919 struct i2c_board_info info;
920
921 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
922
923 if ((type & ~0x80) != dmi_devices[i].type)
924 continue;
925 if (strcasecmp(name, dmi_devices[i].name))
926 continue;
927
928 memset(&info, 0, sizeof(struct i2c_board_info));
929 info.addr = dmi_devices[i].i2c_addr;
930 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
931 i2c_new_device(adap, &info);
932 break;
933 }
934}
935
936
937
938
939static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
940{
941 int i, count;
942
943 if (dm->type != 10)
944 return;
945
946 count = (dm->length - sizeof(struct dmi_header)) / 2;
947 for (i = 0; i < count; i++) {
948 const u8 *d = (char *)(dm + 1) + (i * 2);
949 const char *name = ((char *) dm) + dm->length;
950 u8 type = d[0];
951 u8 s = d[1];
952
953 if (!s)
954 continue;
955 s--;
956 while (s > 0 && name[0]) {
957 name += strlen(name) + 1;
958 s--;
959 }
960 if (name[0] == 0)
961 continue;
962
963 dmi_check_onboard_device(type, name, adap);
964 }
965}
966
967
968static void i801_probe_optional_slaves(struct i801_priv *priv)
969{
970
971 if (priv->features & FEATURE_IDF)
972 return;
973
974 if (apanel_addr) {
975 struct i2c_board_info info;
976
977 memset(&info, 0, sizeof(struct i2c_board_info));
978 info.addr = apanel_addr;
979 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
980 i2c_new_device(&priv->adapter, &info);
981 }
982
983 if (dmi_name_in_vendors("FUJITSU"))
984 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
985}
986#else
987static void __init input_apanel_init(void) {}
988static void i801_probe_optional_slaves(struct i801_priv *priv) {}
989#endif
990
991#if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
992 defined CONFIG_DMI
993static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
994 .gpio_chip = "gpio_ich",
995 .values = { 0x02, 0x03 },
996 .n_values = 2,
997 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
998 .gpios = { 52, 53 },
999 .n_gpios = 2,
1000};
1001
1002static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1003 .gpio_chip = "gpio_ich",
1004 .values = { 0x02, 0x03, 0x01 },
1005 .n_values = 3,
1006 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1007 .gpios = { 52, 53 },
1008 .n_gpios = 2,
1009};
1010
1011static const struct dmi_system_id mux_dmi_table[] = {
1012 {
1013 .matches = {
1014 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1015 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1016 },
1017 .driver_data = &i801_mux_config_asus_z8_d12,
1018 },
1019 {
1020 .matches = {
1021 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1022 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1023 },
1024 .driver_data = &i801_mux_config_asus_z8_d12,
1025 },
1026 {
1027 .matches = {
1028 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1029 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1030 },
1031 .driver_data = &i801_mux_config_asus_z8_d12,
1032 },
1033 {
1034 .matches = {
1035 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1036 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1037 },
1038 .driver_data = &i801_mux_config_asus_z8_d12,
1039 },
1040 {
1041 .matches = {
1042 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1043 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1044 },
1045 .driver_data = &i801_mux_config_asus_z8_d12,
1046 },
1047 {
1048 .matches = {
1049 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1050 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1051 },
1052 .driver_data = &i801_mux_config_asus_z8_d12,
1053 },
1054 {
1055 .matches = {
1056 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1057 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1058 },
1059 .driver_data = &i801_mux_config_asus_z8_d18,
1060 },
1061 {
1062 .matches = {
1063 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1064 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1065 },
1066 .driver_data = &i801_mux_config_asus_z8_d18,
1067 },
1068 {
1069 .matches = {
1070 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1071 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1072 },
1073 .driver_data = &i801_mux_config_asus_z8_d12,
1074 },
1075 { }
1076};
1077
1078
1079static int i801_add_mux(struct i801_priv *priv)
1080{
1081 struct device *dev = &priv->adapter.dev;
1082 const struct i801_mux_config *mux_config;
1083 struct i2c_mux_gpio_platform_data gpio_data;
1084 int err;
1085
1086 if (!priv->mux_drvdata)
1087 return 0;
1088 mux_config = priv->mux_drvdata;
1089
1090
1091 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1092 gpio_data.parent = priv->adapter.nr;
1093 gpio_data.values = mux_config->values;
1094 gpio_data.n_values = mux_config->n_values;
1095 gpio_data.classes = mux_config->classes;
1096 gpio_data.gpio_chip = mux_config->gpio_chip;
1097 gpio_data.gpios = mux_config->gpios;
1098 gpio_data.n_gpios = mux_config->n_gpios;
1099 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1100
1101
1102 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1103 PLATFORM_DEVID_AUTO, &gpio_data,
1104 sizeof(struct i2c_mux_gpio_platform_data));
1105 if (IS_ERR(priv->mux_pdev)) {
1106 err = PTR_ERR(priv->mux_pdev);
1107 priv->mux_pdev = NULL;
1108 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1109 return err;
1110 }
1111
1112 return 0;
1113}
1114
1115static void i801_del_mux(struct i801_priv *priv)
1116{
1117 if (priv->mux_pdev)
1118 platform_device_unregister(priv->mux_pdev);
1119}
1120
1121static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1122{
1123 const struct dmi_system_id *id;
1124 const struct i801_mux_config *mux_config;
1125 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1126 int i;
1127
1128 id = dmi_first_match(mux_dmi_table);
1129 if (id) {
1130
1131 mux_config = id->driver_data;
1132 for (i = 0; i < mux_config->n_values; i++)
1133 class &= ~mux_config->classes[i];
1134
1135
1136 priv->mux_drvdata = mux_config;
1137 }
1138
1139 return class;
1140}
1141#else
1142static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1143static inline void i801_del_mux(struct i801_priv *priv) { }
1144
1145static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1146{
1147 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1148}
1149#endif
1150
1151static const struct itco_wdt_platform_data tco_platform_data = {
1152 .name = "Intel PCH",
1153 .version = 4,
1154};
1155
1156static DEFINE_SPINLOCK(p2sb_spinlock);
1157
1158static void i801_add_tco(struct i801_priv *priv)
1159{
1160 struct pci_dev *pci_dev = priv->pci_dev;
1161 struct resource tco_res[3], *res;
1162 struct platform_device *pdev;
1163 unsigned int devfn;
1164 u32 tco_base, tco_ctl;
1165 u32 base_addr, ctrl_val;
1166 u64 base64_addr;
1167
1168 if (!(priv->features & FEATURE_TCO))
1169 return;
1170
1171 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1172 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1173 if (!(tco_ctl & TCOCTL_EN))
1174 return;
1175
1176 memset(tco_res, 0, sizeof(tco_res));
1177
1178 res = &tco_res[ICH_RES_IO_TCO];
1179 res->start = tco_base & ~1;
1180 res->end = res->start + 32 - 1;
1181 res->flags = IORESOURCE_IO;
1182
1183
1184
1185
1186 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1187 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1188
1189 res = &tco_res[ICH_RES_IO_SMI];
1190 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1191 res->end = res->start + 3;
1192 res->flags = IORESOURCE_IO;
1193
1194
1195
1196
1197 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1198 ctrl_val |= ACPICTRL_EN;
1199 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1200
1201
1202
1203
1204
1205
1206
1207 spin_lock(&p2sb_spinlock);
1208
1209 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1210
1211
1212 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1213
1214 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1215 base64_addr = base_addr & 0xfffffff0;
1216
1217 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1218 base64_addr |= (u64)base_addr << 32;
1219
1220
1221 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1222 spin_unlock(&p2sb_spinlock);
1223
1224 res = &tco_res[ICH_RES_MEM_OFF];
1225 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1226 res->end = res->start + 3;
1227 res->flags = IORESOURCE_MEM;
1228
1229 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1230 tco_res, 3, &tco_platform_data,
1231 sizeof(tco_platform_data));
1232 if (IS_ERR(pdev)) {
1233 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1234 return;
1235 }
1236
1237 priv->tco_pdev = pdev;
1238}
1239
1240static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1241{
1242 unsigned char temp;
1243 int err, i;
1244 struct i801_priv *priv;
1245
1246 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1247 if (!priv)
1248 return -ENOMEM;
1249
1250 i2c_set_adapdata(&priv->adapter, priv);
1251 priv->adapter.owner = THIS_MODULE;
1252 priv->adapter.class = i801_get_adapter_class(priv);
1253 priv->adapter.algo = &smbus_algorithm;
1254
1255 priv->pci_dev = dev;
1256 switch (dev->device) {
1257 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1258 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1259 priv->features |= FEATURE_I2C_BLOCK_READ;
1260 priv->features |= FEATURE_IRQ;
1261 priv->features |= FEATURE_SMBUS_PEC;
1262 priv->features |= FEATURE_BLOCK_BUFFER;
1263 priv->features |= FEATURE_TCO;
1264 break;
1265
1266 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1267 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1268 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1269 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1270 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1271 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1272 priv->features |= FEATURE_IDF;
1273
1274 default:
1275 priv->features |= FEATURE_I2C_BLOCK_READ;
1276 priv->features |= FEATURE_IRQ;
1277
1278 case PCI_DEVICE_ID_INTEL_82801DB_3:
1279 priv->features |= FEATURE_SMBUS_PEC;
1280 priv->features |= FEATURE_BLOCK_BUFFER;
1281
1282 case PCI_DEVICE_ID_INTEL_82801CA_3:
1283 case PCI_DEVICE_ID_INTEL_82801BA_2:
1284 case PCI_DEVICE_ID_INTEL_82801AB_3:
1285 case PCI_DEVICE_ID_INTEL_82801AA_3:
1286 break;
1287 }
1288
1289
1290 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1291 if (priv->features & disable_features & (1 << i))
1292 dev_notice(&dev->dev, "%s disabled by user\n",
1293 i801_feature_names[i]);
1294 }
1295 priv->features &= ~disable_features;
1296
1297 err = pcim_enable_device(dev);
1298 if (err) {
1299 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1300 err);
1301 return err;
1302 }
1303 pcim_pin_device(dev);
1304
1305
1306 priv->smba = pci_resource_start(dev, SMBBAR);
1307 if (!priv->smba) {
1308 dev_err(&dev->dev,
1309 "SMBus base address uninitialized, upgrade BIOS\n");
1310 return -ENODEV;
1311 }
1312
1313 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1314 if (err) {
1315 return -ENODEV;
1316 }
1317
1318 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1319 dev_driver_string(&dev->dev));
1320 if (err) {
1321 dev_err(&dev->dev,
1322 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1323 priv->smba,
1324 (unsigned long long)pci_resource_end(dev, SMBBAR));
1325 return err;
1326 }
1327
1328 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1329 priv->original_hstcfg = temp;
1330 temp &= ~SMBHSTCFG_I2C_EN;
1331 if (!(temp & SMBHSTCFG_HST_EN)) {
1332 dev_info(&dev->dev, "Enabling SMBus device\n");
1333 temp |= SMBHSTCFG_HST_EN;
1334 }
1335 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1336
1337 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1338 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1339
1340 priv->features &= ~FEATURE_IRQ;
1341 }
1342
1343
1344 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1345 outb_p(inb_p(SMBAUXCTL(priv)) &
1346 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1347
1348
1349 priv->adapter.timeout = HZ / 5;
1350
1351 if (priv->features & FEATURE_IRQ) {
1352 u16 pcictl, pcists;
1353
1354
1355 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1356 if (pcists & SMBPCISTS_INTS)
1357 dev_warn(&dev->dev, "An interrupt is pending!\n");
1358
1359
1360 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1361 if (pcictl & SMBPCICTL_INTDIS) {
1362 dev_info(&dev->dev, "Interrupts are disabled\n");
1363 priv->features &= ~FEATURE_IRQ;
1364 }
1365 }
1366
1367 if (priv->features & FEATURE_IRQ) {
1368 init_waitqueue_head(&priv->waitq);
1369
1370 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1371 IRQF_SHARED,
1372 dev_driver_string(&dev->dev), priv);
1373 if (err) {
1374 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1375 dev->irq, err);
1376 priv->features &= ~FEATURE_IRQ;
1377 }
1378 }
1379 dev_info(&dev->dev, "SMBus using %s\n",
1380 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1381
1382 i801_add_tco(priv);
1383
1384
1385 priv->adapter.dev.parent = &dev->dev;
1386
1387
1388 priv->adapter.retries = 3;
1389
1390 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1391 "SMBus I801 adapter at %04lx", priv->smba);
1392 err = i2c_add_adapter(&priv->adapter);
1393 if (err) {
1394 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1395 return err;
1396 }
1397
1398 i801_probe_optional_slaves(priv);
1399
1400 i801_add_mux(priv);
1401
1402 pci_set_drvdata(dev, priv);
1403
1404 return 0;
1405}
1406
1407static void i801_remove(struct pci_dev *dev)
1408{
1409 struct i801_priv *priv = pci_get_drvdata(dev);
1410
1411 i801_del_mux(priv);
1412 i2c_del_adapter(&priv->adapter);
1413 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1414
1415 platform_device_unregister(priv->tco_pdev);
1416
1417
1418
1419
1420
1421}
1422
1423#ifdef CONFIG_PM
1424static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1425{
1426 struct i801_priv *priv = pci_get_drvdata(dev);
1427
1428 pci_save_state(dev);
1429 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1430 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1431 return 0;
1432}
1433
1434static int i801_resume(struct pci_dev *dev)
1435{
1436 pci_set_power_state(dev, PCI_D0);
1437 pci_restore_state(dev);
1438 return 0;
1439}
1440#else
1441#define i801_suspend NULL
1442#define i801_resume NULL
1443#endif
1444
1445static struct pci_driver i801_driver = {
1446 .name = "i801_smbus",
1447 .id_table = i801_ids,
1448 .probe = i801_probe,
1449 .remove = i801_remove,
1450 .suspend = i801_suspend,
1451 .resume = i801_resume,
1452};
1453
1454static int __init i2c_i801_init(void)
1455{
1456 if (dmi_name_in_vendors("FUJITSU"))
1457 input_apanel_init();
1458 return pci_register_driver(&i801_driver);
1459}
1460
1461static void __exit i2c_i801_exit(void)
1462{
1463 pci_unregister_driver(&i801_driver);
1464}
1465
1466MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1467MODULE_DESCRIPTION("I801 SMBus driver");
1468MODULE_LICENSE("GPL");
1469
1470module_init(i2c_i801_init);
1471module_exit(i2c_i801_exit);
1472