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5
6#ifndef __FLEXCOP_REG_H__
7#define __FLEXCOP_REG_H__
8
9typedef enum {
10 FLEXCOP_UNK = 0,
11 FLEXCOP_II,
12 FLEXCOP_IIB,
13 FLEXCOP_III,
14} flexcop_revision_t;
15
16typedef enum {
17 FC_UNK = 0,
18 FC_CABLE,
19 FC_AIR_DVBT,
20 FC_AIR_ATSC1,
21 FC_AIR_ATSC2,
22 FC_AIR_ATSC3,
23 FC_SKY_REV23,
24 FC_SKY_REV26,
25 FC_SKY_REV27,
26 FC_SKY_REV28,
27 FC_SKYS2_REV33,
28} flexcop_device_type_t;
29
30typedef enum {
31 FC_USB = 0,
32 FC_PCI,
33} flexcop_bus_t;
34
35
36#if defined(__LITTLE_ENDIAN)
37#include "flexcop_ibi_value_le.h"
38#else
39#if defined(__BIG_ENDIAN)
40#include "flexcop_ibi_value_be.h"
41#else
42#error no endian defined
43#endif
44#endif
45
46#define fc_data_Tag_ID_DVB 0x3e
47#define fc_data_Tag_ID_ATSC 0x3f
48#define fc_data_Tag_ID_IDSB 0x8b
49
50#define fc_key_code_default 0x1
51#define fc_key_code_even 0x2
52#define fc_key_code_odd 0x3
53
54extern flexcop_ibi_value ibi_zero;
55
56typedef enum {
57 FC_I2C_PORT_DEMOD = 1,
58 FC_I2C_PORT_EEPROM = 2,
59 FC_I2C_PORT_TUNER = 3,
60} flexcop_i2c_port_t;
61
62typedef enum {
63 FC_WRITE = 0,
64 FC_READ = 1,
65} flexcop_access_op_t;
66
67typedef enum {
68 FC_SRAM_DEST_NET = 1,
69 FC_SRAM_DEST_CAI = 2,
70 FC_SRAM_DEST_CAO = 4,
71 FC_SRAM_DEST_MEDIA = 8
72} flexcop_sram_dest_t;
73
74typedef enum {
75 FC_SRAM_DEST_TARGET_WAN_USB = 0,
76 FC_SRAM_DEST_TARGET_DMA1 = 1,
77 FC_SRAM_DEST_TARGET_DMA2 = 2,
78 FC_SRAM_DEST_TARGET_FC3_CA = 3
79} flexcop_sram_dest_target_t;
80
81typedef enum {
82 FC_SRAM_2_32KB = 0,
83 FC_SRAM_1_32KB = 1,
84 FC_SRAM_1_128KB = 2,
85 FC_SRAM_1_48KB = 3,
86} flexcop_sram_type_t;
87
88typedef enum {
89 FC_WAN_SPEED_4MBITS = 0,
90 FC_WAN_SPEED_8MBITS = 1,
91 FC_WAN_SPEED_12MBITS = 2,
92 FC_WAN_SPEED_16MBITS = 3,
93} flexcop_wan_speed_t;
94
95typedef enum {
96 FC_DMA_1 = 1,
97 FC_DMA_2 = 2,
98} flexcop_dma_index_t;
99
100typedef enum {
101 FC_DMA_SUBADDR_0 = 1,
102 FC_DMA_SUBADDR_1 = 2,
103} flexcop_dma_addr_index_t;
104
105
106typedef enum {
107 dma1_000 = 0x000,
108 dma1_004 = 0x004,
109 dma1_008 = 0x008,
110 dma1_00c = 0x00c,
111 dma2_010 = 0x010,
112 dma2_014 = 0x014,
113 dma2_018 = 0x018,
114 dma2_01c = 0x01c,
115
116 tw_sm_c_100 = 0x100,
117 tw_sm_c_104 = 0x104,
118 tw_sm_c_108 = 0x108,
119 tw_sm_c_10c = 0x10c,
120 tw_sm_c_110 = 0x110,
121
122 lnb_switch_freq_200 = 0x200,
123 misc_204 = 0x204,
124 ctrl_208 = 0x208,
125 irq_20c = 0x20c,
126 sw_reset_210 = 0x210,
127 misc_214 = 0x214,
128 mbox_v8_to_host_218 = 0x218,
129 mbox_host_to_v8_21c = 0x21c,
130
131 pid_filter_300 = 0x300,
132 pid_filter_304 = 0x304,
133 pid_filter_308 = 0x308,
134 pid_filter_30c = 0x30c,
135 index_reg_310 = 0x310,
136 pid_n_reg_314 = 0x314,
137 mac_low_reg_318 = 0x318,
138 mac_high_reg_31c = 0x31c,
139
140 data_tag_400 = 0x400,
141 card_id_408 = 0x408,
142 card_id_40c = 0x40c,
143 mac_address_418 = 0x418,
144 mac_address_41c = 0x41c,
145
146 ci_600 = 0x600,
147 pi_604 = 0x604,
148 pi_608 = 0x608,
149 dvb_reg_60c = 0x60c,
150
151 sram_ctrl_reg_700 = 0x700,
152 net_buf_reg_704 = 0x704,
153 cai_buf_reg_708 = 0x708,
154 cao_buf_reg_70c = 0x70c,
155 media_buf_reg_710 = 0x710,
156 sram_dest_reg_714 = 0x714,
157 net_buf_reg_718 = 0x718,
158 wan_ctrl_reg_71c = 0x71c,
159} flexcop_ibi_register;
160
161#define flexcop_set_ibi_value(reg,attr,val) { \
162 flexcop_ibi_value v = fc->read_ibi_reg(fc,reg); \
163 v.reg.attr = val; \
164 fc->write_ibi_reg(fc,reg,v); \
165}
166
167#endif
168
