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35#ifndef __T4_REGS_H
36#define __T4_REGS_H
37
38#define MYPF_BASE 0x1b000
39#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
40
41#define PF0_BASE 0x1e000
42#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
43
44#define PF_STRIDE 0x400
45#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
46#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
47
48#define MYPORT_BASE 0x1c000
49#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
50
51#define PORT0_BASE 0x20000
52#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
53
54#define PORT_STRIDE 0x2000
55#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
56#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
57
58#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
59#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
60
61#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
62#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
63#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
64#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
65
66#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
67
68#define SGE_PF_KDOORBELL_A 0x0
69
70#define QID_S 15
71#define QID_V(x) ((x) << QID_S)
72
73#define DBPRIO_S 14
74#define DBPRIO_V(x) ((x) << DBPRIO_S)
75#define DBPRIO_F DBPRIO_V(1U)
76
77#define PIDX_S 0
78#define PIDX_V(x) ((x) << PIDX_S)
79
80#define SGE_VF_KDOORBELL_A 0x0
81
82#define DBTYPE_S 13
83#define DBTYPE_V(x) ((x) << DBTYPE_S)
84#define DBTYPE_F DBTYPE_V(1U)
85
86#define PIDX_T5_S 0
87#define PIDX_T5_M 0x1fffU
88#define PIDX_T5_V(x) ((x) << PIDX_T5_S)
89#define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M)
90
91#define SGE_PF_GTS_A 0x4
92
93#define INGRESSQID_S 16
94#define INGRESSQID_V(x) ((x) << INGRESSQID_S)
95
96#define TIMERREG_S 13
97#define TIMERREG_V(x) ((x) << TIMERREG_S)
98
99#define SEINTARM_S 12
100#define SEINTARM_V(x) ((x) << SEINTARM_S)
101
102#define CIDXINC_S 0
103#define CIDXINC_M 0xfffU
104#define CIDXINC_V(x) ((x) << CIDXINC_S)
105
106#define SGE_CONTROL_A 0x1008
107#define SGE_CONTROL2_A 0x1124
108
109#define RXPKTCPLMODE_S 18
110#define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S)
111#define RXPKTCPLMODE_F RXPKTCPLMODE_V(1U)
112
113#define EGRSTATUSPAGESIZE_S 17
114#define EGRSTATUSPAGESIZE_V(x) ((x) << EGRSTATUSPAGESIZE_S)
115#define EGRSTATUSPAGESIZE_F EGRSTATUSPAGESIZE_V(1U)
116
117#define PKTSHIFT_S 10
118#define PKTSHIFT_M 0x7U
119#define PKTSHIFT_V(x) ((x) << PKTSHIFT_S)
120#define PKTSHIFT_G(x) (((x) >> PKTSHIFT_S) & PKTSHIFT_M)
121
122#define INGPCIEBOUNDARY_S 7
123#define INGPCIEBOUNDARY_V(x) ((x) << INGPCIEBOUNDARY_S)
124
125#define INGPADBOUNDARY_S 4
126#define INGPADBOUNDARY_M 0x7U
127#define INGPADBOUNDARY_V(x) ((x) << INGPADBOUNDARY_S)
128#define INGPADBOUNDARY_G(x) (((x) >> INGPADBOUNDARY_S) & INGPADBOUNDARY_M)
129
130#define EGRPCIEBOUNDARY_S 1
131#define EGRPCIEBOUNDARY_V(x) ((x) << EGRPCIEBOUNDARY_S)
132
133#define INGPACKBOUNDARY_S 16
134#define INGPACKBOUNDARY_M 0x7U
135#define INGPACKBOUNDARY_V(x) ((x) << INGPACKBOUNDARY_S)
136#define INGPACKBOUNDARY_G(x) (((x) >> INGPACKBOUNDARY_S) \
137 & INGPACKBOUNDARY_M)
138
139#define VFIFO_ENABLE_S 10
140#define VFIFO_ENABLE_V(x) ((x) << VFIFO_ENABLE_S)
141#define VFIFO_ENABLE_F VFIFO_ENABLE_V(1U)
142
143#define SGE_DBVFIFO_BADDR_A 0x1138
144
145#define DBVFIFO_SIZE_S 6
146#define DBVFIFO_SIZE_M 0xfffU
147#define DBVFIFO_SIZE_G(x) (((x) >> DBVFIFO_SIZE_S) & DBVFIFO_SIZE_M)
148
149#define T6_DBVFIFO_SIZE_S 0
150#define T6_DBVFIFO_SIZE_M 0x1fffU
151#define T6_DBVFIFO_SIZE_G(x) (((x) >> T6_DBVFIFO_SIZE_S) & T6_DBVFIFO_SIZE_M)
152
153#define GLOBALENABLE_S 0
154#define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S)
155#define GLOBALENABLE_F GLOBALENABLE_V(1U)
156
157#define SGE_HOST_PAGE_SIZE_A 0x100c
158
159#define HOSTPAGESIZEPF7_S 28
160#define HOSTPAGESIZEPF7_M 0xfU
161#define HOSTPAGESIZEPF7_V(x) ((x) << HOSTPAGESIZEPF7_S)
162#define HOSTPAGESIZEPF7_G(x) (((x) >> HOSTPAGESIZEPF7_S) & HOSTPAGESIZEPF7_M)
163
164#define HOSTPAGESIZEPF6_S 24
165#define HOSTPAGESIZEPF6_M 0xfU
166#define HOSTPAGESIZEPF6_V(x) ((x) << HOSTPAGESIZEPF6_S)
167#define HOSTPAGESIZEPF6_G(x) (((x) >> HOSTPAGESIZEPF6_S) & HOSTPAGESIZEPF6_M)
168
169#define HOSTPAGESIZEPF5_S 20
170#define HOSTPAGESIZEPF5_M 0xfU
171#define HOSTPAGESIZEPF5_V(x) ((x) << HOSTPAGESIZEPF5_S)
172#define HOSTPAGESIZEPF5_G(x) (((x) >> HOSTPAGESIZEPF5_S) & HOSTPAGESIZEPF5_M)
173
174#define HOSTPAGESIZEPF4_S 16
175#define HOSTPAGESIZEPF4_M 0xfU
176#define HOSTPAGESIZEPF4_V(x) ((x) << HOSTPAGESIZEPF4_S)
177#define HOSTPAGESIZEPF4_G(x) (((x) >> HOSTPAGESIZEPF4_S) & HOSTPAGESIZEPF4_M)
178
179#define HOSTPAGESIZEPF3_S 12
180#define HOSTPAGESIZEPF3_M 0xfU
181#define HOSTPAGESIZEPF3_V(x) ((x) << HOSTPAGESIZEPF3_S)
182#define HOSTPAGESIZEPF3_G(x) (((x) >> HOSTPAGESIZEPF3_S) & HOSTPAGESIZEPF3_M)
183
184#define HOSTPAGESIZEPF2_S 8
185#define HOSTPAGESIZEPF2_M 0xfU
186#define HOSTPAGESIZEPF2_V(x) ((x) << HOSTPAGESIZEPF2_S)
187#define HOSTPAGESIZEPF2_G(x) (((x) >> HOSTPAGESIZEPF2_S) & HOSTPAGESIZEPF2_M)
188
189#define HOSTPAGESIZEPF1_S 4
190#define HOSTPAGESIZEPF1_M 0xfU
191#define HOSTPAGESIZEPF1_V(x) ((x) << HOSTPAGESIZEPF1_S)
192#define HOSTPAGESIZEPF1_G(x) (((x) >> HOSTPAGESIZEPF1_S) & HOSTPAGESIZEPF1_M)
193
194#define HOSTPAGESIZEPF0_S 0
195#define HOSTPAGESIZEPF0_M 0xfU
196#define HOSTPAGESIZEPF0_V(x) ((x) << HOSTPAGESIZEPF0_S)
197#define HOSTPAGESIZEPF0_G(x) (((x) >> HOSTPAGESIZEPF0_S) & HOSTPAGESIZEPF0_M)
198
199#define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010
200#define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014
201
202#define QUEUESPERPAGEPF1_S 4
203
204#define QUEUESPERPAGEPF0_S 0
205#define QUEUESPERPAGEPF0_M 0xfU
206#define QUEUESPERPAGEPF0_V(x) ((x) << QUEUESPERPAGEPF0_S)
207#define QUEUESPERPAGEPF0_G(x) (((x) >> QUEUESPERPAGEPF0_S) & QUEUESPERPAGEPF0_M)
208
209#define SGE_INT_CAUSE1_A 0x1024
210#define SGE_INT_CAUSE2_A 0x1030
211#define SGE_INT_CAUSE3_A 0x103c
212
213#define ERR_FLM_DBP_S 31
214#define ERR_FLM_DBP_V(x) ((x) << ERR_FLM_DBP_S)
215#define ERR_FLM_DBP_F ERR_FLM_DBP_V(1U)
216
217#define ERR_FLM_IDMA1_S 30
218#define ERR_FLM_IDMA1_V(x) ((x) << ERR_FLM_IDMA1_S)
219#define ERR_FLM_IDMA1_F ERR_FLM_IDMA1_V(1U)
220
221#define ERR_FLM_IDMA0_S 29
222#define ERR_FLM_IDMA0_V(x) ((x) << ERR_FLM_IDMA0_S)
223#define ERR_FLM_IDMA0_F ERR_FLM_IDMA0_V(1U)
224
225#define ERR_FLM_HINT_S 28
226#define ERR_FLM_HINT_V(x) ((x) << ERR_FLM_HINT_S)
227#define ERR_FLM_HINT_F ERR_FLM_HINT_V(1U)
228
229#define ERR_PCIE_ERROR3_S 27
230#define ERR_PCIE_ERROR3_V(x) ((x) << ERR_PCIE_ERROR3_S)
231#define ERR_PCIE_ERROR3_F ERR_PCIE_ERROR3_V(1U)
232
233#define ERR_PCIE_ERROR2_S 26
234#define ERR_PCIE_ERROR2_V(x) ((x) << ERR_PCIE_ERROR2_S)
235#define ERR_PCIE_ERROR2_F ERR_PCIE_ERROR2_V(1U)
236
237#define ERR_PCIE_ERROR1_S 25
238#define ERR_PCIE_ERROR1_V(x) ((x) << ERR_PCIE_ERROR1_S)
239#define ERR_PCIE_ERROR1_F ERR_PCIE_ERROR1_V(1U)
240
241#define ERR_PCIE_ERROR0_S 24
242#define ERR_PCIE_ERROR0_V(x) ((x) << ERR_PCIE_ERROR0_S)
243#define ERR_PCIE_ERROR0_F ERR_PCIE_ERROR0_V(1U)
244
245#define ERR_CPL_EXCEED_IQE_SIZE_S 22
246#define ERR_CPL_EXCEED_IQE_SIZE_V(x) ((x) << ERR_CPL_EXCEED_IQE_SIZE_S)
247#define ERR_CPL_EXCEED_IQE_SIZE_F ERR_CPL_EXCEED_IQE_SIZE_V(1U)
248
249#define ERR_INVALID_CIDX_INC_S 21
250#define ERR_INVALID_CIDX_INC_V(x) ((x) << ERR_INVALID_CIDX_INC_S)
251#define ERR_INVALID_CIDX_INC_F ERR_INVALID_CIDX_INC_V(1U)
252
253#define ERR_CPL_OPCODE_0_S 19
254#define ERR_CPL_OPCODE_0_V(x) ((x) << ERR_CPL_OPCODE_0_S)
255#define ERR_CPL_OPCODE_0_F ERR_CPL_OPCODE_0_V(1U)
256
257#define ERR_DROPPED_DB_S 18
258#define ERR_DROPPED_DB_V(x) ((x) << ERR_DROPPED_DB_S)
259#define ERR_DROPPED_DB_F ERR_DROPPED_DB_V(1U)
260
261#define ERR_DATA_CPL_ON_HIGH_QID1_S 17
262#define ERR_DATA_CPL_ON_HIGH_QID1_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID1_S)
263#define ERR_DATA_CPL_ON_HIGH_QID1_F ERR_DATA_CPL_ON_HIGH_QID1_V(1U)
264
265#define ERR_DATA_CPL_ON_HIGH_QID0_S 16
266#define ERR_DATA_CPL_ON_HIGH_QID0_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID0_S)
267#define ERR_DATA_CPL_ON_HIGH_QID0_F ERR_DATA_CPL_ON_HIGH_QID0_V(1U)
268
269#define ERR_BAD_DB_PIDX3_S 15
270#define ERR_BAD_DB_PIDX3_V(x) ((x) << ERR_BAD_DB_PIDX3_S)
271#define ERR_BAD_DB_PIDX3_F ERR_BAD_DB_PIDX3_V(1U)
272
273#define ERR_BAD_DB_PIDX2_S 14
274#define ERR_BAD_DB_PIDX2_V(x) ((x) << ERR_BAD_DB_PIDX2_S)
275#define ERR_BAD_DB_PIDX2_F ERR_BAD_DB_PIDX2_V(1U)
276
277#define ERR_BAD_DB_PIDX1_S 13
278#define ERR_BAD_DB_PIDX1_V(x) ((x) << ERR_BAD_DB_PIDX1_S)
279#define ERR_BAD_DB_PIDX1_F ERR_BAD_DB_PIDX1_V(1U)
280
281#define ERR_BAD_DB_PIDX0_S 12
282#define ERR_BAD_DB_PIDX0_V(x) ((x) << ERR_BAD_DB_PIDX0_S)
283#define ERR_BAD_DB_PIDX0_F ERR_BAD_DB_PIDX0_V(1U)
284
285#define ERR_ING_CTXT_PRIO_S 10
286#define ERR_ING_CTXT_PRIO_V(x) ((x) << ERR_ING_CTXT_PRIO_S)
287#define ERR_ING_CTXT_PRIO_F ERR_ING_CTXT_PRIO_V(1U)
288
289#define ERR_EGR_CTXT_PRIO_S 9
290#define ERR_EGR_CTXT_PRIO_V(x) ((x) << ERR_EGR_CTXT_PRIO_S)
291#define ERR_EGR_CTXT_PRIO_F ERR_EGR_CTXT_PRIO_V(1U)
292
293#define DBFIFO_HP_INT_S 8
294#define DBFIFO_HP_INT_V(x) ((x) << DBFIFO_HP_INT_S)
295#define DBFIFO_HP_INT_F DBFIFO_HP_INT_V(1U)
296
297#define DBFIFO_LP_INT_S 7
298#define DBFIFO_LP_INT_V(x) ((x) << DBFIFO_LP_INT_S)
299#define DBFIFO_LP_INT_F DBFIFO_LP_INT_V(1U)
300
301#define INGRESS_SIZE_ERR_S 5
302#define INGRESS_SIZE_ERR_V(x) ((x) << INGRESS_SIZE_ERR_S)
303#define INGRESS_SIZE_ERR_F INGRESS_SIZE_ERR_V(1U)
304
305#define EGRESS_SIZE_ERR_S 4
306#define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S)
307#define EGRESS_SIZE_ERR_F EGRESS_SIZE_ERR_V(1U)
308
309#define SGE_INT_ENABLE3_A 0x1040
310#define SGE_FL_BUFFER_SIZE0_A 0x1044
311#define SGE_FL_BUFFER_SIZE1_A 0x1048
312#define SGE_FL_BUFFER_SIZE2_A 0x104c
313#define SGE_FL_BUFFER_SIZE3_A 0x1050
314#define SGE_FL_BUFFER_SIZE4_A 0x1054
315#define SGE_FL_BUFFER_SIZE5_A 0x1058
316#define SGE_FL_BUFFER_SIZE6_A 0x105c
317#define SGE_FL_BUFFER_SIZE7_A 0x1060
318#define SGE_FL_BUFFER_SIZE8_A 0x1064
319
320#define SGE_IMSG_CTXT_BADDR_A 0x1088
321#define SGE_FLM_CACHE_BADDR_A 0x108c
322#define SGE_INGRESS_RX_THRESHOLD_A 0x10a0
323
324#define THRESHOLD_0_S 24
325#define THRESHOLD_0_M 0x3fU
326#define THRESHOLD_0_V(x) ((x) << THRESHOLD_0_S)
327#define THRESHOLD_0_G(x) (((x) >> THRESHOLD_0_S) & THRESHOLD_0_M)
328
329#define THRESHOLD_1_S 16
330#define THRESHOLD_1_M 0x3fU
331#define THRESHOLD_1_V(x) ((x) << THRESHOLD_1_S)
332#define THRESHOLD_1_G(x) (((x) >> THRESHOLD_1_S) & THRESHOLD_1_M)
333
334#define THRESHOLD_2_S 8
335#define THRESHOLD_2_M 0x3fU
336#define THRESHOLD_2_V(x) ((x) << THRESHOLD_2_S)
337#define THRESHOLD_2_G(x) (((x) >> THRESHOLD_2_S) & THRESHOLD_2_M)
338
339#define THRESHOLD_3_S 0
340#define THRESHOLD_3_M 0x3fU
341#define THRESHOLD_3_V(x) ((x) << THRESHOLD_3_S)
342#define THRESHOLD_3_G(x) (((x) >> THRESHOLD_3_S) & THRESHOLD_3_M)
343
344#define SGE_CONM_CTRL_A 0x1094
345
346#define EGRTHRESHOLD_S 8
347#define EGRTHRESHOLD_M 0x3fU
348#define EGRTHRESHOLD_V(x) ((x) << EGRTHRESHOLD_S)
349#define EGRTHRESHOLD_G(x) (((x) >> EGRTHRESHOLD_S) & EGRTHRESHOLD_M)
350
351#define EGRTHRESHOLDPACKING_S 14
352#define EGRTHRESHOLDPACKING_M 0x3fU
353#define EGRTHRESHOLDPACKING_V(x) ((x) << EGRTHRESHOLDPACKING_S)
354#define EGRTHRESHOLDPACKING_G(x) \
355 (((x) >> EGRTHRESHOLDPACKING_S) & EGRTHRESHOLDPACKING_M)
356
357#define T6_EGRTHRESHOLDPACKING_S 16
358#define T6_EGRTHRESHOLDPACKING_M 0xffU
359#define T6_EGRTHRESHOLDPACKING_G(x) \
360 (((x) >> T6_EGRTHRESHOLDPACKING_S) & T6_EGRTHRESHOLDPACKING_M)
361
362#define SGE_TIMESTAMP_LO_A 0x1098
363#define SGE_TIMESTAMP_HI_A 0x109c
364
365#define TSOP_S 28
366#define TSOP_M 0x3U
367#define TSOP_V(x) ((x) << TSOP_S)
368#define TSOP_G(x) (((x) >> TSOP_S) & TSOP_M)
369
370#define TSVAL_S 0
371#define TSVAL_M 0xfffffffU
372#define TSVAL_V(x) ((x) << TSVAL_S)
373#define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M)
374
375#define SGE_DBFIFO_STATUS_A 0x10a4
376#define SGE_DBVFIFO_SIZE_A 0x113c
377
378#define HP_INT_THRESH_S 28
379#define HP_INT_THRESH_M 0xfU
380#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
381
382#define LP_INT_THRESH_S 12
383#define LP_INT_THRESH_M 0xfU
384#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
385
386#define SGE_DOORBELL_CONTROL_A 0x10a8
387
388#define NOCOALESCE_S 26
389#define NOCOALESCE_V(x) ((x) << NOCOALESCE_S)
390#define NOCOALESCE_F NOCOALESCE_V(1U)
391
392#define ENABLE_DROP_S 13
393#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
394#define ENABLE_DROP_F ENABLE_DROP_V(1U)
395
396#define SGE_TIMER_VALUE_0_AND_1_A 0x10b8
397
398#define TIMERVALUE0_S 16
399#define TIMERVALUE0_M 0xffffU
400#define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S)
401#define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M)
402
403#define TIMERVALUE1_S 0
404#define TIMERVALUE1_M 0xffffU
405#define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S)
406#define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M)
407
408#define SGE_TIMER_VALUE_2_AND_3_A 0x10bc
409
410#define TIMERVALUE2_S 16
411#define TIMERVALUE2_M 0xffffU
412#define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S)
413#define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M)
414
415#define TIMERVALUE3_S 0
416#define TIMERVALUE3_M 0xffffU
417#define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S)
418#define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M)
419
420#define SGE_TIMER_VALUE_4_AND_5_A 0x10c0
421
422#define TIMERVALUE4_S 16
423#define TIMERVALUE4_M 0xffffU
424#define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S)
425#define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M)
426
427#define TIMERVALUE5_S 0
428#define TIMERVALUE5_M 0xffffU
429#define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S)
430#define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M)
431
432#define SGE_DEBUG_INDEX_A 0x10cc
433#define SGE_DEBUG_DATA_HIGH_A 0x10d0
434#define SGE_DEBUG_DATA_LOW_A 0x10d4
435
436#define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8
437#define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc
438#define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8
439
440#define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4
441#define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
442
443#define SGE_ERROR_STATS_A 0x1100
444
445#define UNCAPTURED_ERROR_S 18
446#define UNCAPTURED_ERROR_V(x) ((x) << UNCAPTURED_ERROR_S)
447#define UNCAPTURED_ERROR_F UNCAPTURED_ERROR_V(1U)
448
449#define ERROR_QID_VALID_S 17
450#define ERROR_QID_VALID_V(x) ((x) << ERROR_QID_VALID_S)
451#define ERROR_QID_VALID_F ERROR_QID_VALID_V(1U)
452
453#define ERROR_QID_S 0
454#define ERROR_QID_M 0x1ffffU
455#define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M)
456
457#define HP_INT_THRESH_S 28
458#define HP_INT_THRESH_M 0xfU
459#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
460
461#define HP_COUNT_S 16
462#define HP_COUNT_M 0x7ffU
463#define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M)
464
465#define LP_INT_THRESH_S 12
466#define LP_INT_THRESH_M 0xfU
467#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
468
469#define LP_COUNT_S 0
470#define LP_COUNT_M 0x7ffU
471#define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M)
472
473#define LP_INT_THRESH_T5_S 18
474#define LP_INT_THRESH_T5_M 0xfffU
475#define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S)
476
477#define LP_COUNT_T5_S 0
478#define LP_COUNT_T5_M 0x3ffffU
479#define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M)
480
481#define SGE_DOORBELL_CONTROL_A 0x10a8
482
483#define SGE_STAT_TOTAL_A 0x10e4
484#define SGE_STAT_MATCH_A 0x10e8
485#define SGE_STAT_CFG_A 0x10ec
486
487#define STATMODE_S 2
488#define STATMODE_V(x) ((x) << STATMODE_S)
489
490#define STATSOURCE_T5_S 9
491#define STATSOURCE_T5_M 0xfU
492#define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S)
493#define STATSOURCE_T5_G(x) (((x) >> STATSOURCE_T5_S) & STATSOURCE_T5_M)
494
495#define SGE_DBFIFO_STATUS2_A 0x1118
496
497#define HP_INT_THRESH_T5_S 10
498#define HP_INT_THRESH_T5_M 0xfU
499#define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S)
500
501#define HP_COUNT_T5_S 0
502#define HP_COUNT_T5_M 0x3ffU
503#define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M)
504
505#define ENABLE_DROP_S 13
506#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
507#define ENABLE_DROP_F ENABLE_DROP_V(1U)
508
509#define DROPPED_DB_S 0
510#define DROPPED_DB_V(x) ((x) << DROPPED_DB_S)
511#define DROPPED_DB_F DROPPED_DB_V(1U)
512
513#define SGE_CTXT_CMD_A 0x11fc
514#define SGE_DBQ_CTXT_BADDR_A 0x1084
515
516
517#define PCIE_PF_CFG_A 0x40
518
519#define AIVEC_S 4
520#define AIVEC_M 0x3ffU
521#define AIVEC_V(x) ((x) << AIVEC_S)
522
523#define PCIE_PF_CLI_A 0x44
524#define PCIE_INT_CAUSE_A 0x3004
525
526#define UNXSPLCPLERR_S 29
527#define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S)
528#define UNXSPLCPLERR_F UNXSPLCPLERR_V(1U)
529
530#define PCIEPINT_S 28
531#define PCIEPINT_V(x) ((x) << PCIEPINT_S)
532#define PCIEPINT_F PCIEPINT_V(1U)
533
534#define PCIESINT_S 27
535#define PCIESINT_V(x) ((x) << PCIESINT_S)
536#define PCIESINT_F PCIESINT_V(1U)
537
538#define RPLPERR_S 26
539#define RPLPERR_V(x) ((x) << RPLPERR_S)
540#define RPLPERR_F RPLPERR_V(1U)
541
542#define RXWRPERR_S 25
543#define RXWRPERR_V(x) ((x) << RXWRPERR_S)
544#define RXWRPERR_F RXWRPERR_V(1U)
545
546#define RXCPLPERR_S 24
547#define RXCPLPERR_V(x) ((x) << RXCPLPERR_S)
548#define RXCPLPERR_F RXCPLPERR_V(1U)
549
550#define PIOTAGPERR_S 23
551#define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S)
552#define PIOTAGPERR_F PIOTAGPERR_V(1U)
553
554#define MATAGPERR_S 22
555#define MATAGPERR_V(x) ((x) << MATAGPERR_S)
556#define MATAGPERR_F MATAGPERR_V(1U)
557
558#define INTXCLRPERR_S 21
559#define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S)
560#define INTXCLRPERR_F INTXCLRPERR_V(1U)
561
562#define FIDPERR_S 20
563#define FIDPERR_V(x) ((x) << FIDPERR_S)
564#define FIDPERR_F FIDPERR_V(1U)
565
566#define CFGSNPPERR_S 19
567#define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S)
568#define CFGSNPPERR_F CFGSNPPERR_V(1U)
569
570#define HRSPPERR_S 18
571#define HRSPPERR_V(x) ((x) << HRSPPERR_S)
572#define HRSPPERR_F HRSPPERR_V(1U)
573
574#define HREQPERR_S 17
575#define HREQPERR_V(x) ((x) << HREQPERR_S)
576#define HREQPERR_F HREQPERR_V(1U)
577
578#define HCNTPERR_S 16
579#define HCNTPERR_V(x) ((x) << HCNTPERR_S)
580#define HCNTPERR_F HCNTPERR_V(1U)
581
582#define DRSPPERR_S 15
583#define DRSPPERR_V(x) ((x) << DRSPPERR_S)
584#define DRSPPERR_F DRSPPERR_V(1U)
585
586#define DREQPERR_S 14
587#define DREQPERR_V(x) ((x) << DREQPERR_S)
588#define DREQPERR_F DREQPERR_V(1U)
589
590#define DCNTPERR_S 13
591#define DCNTPERR_V(x) ((x) << DCNTPERR_S)
592#define DCNTPERR_F DCNTPERR_V(1U)
593
594#define CRSPPERR_S 12
595#define CRSPPERR_V(x) ((x) << CRSPPERR_S)
596#define CRSPPERR_F CRSPPERR_V(1U)
597
598#define CREQPERR_S 11
599#define CREQPERR_V(x) ((x) << CREQPERR_S)
600#define CREQPERR_F CREQPERR_V(1U)
601
602#define CCNTPERR_S 10
603#define CCNTPERR_V(x) ((x) << CCNTPERR_S)
604#define CCNTPERR_F CCNTPERR_V(1U)
605
606#define TARTAGPERR_S 9
607#define TARTAGPERR_V(x) ((x) << TARTAGPERR_S)
608#define TARTAGPERR_F TARTAGPERR_V(1U)
609
610#define PIOREQPERR_S 8
611#define PIOREQPERR_V(x) ((x) << PIOREQPERR_S)
612#define PIOREQPERR_F PIOREQPERR_V(1U)
613
614#define PIOCPLPERR_S 7
615#define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S)
616#define PIOCPLPERR_F PIOCPLPERR_V(1U)
617
618#define MSIXDIPERR_S 6
619#define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S)
620#define MSIXDIPERR_F MSIXDIPERR_V(1U)
621
622#define MSIXDATAPERR_S 5
623#define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S)
624#define MSIXDATAPERR_F MSIXDATAPERR_V(1U)
625
626#define MSIXADDRHPERR_S 4
627#define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S)
628#define MSIXADDRHPERR_F MSIXADDRHPERR_V(1U)
629
630#define MSIXADDRLPERR_S 3
631#define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S)
632#define MSIXADDRLPERR_F MSIXADDRLPERR_V(1U)
633
634#define MSIDATAPERR_S 2
635#define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S)
636#define MSIDATAPERR_F MSIDATAPERR_V(1U)
637
638#define MSIADDRHPERR_S 1
639#define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S)
640#define MSIADDRHPERR_F MSIADDRHPERR_V(1U)
641
642#define MSIADDRLPERR_S 0
643#define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S)
644#define MSIADDRLPERR_F MSIADDRLPERR_V(1U)
645
646#define READRSPERR_S 29
647#define READRSPERR_V(x) ((x) << READRSPERR_S)
648#define READRSPERR_F READRSPERR_V(1U)
649
650#define TRGT1GRPPERR_S 28
651#define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S)
652#define TRGT1GRPPERR_F TRGT1GRPPERR_V(1U)
653
654#define IPSOTPERR_S 27
655#define IPSOTPERR_V(x) ((x) << IPSOTPERR_S)
656#define IPSOTPERR_F IPSOTPERR_V(1U)
657
658#define IPRETRYPERR_S 26
659#define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S)
660#define IPRETRYPERR_F IPRETRYPERR_V(1U)
661
662#define IPRXDATAGRPPERR_S 25
663#define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S)
664#define IPRXDATAGRPPERR_F IPRXDATAGRPPERR_V(1U)
665
666#define IPRXHDRGRPPERR_S 24
667#define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S)
668#define IPRXHDRGRPPERR_F IPRXHDRGRPPERR_V(1U)
669
670#define MAGRPPERR_S 22
671#define MAGRPPERR_V(x) ((x) << MAGRPPERR_S)
672#define MAGRPPERR_F MAGRPPERR_V(1U)
673
674#define VFIDPERR_S 21
675#define VFIDPERR_V(x) ((x) << VFIDPERR_S)
676#define VFIDPERR_F VFIDPERR_V(1U)
677
678#define HREQWRPERR_S 16
679#define HREQWRPERR_V(x) ((x) << HREQWRPERR_S)
680#define HREQWRPERR_F HREQWRPERR_V(1U)
681
682#define DREQWRPERR_S 13
683#define DREQWRPERR_V(x) ((x) << DREQWRPERR_S)
684#define DREQWRPERR_F DREQWRPERR_V(1U)
685
686#define CREQRDPERR_S 11
687#define CREQRDPERR_V(x) ((x) << CREQRDPERR_S)
688#define CREQRDPERR_F CREQRDPERR_V(1U)
689
690#define MSTTAGQPERR_S 10
691#define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S)
692#define MSTTAGQPERR_F MSTTAGQPERR_V(1U)
693
694#define PIOREQGRPPERR_S 8
695#define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S)
696#define PIOREQGRPPERR_F PIOREQGRPPERR_V(1U)
697
698#define PIOCPLGRPPERR_S 7
699#define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S)
700#define PIOCPLGRPPERR_F PIOCPLGRPPERR_V(1U)
701
702#define MSIXSTIPERR_S 2
703#define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S)
704#define MSIXSTIPERR_F MSIXSTIPERR_V(1U)
705
706#define MSTTIMEOUTPERR_S 1
707#define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S)
708#define MSTTIMEOUTPERR_F MSTTIMEOUTPERR_V(1U)
709
710#define MSTGRPPERR_S 0
711#define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S)
712#define MSTGRPPERR_F MSTGRPPERR_V(1U)
713
714#define PCIE_NONFAT_ERR_A 0x3010
715#define PCIE_CFG_SPACE_REQ_A 0x3060
716#define PCIE_CFG_SPACE_DATA_A 0x3064
717#define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
718
719#define PCIEOFST_S 10
720#define PCIEOFST_M 0x3fffffU
721#define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M)
722
723#define BIR_S 8
724#define BIR_M 0x3U
725#define BIR_V(x) ((x) << BIR_S)
726#define BIR_G(x) (((x) >> BIR_S) & BIR_M)
727
728#define WINDOW_S 0
729#define WINDOW_M 0xffU
730#define WINDOW_V(x) ((x) << WINDOW_S)
731#define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M)
732
733#define PCIE_MEM_ACCESS_OFFSET_A 0x306c
734
735#define ENABLE_S 30
736#define ENABLE_V(x) ((x) << ENABLE_S)
737#define ENABLE_F ENABLE_V(1U)
738
739#define LOCALCFG_S 28
740#define LOCALCFG_V(x) ((x) << LOCALCFG_S)
741#define LOCALCFG_F LOCALCFG_V(1U)
742
743#define FUNCTION_S 12
744#define FUNCTION_V(x) ((x) << FUNCTION_S)
745
746#define REGISTER_S 0
747#define REGISTER_V(x) ((x) << REGISTER_S)
748
749#define T6_ENABLE_S 31
750#define T6_ENABLE_V(x) ((x) << T6_ENABLE_S)
751#define T6_ENABLE_F T6_ENABLE_V(1U)
752
753#define PFNUM_S 0
754#define PFNUM_V(x) ((x) << PFNUM_S)
755
756#define PCIE_FW_A 0x30b8
757#define PCIE_FW_PF_A 0x30bc
758
759#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908
760
761#define RNPP_S 31
762#define RNPP_V(x) ((x) << RNPP_S)
763#define RNPP_F RNPP_V(1U)
764
765#define RPCP_S 29
766#define RPCP_V(x) ((x) << RPCP_S)
767#define RPCP_F RPCP_V(1U)
768
769#define RCIP_S 27
770#define RCIP_V(x) ((x) << RCIP_S)
771#define RCIP_F RCIP_V(1U)
772
773#define RCCP_S 26
774#define RCCP_V(x) ((x) << RCCP_S)
775#define RCCP_F RCCP_V(1U)
776
777#define RFTP_S 23
778#define RFTP_V(x) ((x) << RFTP_S)
779#define RFTP_F RFTP_V(1U)
780
781#define PTRP_S 20
782#define PTRP_V(x) ((x) << PTRP_S)
783#define PTRP_F PTRP_V(1U)
784
785#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4
786
787#define TPCP_S 30
788#define TPCP_V(x) ((x) << TPCP_S)
789#define TPCP_F TPCP_V(1U)
790
791#define TNPP_S 29
792#define TNPP_V(x) ((x) << TNPP_S)
793#define TNPP_F TNPP_V(1U)
794
795#define TFTP_S 28
796#define TFTP_V(x) ((x) << TFTP_S)
797#define TFTP_F TFTP_V(1U)
798
799#define TCAP_S 27
800#define TCAP_V(x) ((x) << TCAP_S)
801#define TCAP_F TCAP_V(1U)
802
803#define TCIP_S 26
804#define TCIP_V(x) ((x) << TCIP_S)
805#define TCIP_F TCIP_V(1U)
806
807#define RCAP_S 25
808#define RCAP_V(x) ((x) << RCAP_S)
809#define RCAP_F RCAP_V(1U)
810
811#define PLUP_S 23
812#define PLUP_V(x) ((x) << PLUP_S)
813#define PLUP_F PLUP_V(1U)
814
815#define PLDN_S 22
816#define PLDN_V(x) ((x) << PLDN_S)
817#define PLDN_F PLDN_V(1U)
818
819#define OTDD_S 21
820#define OTDD_V(x) ((x) << OTDD_S)
821#define OTDD_F OTDD_V(1U)
822
823#define GTRP_S 20
824#define GTRP_V(x) ((x) << GTRP_S)
825#define GTRP_F GTRP_V(1U)
826
827#define RDPE_S 18
828#define RDPE_V(x) ((x) << RDPE_S)
829#define RDPE_F RDPE_V(1U)
830
831#define TDCE_S 17
832#define TDCE_V(x) ((x) << TDCE_S)
833#define TDCE_F TDCE_V(1U)
834
835#define TDUE_S 16
836#define TDUE_V(x) ((x) << TDUE_S)
837#define TDUE_F TDUE_V(1U)
838
839
840#define MC_INT_CAUSE_A 0x7518
841#define MC_P_INT_CAUSE_A 0x41318
842
843#define ECC_UE_INT_CAUSE_S 2
844#define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S)
845#define ECC_UE_INT_CAUSE_F ECC_UE_INT_CAUSE_V(1U)
846
847#define ECC_CE_INT_CAUSE_S 1
848#define ECC_CE_INT_CAUSE_V(x) ((x) << ECC_CE_INT_CAUSE_S)
849#define ECC_CE_INT_CAUSE_F ECC_CE_INT_CAUSE_V(1U)
850
851#define PERR_INT_CAUSE_S 0
852#define PERR_INT_CAUSE_V(x) ((x) << PERR_INT_CAUSE_S)
853#define PERR_INT_CAUSE_F PERR_INT_CAUSE_V(1U)
854
855#define MC_ECC_STATUS_A 0x751c
856#define MC_P_ECC_STATUS_A 0x4131c
857
858#define ECC_CECNT_S 16
859#define ECC_CECNT_M 0xffffU
860#define ECC_CECNT_V(x) ((x) << ECC_CECNT_S)
861#define ECC_CECNT_G(x) (((x) >> ECC_CECNT_S) & ECC_CECNT_M)
862
863#define ECC_UECNT_S 0
864#define ECC_UECNT_M 0xffffU
865#define ECC_UECNT_V(x) ((x) << ECC_UECNT_S)
866#define ECC_UECNT_G(x) (((x) >> ECC_UECNT_S) & ECC_UECNT_M)
867
868#define MC_BIST_CMD_A 0x7600
869
870#define START_BIST_S 31
871#define START_BIST_V(x) ((x) << START_BIST_S)
872#define START_BIST_F START_BIST_V(1U)
873
874#define BIST_CMD_GAP_S 8
875#define BIST_CMD_GAP_V(x) ((x) << BIST_CMD_GAP_S)
876
877#define BIST_OPCODE_S 0
878#define BIST_OPCODE_V(x) ((x) << BIST_OPCODE_S)
879
880#define MC_BIST_CMD_ADDR_A 0x7604
881#define MC_BIST_CMD_LEN_A 0x7608
882#define MC_BIST_DATA_PATTERN_A 0x760c
883
884#define MC_BIST_STATUS_RDATA_A 0x7688
885
886
887#define MA_EDRAM0_BAR_A 0x77c0
888
889#define EDRAM0_BASE_S 16
890#define EDRAM0_BASE_M 0xfffU
891#define EDRAM0_BASE_G(x) (((x) >> EDRAM0_BASE_S) & EDRAM0_BASE_M)
892
893#define EDRAM0_SIZE_S 0
894#define EDRAM0_SIZE_M 0xfffU
895#define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)
896#define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)
897
898#define MA_EDRAM1_BAR_A 0x77c4
899
900#define EDRAM1_BASE_S 16
901#define EDRAM1_BASE_M 0xfffU
902#define EDRAM1_BASE_G(x) (((x) >> EDRAM1_BASE_S) & EDRAM1_BASE_M)
903
904#define EDRAM1_SIZE_S 0
905#define EDRAM1_SIZE_M 0xfffU
906#define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)
907#define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)
908
909#define MA_EXT_MEMORY_BAR_A 0x77c8
910
911#define EXT_MEM_BASE_S 16
912#define EXT_MEM_BASE_M 0xfffU
913#define EXT_MEM_BASE_V(x) ((x) << EXT_MEM_BASE_S)
914#define EXT_MEM_BASE_G(x) (((x) >> EXT_MEM_BASE_S) & EXT_MEM_BASE_M)
915
916#define EXT_MEM_SIZE_S 0
917#define EXT_MEM_SIZE_M 0xfffU
918#define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S)
919#define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M)
920
921#define MA_EXT_MEMORY1_BAR_A 0x7808
922
923#define EXT_MEM1_BASE_S 16
924#define EXT_MEM1_BASE_M 0xfffU
925#define EXT_MEM1_BASE_G(x) (((x) >> EXT_MEM1_BASE_S) & EXT_MEM1_BASE_M)
926
927#define EXT_MEM1_SIZE_S 0
928#define EXT_MEM1_SIZE_M 0xfffU
929#define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)
930#define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)
931
932#define MA_EXT_MEMORY0_BAR_A 0x77c8
933
934#define EXT_MEM0_BASE_S 16
935#define EXT_MEM0_BASE_M 0xfffU
936#define EXT_MEM0_BASE_G(x) (((x) >> EXT_MEM0_BASE_S) & EXT_MEM0_BASE_M)
937
938#define EXT_MEM0_SIZE_S 0
939#define EXT_MEM0_SIZE_M 0xfffU
940#define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)
941#define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)
942
943#define MA_TARGET_MEM_ENABLE_A 0x77d8
944
945#define EXT_MEM_ENABLE_S 2
946#define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S)
947#define EXT_MEM_ENABLE_F EXT_MEM_ENABLE_V(1U)
948
949#define EDRAM1_ENABLE_S 1
950#define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S)
951#define EDRAM1_ENABLE_F EDRAM1_ENABLE_V(1U)
952
953#define EDRAM0_ENABLE_S 0
954#define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S)
955#define EDRAM0_ENABLE_F EDRAM0_ENABLE_V(1U)
956
957#define EXT_MEM1_ENABLE_S 4
958#define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S)
959#define EXT_MEM1_ENABLE_F EXT_MEM1_ENABLE_V(1U)
960
961#define EXT_MEM0_ENABLE_S 2
962#define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
963#define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U)
964
965#define MA_INT_CAUSE_A 0x77e0
966
967#define MEM_PERR_INT_CAUSE_S 1
968#define MEM_PERR_INT_CAUSE_V(x) ((x) << MEM_PERR_INT_CAUSE_S)
969#define MEM_PERR_INT_CAUSE_F MEM_PERR_INT_CAUSE_V(1U)
970
971#define MEM_WRAP_INT_CAUSE_S 0
972#define MEM_WRAP_INT_CAUSE_V(x) ((x) << MEM_WRAP_INT_CAUSE_S)
973#define MEM_WRAP_INT_CAUSE_F MEM_WRAP_INT_CAUSE_V(1U)
974
975#define MA_INT_WRAP_STATUS_A 0x77e4
976
977#define MEM_WRAP_ADDRESS_S 4
978#define MEM_WRAP_ADDRESS_M 0xfffffffU
979#define MEM_WRAP_ADDRESS_G(x) (((x) >> MEM_WRAP_ADDRESS_S) & MEM_WRAP_ADDRESS_M)
980
981#define MEM_WRAP_CLIENT_NUM_S 0
982#define MEM_WRAP_CLIENT_NUM_M 0xfU
983#define MEM_WRAP_CLIENT_NUM_G(x) \
984 (((x) >> MEM_WRAP_CLIENT_NUM_S) & MEM_WRAP_CLIENT_NUM_M)
985
986#define MA_PARITY_ERROR_STATUS_A 0x77f4
987#define MA_PARITY_ERROR_STATUS1_A 0x77f4
988#define MA_PARITY_ERROR_STATUS2_A 0x7804
989
990
991#define EDC_0_BASE_ADDR 0x7900
992
993#define EDC_BIST_CMD_A 0x7904
994#define EDC_BIST_CMD_ADDR_A 0x7908
995#define EDC_BIST_CMD_LEN_A 0x790c
996#define EDC_BIST_DATA_PATTERN_A 0x7910
997#define EDC_BIST_STATUS_RDATA_A 0x7928
998#define EDC_INT_CAUSE_A 0x7978
999
1000#define ECC_UE_PAR_S 5
1001#define ECC_UE_PAR_V(x) ((x) << ECC_UE_PAR_S)
1002#define ECC_UE_PAR_F ECC_UE_PAR_V(1U)
1003
1004#define ECC_CE_PAR_S 4
1005#define ECC_CE_PAR_V(x) ((x) << ECC_CE_PAR_S)
1006#define ECC_CE_PAR_F ECC_CE_PAR_V(1U)
1007
1008#define PERR_PAR_CAUSE_S 3
1009#define PERR_PAR_CAUSE_V(x) ((x) << PERR_PAR_CAUSE_S)
1010#define PERR_PAR_CAUSE_F PERR_PAR_CAUSE_V(1U)
1011
1012#define EDC_ECC_STATUS_A 0x797c
1013
1014
1015#define EDC_1_BASE_ADDR 0x7980
1016
1017
1018#define CIM_BOOT_CFG_A 0x7b00
1019#define CIM_SDRAM_BASE_ADDR_A 0x7b14
1020#define CIM_SDRAM_ADDR_SIZE_A 0x7b18
1021#define CIM_EXTMEM2_BASE_ADDR_A 0x7b1c
1022#define CIM_EXTMEM2_ADDR_SIZE_A 0x7b20
1023#define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x290
1024
1025#define BOOTADDR_M 0xffffff00U
1026
1027#define UPCRST_S 0
1028#define UPCRST_V(x) ((x) << UPCRST_S)
1029#define UPCRST_F UPCRST_V(1U)
1030
1031#define CIM_PF_MAILBOX_DATA_A 0x240
1032#define CIM_PF_MAILBOX_CTRL_A 0x280
1033
1034#define MBMSGVALID_S 3
1035#define MBMSGVALID_V(x) ((x) << MBMSGVALID_S)
1036#define MBMSGVALID_F MBMSGVALID_V(1U)
1037
1038#define MBINTREQ_S 2
1039#define MBINTREQ_V(x) ((x) << MBINTREQ_S)
1040#define MBINTREQ_F MBINTREQ_V(1U)
1041
1042#define MBOWNER_S 0
1043#define MBOWNER_M 0x3U
1044#define MBOWNER_V(x) ((x) << MBOWNER_S)
1045#define MBOWNER_G(x) (((x) >> MBOWNER_S) & MBOWNER_M)
1046
1047#define CIM_PF_HOST_INT_ENABLE_A 0x288
1048
1049#define MBMSGRDYINTEN_S 19
1050#define MBMSGRDYINTEN_V(x) ((x) << MBMSGRDYINTEN_S)
1051#define MBMSGRDYINTEN_F MBMSGRDYINTEN_V(1U)
1052
1053#define CIM_PF_HOST_INT_CAUSE_A 0x28c
1054
1055#define MBMSGRDYINT_S 19
1056#define MBMSGRDYINT_V(x) ((x) << MBMSGRDYINT_S)
1057#define MBMSGRDYINT_F MBMSGRDYINT_V(1U)
1058
1059#define CIM_HOST_INT_CAUSE_A 0x7b2c
1060
1061#define TIEQOUTPARERRINT_S 20
1062#define TIEQOUTPARERRINT_V(x) ((x) << TIEQOUTPARERRINT_S)
1063#define TIEQOUTPARERRINT_F TIEQOUTPARERRINT_V(1U)
1064
1065#define TIEQINPARERRINT_S 19
1066#define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S)
1067#define TIEQINPARERRINT_F TIEQINPARERRINT_V(1U)
1068
1069#define PREFDROPINT_S 1
1070#define PREFDROPINT_V(x) ((x) << PREFDROPINT_S)
1071#define PREFDROPINT_F PREFDROPINT_V(1U)
1072
1073#define UPACCNONZERO_S 0
1074#define UPACCNONZERO_V(x) ((x) << UPACCNONZERO_S)
1075#define UPACCNONZERO_F UPACCNONZERO_V(1U)
1076
1077#define MBHOSTPARERR_S 18
1078#define MBHOSTPARERR_V(x) ((x) << MBHOSTPARERR_S)
1079#define MBHOSTPARERR_F MBHOSTPARERR_V(1U)
1080
1081#define MBUPPARERR_S 17
1082#define MBUPPARERR_V(x) ((x) << MBUPPARERR_S)
1083#define MBUPPARERR_F MBUPPARERR_V(1U)
1084
1085#define IBQTP0PARERR_S 16
1086#define IBQTP0PARERR_V(x) ((x) << IBQTP0PARERR_S)
1087#define IBQTP0PARERR_F IBQTP0PARERR_V(1U)
1088
1089#define IBQTP1PARERR_S 15
1090#define IBQTP1PARERR_V(x) ((x) << IBQTP1PARERR_S)
1091#define IBQTP1PARERR_F IBQTP1PARERR_V(1U)
1092
1093#define IBQULPPARERR_S 14
1094#define IBQULPPARERR_V(x) ((x) << IBQULPPARERR_S)
1095#define IBQULPPARERR_F IBQULPPARERR_V(1U)
1096
1097#define IBQSGELOPARERR_S 13
1098#define IBQSGELOPARERR_V(x) ((x) << IBQSGELOPARERR_S)
1099#define IBQSGELOPARERR_F IBQSGELOPARERR_V(1U)
1100
1101#define IBQSGEHIPARERR_S 12
1102#define IBQSGEHIPARERR_V(x) ((x) << IBQSGEHIPARERR_S)
1103#define IBQSGEHIPARERR_F IBQSGEHIPARERR_V(1U)
1104
1105#define IBQNCSIPARERR_S 11
1106#define IBQNCSIPARERR_V(x) ((x) << IBQNCSIPARERR_S)
1107#define IBQNCSIPARERR_F IBQNCSIPARERR_V(1U)
1108
1109#define OBQULP0PARERR_S 10
1110#define OBQULP0PARERR_V(x) ((x) << OBQULP0PARERR_S)
1111#define OBQULP0PARERR_F OBQULP0PARERR_V(1U)
1112
1113#define OBQULP1PARERR_S 9
1114#define OBQULP1PARERR_V(x) ((x) << OBQULP1PARERR_S)
1115#define OBQULP1PARERR_F OBQULP1PARERR_V(1U)
1116
1117#define OBQULP2PARERR_S 8
1118#define OBQULP2PARERR_V(x) ((x) << OBQULP2PARERR_S)
1119#define OBQULP2PARERR_F OBQULP2PARERR_V(1U)
1120
1121#define OBQULP3PARERR_S 7
1122#define OBQULP3PARERR_V(x) ((x) << OBQULP3PARERR_S)
1123#define OBQULP3PARERR_F OBQULP3PARERR_V(1U)
1124
1125#define OBQSGEPARERR_S 6
1126#define OBQSGEPARERR_V(x) ((x) << OBQSGEPARERR_S)
1127#define OBQSGEPARERR_F OBQSGEPARERR_V(1U)
1128
1129#define OBQNCSIPARERR_S 5
1130#define OBQNCSIPARERR_V(x) ((x) << OBQNCSIPARERR_S)
1131#define OBQNCSIPARERR_F OBQNCSIPARERR_V(1U)
1132
1133#define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34
1134
1135#define EEPROMWRINT_S 30
1136#define EEPROMWRINT_V(x) ((x) << EEPROMWRINT_S)
1137#define EEPROMWRINT_F EEPROMWRINT_V(1U)
1138
1139#define TIMEOUTMAINT_S 29
1140#define TIMEOUTMAINT_V(x) ((x) << TIMEOUTMAINT_S)
1141#define TIMEOUTMAINT_F TIMEOUTMAINT_V(1U)
1142
1143#define TIMEOUTINT_S 28
1144#define TIMEOUTINT_V(x) ((x) << TIMEOUTINT_S)
1145#define TIMEOUTINT_F TIMEOUTINT_V(1U)
1146
1147#define RSPOVRLOOKUPINT_S 27
1148#define RSPOVRLOOKUPINT_V(x) ((x) << RSPOVRLOOKUPINT_S)
1149#define RSPOVRLOOKUPINT_F RSPOVRLOOKUPINT_V(1U)
1150
1151#define REQOVRLOOKUPINT_S 26
1152#define REQOVRLOOKUPINT_V(x) ((x) << REQOVRLOOKUPINT_S)
1153#define REQOVRLOOKUPINT_F REQOVRLOOKUPINT_V(1U)
1154
1155#define BLKWRPLINT_S 25
1156#define BLKWRPLINT_V(x) ((x) << BLKWRPLINT_S)
1157#define BLKWRPLINT_F BLKWRPLINT_V(1U)
1158
1159#define BLKRDPLINT_S 24
1160#define BLKRDPLINT_V(x) ((x) << BLKRDPLINT_S)
1161#define BLKRDPLINT_F BLKRDPLINT_V(1U)
1162
1163#define SGLWRPLINT_S 23
1164#define SGLWRPLINT_V(x) ((x) << SGLWRPLINT_S)
1165#define SGLWRPLINT_F SGLWRPLINT_V(1U)
1166
1167#define SGLRDPLINT_S 22
1168#define SGLRDPLINT_V(x) ((x) << SGLRDPLINT_S)
1169#define SGLRDPLINT_F SGLRDPLINT_V(1U)
1170
1171#define BLKWRCTLINT_S 21
1172#define BLKWRCTLINT_V(x) ((x) << BLKWRCTLINT_S)
1173#define BLKWRCTLINT_F BLKWRCTLINT_V(1U)
1174
1175#define BLKRDCTLINT_S 20
1176#define BLKRDCTLINT_V(x) ((x) << BLKRDCTLINT_S)
1177#define BLKRDCTLINT_F BLKRDCTLINT_V(1U)
1178
1179#define SGLWRCTLINT_S 19
1180#define SGLWRCTLINT_V(x) ((x) << SGLWRCTLINT_S)
1181#define SGLWRCTLINT_F SGLWRCTLINT_V(1U)
1182
1183#define SGLRDCTLINT_S 18
1184#define SGLRDCTLINT_V(x) ((x) << SGLRDCTLINT_S)
1185#define SGLRDCTLINT_F SGLRDCTLINT_V(1U)
1186
1187#define BLKWREEPROMINT_S 17
1188#define BLKWREEPROMINT_V(x) ((x) << BLKWREEPROMINT_S)
1189#define BLKWREEPROMINT_F BLKWREEPROMINT_V(1U)
1190
1191#define BLKRDEEPROMINT_S 16
1192#define BLKRDEEPROMINT_V(x) ((x) << BLKRDEEPROMINT_S)
1193#define BLKRDEEPROMINT_F BLKRDEEPROMINT_V(1U)
1194
1195#define SGLWREEPROMINT_S 15
1196#define SGLWREEPROMINT_V(x) ((x) << SGLWREEPROMINT_S)
1197#define SGLWREEPROMINT_F SGLWREEPROMINT_V(1U)
1198
1199#define SGLRDEEPROMINT_S 14
1200#define SGLRDEEPROMINT_V(x) ((x) << SGLRDEEPROMINT_S)
1201#define SGLRDEEPROMINT_F SGLRDEEPROMINT_V(1U)
1202
1203#define BLKWRFLASHINT_S 13
1204#define BLKWRFLASHINT_V(x) ((x) << BLKWRFLASHINT_S)
1205#define BLKWRFLASHINT_F BLKWRFLASHINT_V(1U)
1206
1207#define BLKRDFLASHINT_S 12
1208#define BLKRDFLASHINT_V(x) ((x) << BLKRDFLASHINT_S)
1209#define BLKRDFLASHINT_F BLKRDFLASHINT_V(1U)
1210
1211#define SGLWRFLASHINT_S 11
1212#define SGLWRFLASHINT_V(x) ((x) << SGLWRFLASHINT_S)
1213#define SGLWRFLASHINT_F SGLWRFLASHINT_V(1U)
1214
1215#define SGLRDFLASHINT_S 10
1216#define SGLRDFLASHINT_V(x) ((x) << SGLRDFLASHINT_S)
1217#define SGLRDFLASHINT_F SGLRDFLASHINT_V(1U)
1218
1219#define BLKWRBOOTINT_S 9
1220#define BLKWRBOOTINT_V(x) ((x) << BLKWRBOOTINT_S)
1221#define BLKWRBOOTINT_F BLKWRBOOTINT_V(1U)
1222
1223#define BLKRDBOOTINT_S 8
1224#define BLKRDBOOTINT_V(x) ((x) << BLKRDBOOTINT_S)
1225#define BLKRDBOOTINT_F BLKRDBOOTINT_V(1U)
1226
1227#define SGLWRBOOTINT_S 7
1228#define SGLWRBOOTINT_V(x) ((x) << SGLWRBOOTINT_S)
1229#define SGLWRBOOTINT_F SGLWRBOOTINT_V(1U)
1230
1231#define SGLRDBOOTINT_S 6
1232#define SGLRDBOOTINT_V(x) ((x) << SGLRDBOOTINT_S)
1233#define SGLRDBOOTINT_F SGLRDBOOTINT_V(1U)
1234
1235#define ILLWRBEINT_S 5
1236#define ILLWRBEINT_V(x) ((x) << ILLWRBEINT_S)
1237#define ILLWRBEINT_F ILLWRBEINT_V(1U)
1238
1239#define ILLRDBEINT_S 4
1240#define ILLRDBEINT_V(x) ((x) << ILLRDBEINT_S)
1241#define ILLRDBEINT_F ILLRDBEINT_V(1U)
1242
1243#define ILLRDINT_S 3
1244#define ILLRDINT_V(x) ((x) << ILLRDINT_S)
1245#define ILLRDINT_F ILLRDINT_V(1U)
1246
1247#define ILLWRINT_S 2
1248#define ILLWRINT_V(x) ((x) << ILLWRINT_S)
1249#define ILLWRINT_F ILLWRINT_V(1U)
1250
1251#define ILLTRANSINT_S 1
1252#define ILLTRANSINT_V(x) ((x) << ILLTRANSINT_S)
1253#define ILLTRANSINT_F ILLTRANSINT_V(1U)
1254
1255#define RSVDSPACEINT_S 0
1256#define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S)
1257#define RSVDSPACEINT_F RSVDSPACEINT_V(1U)
1258
1259
1260#define DBGLAWHLF_S 23
1261#define DBGLAWHLF_V(x) ((x) << DBGLAWHLF_S)
1262#define DBGLAWHLF_F DBGLAWHLF_V(1U)
1263
1264#define DBGLAWPTR_S 16
1265#define DBGLAWPTR_M 0x7fU
1266#define DBGLAWPTR_G(x) (((x) >> DBGLAWPTR_S) & DBGLAWPTR_M)
1267
1268#define DBGLAENABLE_S 12
1269#define DBGLAENABLE_V(x) ((x) << DBGLAENABLE_S)
1270#define DBGLAENABLE_F DBGLAENABLE_V(1U)
1271
1272#define DBGLARPTR_S 0
1273#define DBGLARPTR_M 0x7fU
1274#define DBGLARPTR_V(x) ((x) << DBGLARPTR_S)
1275
1276#define TP_DBG_LA_DATAL_A 0x7ed8
1277#define TP_DBG_LA_CONFIG_A 0x7ed4
1278#define TP_OUT_CONFIG_A 0x7d04
1279#define TP_GLOBAL_CONFIG_A 0x7d08
1280
1281#define TP_CMM_TCB_BASE_A 0x7d10
1282#define TP_CMM_MM_BASE_A 0x7d14
1283#define TP_CMM_TIMER_BASE_A 0x7d18
1284#define TP_PMM_TX_BASE_A 0x7d20
1285#define TP_PMM_RX_BASE_A 0x7d28
1286#define TP_PMM_RX_PAGE_SIZE_A 0x7d2c
1287#define TP_PMM_RX_MAX_PAGE_A 0x7d30
1288#define TP_PMM_TX_PAGE_SIZE_A 0x7d34
1289#define TP_PMM_TX_MAX_PAGE_A 0x7d38
1290#define TP_CMM_MM_MAX_PSTRUCT_A 0x7e6c
1291
1292#define PMRXNUMCHN_S 31
1293#define PMRXNUMCHN_V(x) ((x) << PMRXNUMCHN_S)
1294#define PMRXNUMCHN_F PMRXNUMCHN_V(1U)
1295
1296#define PMTXNUMCHN_S 30
1297#define PMTXNUMCHN_M 0x3U
1298#define PMTXNUMCHN_G(x) (((x) >> PMTXNUMCHN_S) & PMTXNUMCHN_M)
1299
1300#define PMTXMAXPAGE_S 0
1301#define PMTXMAXPAGE_M 0x1fffffU
1302#define PMTXMAXPAGE_G(x) (((x) >> PMTXMAXPAGE_S) & PMTXMAXPAGE_M)
1303
1304#define PMRXMAXPAGE_S 0
1305#define PMRXMAXPAGE_M 0x1fffffU
1306#define PMRXMAXPAGE_G(x) (((x) >> PMRXMAXPAGE_S) & PMRXMAXPAGE_M)
1307
1308#define DBGLAMODE_S 14
1309#define DBGLAMODE_M 0x3U
1310#define DBGLAMODE_G(x) (((x) >> DBGLAMODE_S) & DBGLAMODE_M)
1311
1312#define FIVETUPLELOOKUP_S 17
1313#define FIVETUPLELOOKUP_M 0x3U
1314#define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S)
1315#define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M)
1316
1317#define TP_PARA_REG2_A 0x7d68
1318
1319#define MAXRXDATA_S 16
1320#define MAXRXDATA_M 0xffffU
1321#define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M)
1322
1323#define TP_TIMER_RESOLUTION_A 0x7d90
1324
1325#define TIMERRESOLUTION_S 16
1326#define TIMERRESOLUTION_M 0xffU
1327#define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M)
1328
1329#define TIMESTAMPRESOLUTION_S 8
1330#define TIMESTAMPRESOLUTION_M 0xffU
1331#define TIMESTAMPRESOLUTION_G(x) \
1332 (((x) >> TIMESTAMPRESOLUTION_S) & TIMESTAMPRESOLUTION_M)
1333
1334#define DELAYEDACKRESOLUTION_S 0
1335#define DELAYEDACKRESOLUTION_M 0xffU
1336#define DELAYEDACKRESOLUTION_G(x) \
1337 (((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M)
1338
1339#define TP_SHIFT_CNT_A 0x7dc0
1340#define TP_RXT_MIN_A 0x7d98
1341#define TP_RXT_MAX_A 0x7d9c
1342#define TP_PERS_MIN_A 0x7da0
1343#define TP_PERS_MAX_A 0x7da4
1344#define TP_KEEP_IDLE_A 0x7da8
1345#define TP_KEEP_INTVL_A 0x7dac
1346#define TP_INIT_SRTT_A 0x7db0
1347#define TP_DACK_TIMER_A 0x7db4
1348#define TP_FINWAIT2_TIMER_A 0x7db8
1349
1350#define INITSRTT_S 0
1351#define INITSRTT_M 0xffffU
1352#define INITSRTT_G(x) (((x) >> INITSRTT_S) & INITSRTT_M)
1353
1354#define PERSMAX_S 0
1355#define PERSMAX_M 0x3fffffffU
1356#define PERSMAX_V(x) ((x) << PERSMAX_S)
1357#define PERSMAX_G(x) (((x) >> PERSMAX_S) & PERSMAX_M)
1358
1359#define SYNSHIFTMAX_S 24
1360#define SYNSHIFTMAX_M 0xffU
1361#define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S)
1362#define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M)
1363
1364#define RXTSHIFTMAXR1_S 20
1365#define RXTSHIFTMAXR1_M 0xfU
1366#define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S)
1367#define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M)
1368
1369#define RXTSHIFTMAXR2_S 16
1370#define RXTSHIFTMAXR2_M 0xfU
1371#define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S)
1372#define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M)
1373
1374#define PERSHIFTBACKOFFMAX_S 12
1375#define PERSHIFTBACKOFFMAX_M 0xfU
1376#define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S)
1377#define PERSHIFTBACKOFFMAX_G(x) \
1378 (((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M)
1379
1380#define PERSHIFTMAX_S 8
1381#define PERSHIFTMAX_M 0xfU
1382#define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S)
1383#define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M)
1384
1385#define KEEPALIVEMAXR1_S 4
1386#define KEEPALIVEMAXR1_M 0xfU
1387#define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S)
1388#define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M)
1389
1390#define KEEPALIVEMAXR2_S 0
1391#define KEEPALIVEMAXR2_M 0xfU
1392#define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S)
1393#define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M)
1394
1395#define ROWINDEX_S 16
1396#define ROWINDEX_V(x) ((x) << ROWINDEX_S)
1397
1398#define TP_CCTRL_TABLE_A 0x7ddc
1399#define TP_MTU_TABLE_A 0x7de4
1400
1401#define MTUINDEX_S 24
1402#define MTUINDEX_V(x) ((x) << MTUINDEX_S)
1403
1404#define MTUWIDTH_S 16
1405#define MTUWIDTH_M 0xfU
1406#define MTUWIDTH_V(x) ((x) << MTUWIDTH_S)
1407#define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M)
1408
1409#define MTUVALUE_S 0
1410#define MTUVALUE_M 0x3fffU
1411#define MTUVALUE_V(x) ((x) << MTUVALUE_S)
1412#define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M)
1413
1414#define TP_RSS_LKP_TABLE_A 0x7dec
1415#define TP_CMM_MM_RX_FLST_BASE_A 0x7e60
1416#define TP_CMM_MM_TX_FLST_BASE_A 0x7e64
1417#define TP_CMM_MM_PS_FLST_BASE_A 0x7e68
1418
1419#define LKPTBLROWVLD_S 31
1420#define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S)
1421#define LKPTBLROWVLD_F LKPTBLROWVLD_V(1U)
1422
1423#define LKPTBLQUEUE1_S 10
1424#define LKPTBLQUEUE1_M 0x3ffU
1425#define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M)
1426
1427#define LKPTBLQUEUE0_S 0
1428#define LKPTBLQUEUE0_M 0x3ffU
1429#define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M)
1430
1431#define TP_PIO_ADDR_A 0x7e40
1432#define TP_PIO_DATA_A 0x7e44
1433#define TP_MIB_INDEX_A 0x7e50
1434#define TP_MIB_DATA_A 0x7e54
1435#define TP_INT_CAUSE_A 0x7e74
1436
1437#define FLMTXFLSTEMPTY_S 30
1438#define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S)
1439#define FLMTXFLSTEMPTY_F FLMTXFLSTEMPTY_V(1U)
1440
1441#define TP_TX_ORATE_A 0x7ebc
1442
1443#define OFDRATE3_S 24
1444#define OFDRATE3_M 0xffU
1445#define OFDRATE3_G(x) (((x) >> OFDRATE3_S) & OFDRATE3_M)
1446
1447#define OFDRATE2_S 16
1448#define OFDRATE2_M 0xffU
1449#define OFDRATE2_G(x) (((x) >> OFDRATE2_S) & OFDRATE2_M)
1450
1451#define OFDRATE1_S 8
1452#define OFDRATE1_M 0xffU
1453#define OFDRATE1_G(x) (((x) >> OFDRATE1_S) & OFDRATE1_M)
1454
1455#define OFDRATE0_S 0
1456#define OFDRATE0_M 0xffU
1457#define OFDRATE0_G(x) (((x) >> OFDRATE0_S) & OFDRATE0_M)
1458
1459#define TP_TX_TRATE_A 0x7ed0
1460
1461#define TNLRATE3_S 24
1462#define TNLRATE3_M 0xffU
1463#define TNLRATE3_G(x) (((x) >> TNLRATE3_S) & TNLRATE3_M)
1464
1465#define TNLRATE2_S 16
1466#define TNLRATE2_M 0xffU
1467#define TNLRATE2_G(x) (((x) >> TNLRATE2_S) & TNLRATE2_M)
1468
1469#define TNLRATE1_S 8
1470#define TNLRATE1_M 0xffU
1471#define TNLRATE1_G(x) (((x) >> TNLRATE1_S) & TNLRATE1_M)
1472
1473#define TNLRATE0_S 0
1474#define TNLRATE0_M 0xffU
1475#define TNLRATE0_G(x) (((x) >> TNLRATE0_S) & TNLRATE0_M)
1476
1477#define TP_VLAN_PRI_MAP_A 0x140
1478
1479#define FRAGMENTATION_S 9
1480#define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S)
1481#define FRAGMENTATION_F FRAGMENTATION_V(1U)
1482
1483#define MPSHITTYPE_S 8
1484#define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S)
1485#define MPSHITTYPE_F MPSHITTYPE_V(1U)
1486
1487#define MACMATCH_S 7
1488#define MACMATCH_V(x) ((x) << MACMATCH_S)
1489#define MACMATCH_F MACMATCH_V(1U)
1490
1491#define ETHERTYPE_S 6
1492#define ETHERTYPE_V(x) ((x) << ETHERTYPE_S)
1493#define ETHERTYPE_F ETHERTYPE_V(1U)
1494
1495#define PROTOCOL_S 5
1496#define PROTOCOL_V(x) ((x) << PROTOCOL_S)
1497#define PROTOCOL_F PROTOCOL_V(1U)
1498
1499#define TOS_S 4
1500#define TOS_V(x) ((x) << TOS_S)
1501#define TOS_F TOS_V(1U)
1502
1503#define VLAN_S 3
1504#define VLAN_V(x) ((x) << VLAN_S)
1505#define VLAN_F VLAN_V(1U)
1506
1507#define VNIC_ID_S 2
1508#define VNIC_ID_V(x) ((x) << VNIC_ID_S)
1509#define VNIC_ID_F VNIC_ID_V(1U)
1510
1511#define PORT_S 1
1512#define PORT_V(x) ((x) << PORT_S)
1513#define PORT_F PORT_V(1U)
1514
1515#define FCOE_S 0
1516#define FCOE_V(x) ((x) << FCOE_S)
1517#define FCOE_F FCOE_V(1U)
1518
1519#define FILTERMODE_S 15
1520#define FILTERMODE_V(x) ((x) << FILTERMODE_S)
1521#define FILTERMODE_F FILTERMODE_V(1U)
1522
1523#define FCOEMASK_S 14
1524#define FCOEMASK_V(x) ((x) << FCOEMASK_S)
1525#define FCOEMASK_F FCOEMASK_V(1U)
1526
1527#define TP_INGRESS_CONFIG_A 0x141
1528
1529#define VNIC_S 11
1530#define VNIC_V(x) ((x) << VNIC_S)
1531#define VNIC_F VNIC_V(1U)
1532
1533#define CSUM_HAS_PSEUDO_HDR_S 10
1534#define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S)
1535#define CSUM_HAS_PSEUDO_HDR_F CSUM_HAS_PSEUDO_HDR_V(1U)
1536
1537#define TP_MIB_MAC_IN_ERR_0_A 0x0
1538#define TP_MIB_HDR_IN_ERR_0_A 0x4
1539#define TP_MIB_TCP_IN_ERR_0_A 0x8
1540#define TP_MIB_TCP_OUT_RST_A 0xc
1541#define TP_MIB_TCP_IN_SEG_HI_A 0x10
1542#define TP_MIB_TCP_IN_SEG_LO_A 0x11
1543#define TP_MIB_TCP_OUT_SEG_HI_A 0x12
1544#define TP_MIB_TCP_OUT_SEG_LO_A 0x13
1545#define TP_MIB_TCP_RXT_SEG_HI_A 0x14
1546#define TP_MIB_TCP_RXT_SEG_LO_A 0x15
1547#define TP_MIB_TNL_CNG_DROP_0_A 0x18
1548#define TP_MIB_OFD_CHN_DROP_0_A 0x1c
1549#define TP_MIB_TCP_V6IN_ERR_0_A 0x28
1550#define TP_MIB_TCP_V6OUT_RST_A 0x2c
1551#define TP_MIB_OFD_ARP_DROP_A 0x36
1552#define TP_MIB_CPL_IN_REQ_0_A 0x38
1553#define TP_MIB_CPL_OUT_RSP_0_A 0x3c
1554#define TP_MIB_TNL_DROP_0_A 0x44
1555#define TP_MIB_FCOE_DDP_0_A 0x48
1556#define TP_MIB_FCOE_DROP_0_A 0x4c
1557#define TP_MIB_FCOE_BYTE_0_HI_A 0x50
1558#define TP_MIB_OFD_VLN_DROP_0_A 0x58
1559#define TP_MIB_USM_PKTS_A 0x5c
1560#define TP_MIB_RQE_DFR_PKT_A 0x64
1561
1562#define ULP_TX_INT_CAUSE_A 0x8dcc
1563#define ULP_TX_TPT_LLIMIT_A 0x8dd4
1564#define ULP_TX_TPT_ULIMIT_A 0x8dd8
1565#define ULP_TX_PBL_LLIMIT_A 0x8ddc
1566#define ULP_TX_PBL_ULIMIT_A 0x8de0
1567#define ULP_TX_ERR_TABLE_BASE_A 0x8e04
1568
1569#define PBL_BOUND_ERR_CH3_S 31
1570#define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S)
1571#define PBL_BOUND_ERR_CH3_F PBL_BOUND_ERR_CH3_V(1U)
1572
1573#define PBL_BOUND_ERR_CH2_S 30
1574#define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S)
1575#define PBL_BOUND_ERR_CH2_F PBL_BOUND_ERR_CH2_V(1U)
1576
1577#define PBL_BOUND_ERR_CH1_S 29
1578#define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S)
1579#define PBL_BOUND_ERR_CH1_F PBL_BOUND_ERR_CH1_V(1U)
1580
1581#define PBL_BOUND_ERR_CH0_S 28
1582#define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S)
1583#define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U)
1584
1585#define PM_RX_INT_CAUSE_A 0x8fdc
1586#define PM_RX_STAT_CONFIG_A 0x8fc8
1587#define PM_RX_STAT_COUNT_A 0x8fcc
1588#define PM_RX_STAT_LSB_A 0x8fd0
1589#define PM_RX_DBG_CTRL_A 0x8fd0
1590#define PM_RX_DBG_DATA_A 0x8fd4
1591#define PM_RX_DBG_STAT_MSB_A 0x10013
1592
1593#define PMRX_FRAMING_ERROR_F 0x003ffff0U
1594
1595#define ZERO_E_CMD_ERROR_S 22
1596#define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S)
1597#define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U)
1598
1599#define OCSPI_PAR_ERROR_S 3
1600#define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S)
1601#define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U)
1602
1603#define DB_OPTIONS_PAR_ERROR_S 2
1604#define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S)
1605#define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U)
1606
1607#define IESPI_PAR_ERROR_S 1
1608#define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S)
1609#define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U)
1610
1611#define PMRX_E_PCMD_PAR_ERROR_S 0
1612#define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S)
1613#define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U)
1614
1615#define PM_TX_INT_CAUSE_A 0x8ffc
1616#define PM_TX_STAT_CONFIG_A 0x8fe8
1617#define PM_TX_STAT_COUNT_A 0x8fec
1618#define PM_TX_STAT_LSB_A 0x8ff0
1619#define PM_TX_DBG_CTRL_A 0x8ff0
1620#define PM_TX_DBG_DATA_A 0x8ff4
1621#define PM_TX_DBG_STAT_MSB_A 0x1001a
1622
1623#define PCMD_LEN_OVFL0_S 31
1624#define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S)
1625#define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U)
1626
1627#define PCMD_LEN_OVFL1_S 30
1628#define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S)
1629#define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U)
1630
1631#define PCMD_LEN_OVFL2_S 29
1632#define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S)
1633#define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U)
1634
1635#define ZERO_C_CMD_ERROR_S 28
1636#define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S)
1637#define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U)
1638
1639#define PMTX_FRAMING_ERROR_F 0x0ffffff0U
1640
1641#define OESPI_PAR_ERROR_S 3
1642#define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S)
1643#define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U)
1644
1645#define ICSPI_PAR_ERROR_S 1
1646#define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S)
1647#define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U)
1648
1649#define PMTX_C_PCMD_PAR_ERROR_S 0
1650#define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S)
1651#define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U)
1652
1653#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
1654#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
1655#define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
1656#define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
1657#define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
1658#define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
1659#define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
1660#define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
1661#define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
1662#define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
1663#define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
1664#define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
1665#define MPS_PORT_STAT_TX_PORT_64B_L 0x430
1666#define MPS_PORT_STAT_TX_PORT_64B_H 0x434
1667#define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
1668#define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
1669#define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
1670#define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
1671#define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
1672#define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
1673#define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
1674#define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
1675#define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
1676#define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
1677#define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
1678#define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
1679#define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
1680#define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
1681#define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
1682#define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
1683#define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
1684#define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
1685#define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
1686#define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
1687#define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
1688#define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
1689#define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
1690#define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
1691#define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
1692#define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
1693#define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
1694#define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
1695#define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
1696#define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
1697#define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
1698#define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
1699#define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
1700#define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
1701#define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
1702#define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
1703#define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
1704#define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
1705#define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
1706#define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
1707#define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
1708#define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
1709#define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
1710#define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
1711#define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
1712#define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
1713#define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
1714#define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
1715#define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
1716#define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
1717#define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
1718#define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
1719#define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
1720#define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
1721#define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
1722#define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
1723#define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
1724#define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
1725#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
1726#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
1727#define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
1728#define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
1729#define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
1730#define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
1731#define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
1732#define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
1733#define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
1734#define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
1735#define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
1736#define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
1737#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
1738#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
1739#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
1740#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
1741#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
1742#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
1743#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
1744#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
1745#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
1746#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
1747#define MPS_PORT_STAT_RX_PORT_64B_L 0x590
1748#define MPS_PORT_STAT_RX_PORT_64B_H 0x594
1749#define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
1750#define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
1751#define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
1752#define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
1753#define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
1754#define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
1755#define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
1756#define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
1757#define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
1758#define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
1759#define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
1760#define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
1761#define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
1762#define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
1763#define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
1764#define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
1765#define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
1766#define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
1767#define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
1768#define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
1769#define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
1770#define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
1771#define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
1772#define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
1773#define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
1774#define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
1775#define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
1776#define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
1777#define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
1778#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
1779#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
1780#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
1781#define MAC_PORT_MAGIC_MACID_LO 0x824
1782#define MAC_PORT_MAGIC_MACID_HI 0x828
1783
1784#define MAC_PORT_EPIO_DATA0_A 0x8c0
1785#define MAC_PORT_EPIO_DATA1_A 0x8c4
1786#define MAC_PORT_EPIO_DATA2_A 0x8c8
1787#define MAC_PORT_EPIO_DATA3_A 0x8cc
1788#define MAC_PORT_EPIO_OP_A 0x8d0
1789
1790#define MAC_PORT_CFG2_A 0x818
1791
1792#define MPS_CMN_CTL_A 0x9000
1793
1794#define NUMPORTS_S 0
1795#define NUMPORTS_M 0x3U
1796#define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M)
1797
1798#define MPS_INT_CAUSE_A 0x9008
1799#define MPS_TX_INT_CAUSE_A 0x9408
1800
1801#define FRMERR_S 15
1802#define FRMERR_V(x) ((x) << FRMERR_S)
1803#define FRMERR_F FRMERR_V(1U)
1804
1805#define SECNTERR_S 14
1806#define SECNTERR_V(x) ((x) << SECNTERR_S)
1807#define SECNTERR_F SECNTERR_V(1U)
1808
1809#define BUBBLE_S 13
1810#define BUBBLE_V(x) ((x) << BUBBLE_S)
1811#define BUBBLE_F BUBBLE_V(1U)
1812
1813#define TXDESCFIFO_S 9
1814#define TXDESCFIFO_M 0xfU
1815#define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S)
1816
1817#define TXDATAFIFO_S 5
1818#define TXDATAFIFO_M 0xfU
1819#define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S)
1820
1821#define NCSIFIFO_S 4
1822#define NCSIFIFO_V(x) ((x) << NCSIFIFO_S)
1823#define NCSIFIFO_F NCSIFIFO_V(1U)
1824
1825#define TPFIFO_S 0
1826#define TPFIFO_M 0xfU
1827#define TPFIFO_V(x) ((x) << TPFIFO_S)
1828
1829#define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614
1830#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620
1831#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c
1832
1833#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
1834#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
1835#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
1836#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
1837#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
1838#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
1839#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
1840#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
1841#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
1842#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
1843#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
1844#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
1845#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
1846#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
1847#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
1848#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
1849#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
1850#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
1851#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
1852#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
1853#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
1854#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
1855#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
1856#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
1857#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
1858#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
1859#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
1860#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
1861#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
1862#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
1863#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
1864#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
1865
1866#define MPS_TRC_CFG_A 0x9800
1867
1868#define TRCFIFOEMPTY_S 4
1869#define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S)
1870#define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U)
1871
1872#define TRCIGNOREDROPINPUT_S 3
1873#define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S)
1874#define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U)
1875
1876#define TRCKEEPDUPLICATES_S 2
1877#define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S)
1878#define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U)
1879
1880#define TRCEN_S 1
1881#define TRCEN_V(x) ((x) << TRCEN_S)
1882#define TRCEN_F TRCEN_V(1U)
1883
1884#define TRCMULTIFILTER_S 0
1885#define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S)
1886#define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U)
1887
1888#define MPS_TRC_RSS_CONTROL_A 0x9808
1889#define MPS_TRC_FILTER1_RSS_CONTROL_A 0x9ff4
1890#define MPS_TRC_FILTER2_RSS_CONTROL_A 0x9ffc
1891#define MPS_TRC_FILTER3_RSS_CONTROL_A 0xa004
1892#define MPS_T5_TRC_RSS_CONTROL_A 0xa00c
1893
1894#define RSSCONTROL_S 16
1895#define RSSCONTROL_V(x) ((x) << RSSCONTROL_S)
1896
1897#define QUEUENUMBER_S 0
1898#define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S)
1899
1900#define TFINVERTMATCH_S 24
1901#define TFINVERTMATCH_V(x) ((x) << TFINVERTMATCH_S)
1902#define TFINVERTMATCH_F TFINVERTMATCH_V(1U)
1903
1904#define TFEN_S 22
1905#define TFEN_V(x) ((x) << TFEN_S)
1906#define TFEN_F TFEN_V(1U)
1907
1908#define TFPORT_S 18
1909#define TFPORT_M 0xfU
1910#define TFPORT_V(x) ((x) << TFPORT_S)
1911#define TFPORT_G(x) (((x) >> TFPORT_S) & TFPORT_M)
1912
1913#define TFLENGTH_S 8
1914#define TFLENGTH_M 0x1fU
1915#define TFLENGTH_V(x) ((x) << TFLENGTH_S)
1916#define TFLENGTH_G(x) (((x) >> TFLENGTH_S) & TFLENGTH_M)
1917
1918#define TFOFFSET_S 0
1919#define TFOFFSET_M 0x1fU
1920#define TFOFFSET_V(x) ((x) << TFOFFSET_S)
1921#define TFOFFSET_G(x) (((x) >> TFOFFSET_S) & TFOFFSET_M)
1922
1923#define T5_TFINVERTMATCH_S 25
1924#define T5_TFINVERTMATCH_V(x) ((x) << T5_TFINVERTMATCH_S)
1925#define T5_TFINVERTMATCH_F T5_TFINVERTMATCH_V(1U)
1926
1927#define T5_TFEN_S 23
1928#define T5_TFEN_V(x) ((x) << T5_TFEN_S)
1929#define T5_TFEN_F T5_TFEN_V(1U)
1930
1931#define T5_TFPORT_S 18
1932#define T5_TFPORT_M 0x1fU
1933#define T5_TFPORT_V(x) ((x) << T5_TFPORT_S)
1934#define T5_TFPORT_G(x) (((x) >> T5_TFPORT_S) & T5_TFPORT_M)
1935
1936#define MPS_TRC_FILTER_MATCH_CTL_A_A 0x9810
1937#define MPS_TRC_FILTER_MATCH_CTL_B_A 0x9820
1938
1939#define TFMINPKTSIZE_S 16
1940#define TFMINPKTSIZE_M 0x1ffU
1941#define TFMINPKTSIZE_V(x) ((x) << TFMINPKTSIZE_S)
1942#define TFMINPKTSIZE_G(x) (((x) >> TFMINPKTSIZE_S) & TFMINPKTSIZE_M)
1943
1944#define TFCAPTUREMAX_S 0
1945#define TFCAPTUREMAX_M 0x3fffU
1946#define TFCAPTUREMAX_V(x) ((x) << TFCAPTUREMAX_S)
1947#define TFCAPTUREMAX_G(x) (((x) >> TFCAPTUREMAX_S) & TFCAPTUREMAX_M)
1948
1949#define MPS_TRC_FILTER0_MATCH_A 0x9c00
1950#define MPS_TRC_FILTER0_DONT_CARE_A 0x9c80
1951#define MPS_TRC_FILTER1_MATCH_A 0x9d00
1952
1953#define TP_RSS_CONFIG_A 0x7df0
1954
1955#define TNL4TUPENIPV6_S 31
1956#define TNL4TUPENIPV6_V(x) ((x) << TNL4TUPENIPV6_S)
1957#define TNL4TUPENIPV6_F TNL4TUPENIPV6_V(1U)
1958
1959#define TNL2TUPENIPV6_S 30
1960#define TNL2TUPENIPV6_V(x) ((x) << TNL2TUPENIPV6_S)
1961#define TNL2TUPENIPV6_F TNL2TUPENIPV6_V(1U)
1962
1963#define TNL4TUPENIPV4_S 29
1964#define TNL4TUPENIPV4_V(x) ((x) << TNL4TUPENIPV4_S)
1965#define TNL4TUPENIPV4_F TNL4TUPENIPV4_V(1U)
1966
1967#define TNL2TUPENIPV4_S 28
1968#define TNL2TUPENIPV4_V(x) ((x) << TNL2TUPENIPV4_S)
1969#define TNL2TUPENIPV4_F TNL2TUPENIPV4_V(1U)
1970
1971#define TNLTCPSEL_S 27
1972#define TNLTCPSEL_V(x) ((x) << TNLTCPSEL_S)
1973#define TNLTCPSEL_F TNLTCPSEL_V(1U)
1974
1975#define TNLIP6SEL_S 26
1976#define TNLIP6SEL_V(x) ((x) << TNLIP6SEL_S)
1977#define TNLIP6SEL_F TNLIP6SEL_V(1U)
1978
1979#define TNLVRTSEL_S 25
1980#define TNLVRTSEL_V(x) ((x) << TNLVRTSEL_S)
1981#define TNLVRTSEL_F TNLVRTSEL_V(1U)
1982
1983#define TNLMAPEN_S 24
1984#define TNLMAPEN_V(x) ((x) << TNLMAPEN_S)
1985#define TNLMAPEN_F TNLMAPEN_V(1U)
1986
1987#define OFDHASHSAVE_S 19
1988#define OFDHASHSAVE_V(x) ((x) << OFDHASHSAVE_S)
1989#define OFDHASHSAVE_F OFDHASHSAVE_V(1U)
1990
1991#define OFDVRTSEL_S 18
1992#define OFDVRTSEL_V(x) ((x) << OFDVRTSEL_S)
1993#define OFDVRTSEL_F OFDVRTSEL_V(1U)
1994
1995#define OFDMAPEN_S 17
1996#define OFDMAPEN_V(x) ((x) << OFDMAPEN_S)
1997#define OFDMAPEN_F OFDMAPEN_V(1U)
1998
1999#define OFDLKPEN_S 16
2000#define OFDLKPEN_V(x) ((x) << OFDLKPEN_S)
2001#define OFDLKPEN_F OFDLKPEN_V(1U)
2002
2003#define SYN4TUPENIPV6_S 15
2004#define SYN4TUPENIPV6_V(x) ((x) << SYN4TUPENIPV6_S)
2005#define SYN4TUPENIPV6_F SYN4TUPENIPV6_V(1U)
2006
2007#define SYN2TUPENIPV6_S 14
2008#define SYN2TUPENIPV6_V(x) ((x) << SYN2TUPENIPV6_S)
2009#define SYN2TUPENIPV6_F SYN2TUPENIPV6_V(1U)
2010
2011#define SYN4TUPENIPV4_S 13
2012#define SYN4TUPENIPV4_V(x) ((x) << SYN4TUPENIPV4_S)
2013#define SYN4TUPENIPV4_F SYN4TUPENIPV4_V(1U)
2014
2015#define SYN2TUPENIPV4_S 12
2016#define SYN2TUPENIPV4_V(x) ((x) << SYN2TUPENIPV4_S)
2017#define SYN2TUPENIPV4_F SYN2TUPENIPV4_V(1U)
2018
2019#define SYNIP6SEL_S 11
2020#define SYNIP6SEL_V(x) ((x) << SYNIP6SEL_S)
2021#define SYNIP6SEL_F SYNIP6SEL_V(1U)
2022
2023#define SYNVRTSEL_S 10
2024#define SYNVRTSEL_V(x) ((x) << SYNVRTSEL_S)
2025#define SYNVRTSEL_F SYNVRTSEL_V(1U)
2026
2027#define SYNMAPEN_S 9
2028#define SYNMAPEN_V(x) ((x) << SYNMAPEN_S)
2029#define SYNMAPEN_F SYNMAPEN_V(1U)
2030
2031#define SYNLKPEN_S 8
2032#define SYNLKPEN_V(x) ((x) << SYNLKPEN_S)
2033#define SYNLKPEN_F SYNLKPEN_V(1U)
2034
2035#define CHANNELENABLE_S 7
2036#define CHANNELENABLE_V(x) ((x) << CHANNELENABLE_S)
2037#define CHANNELENABLE_F CHANNELENABLE_V(1U)
2038
2039#define PORTENABLE_S 6
2040#define PORTENABLE_V(x) ((x) << PORTENABLE_S)
2041#define PORTENABLE_F PORTENABLE_V(1U)
2042
2043#define TNLALLLOOKUP_S 5
2044#define TNLALLLOOKUP_V(x) ((x) << TNLALLLOOKUP_S)
2045#define TNLALLLOOKUP_F TNLALLLOOKUP_V(1U)
2046
2047#define VIRTENABLE_S 4
2048#define VIRTENABLE_V(x) ((x) << VIRTENABLE_S)
2049#define VIRTENABLE_F VIRTENABLE_V(1U)
2050
2051#define CONGESTIONENABLE_S 3
2052#define CONGESTIONENABLE_V(x) ((x) << CONGESTIONENABLE_S)
2053#define CONGESTIONENABLE_F CONGESTIONENABLE_V(1U)
2054
2055#define HASHTOEPLITZ_S 2
2056#define HASHTOEPLITZ_V(x) ((x) << HASHTOEPLITZ_S)
2057#define HASHTOEPLITZ_F HASHTOEPLITZ_V(1U)
2058
2059#define UDPENABLE_S 1
2060#define UDPENABLE_V(x) ((x) << UDPENABLE_S)
2061#define UDPENABLE_F UDPENABLE_V(1U)
2062
2063#define DISABLE_S 0
2064#define DISABLE_V(x) ((x) << DISABLE_S)
2065#define DISABLE_F DISABLE_V(1U)
2066
2067#define TP_RSS_CONFIG_TNL_A 0x7df4
2068
2069#define MASKSIZE_S 28
2070#define MASKSIZE_M 0xfU
2071#define MASKSIZE_V(x) ((x) << MASKSIZE_S)
2072#define MASKSIZE_G(x) (((x) >> MASKSIZE_S) & MASKSIZE_M)
2073
2074#define MASKFILTER_S 16
2075#define MASKFILTER_M 0x7ffU
2076#define MASKFILTER_V(x) ((x) << MASKFILTER_S)
2077#define MASKFILTER_G(x) (((x) >> MASKFILTER_S) & MASKFILTER_M)
2078
2079#define USEWIRECH_S 0
2080#define USEWIRECH_V(x) ((x) << USEWIRECH_S)
2081#define USEWIRECH_F USEWIRECH_V(1U)
2082
2083#define HASHALL_S 2
2084#define HASHALL_V(x) ((x) << HASHALL_S)
2085#define HASHALL_F HASHALL_V(1U)
2086
2087#define HASHETH_S 1
2088#define HASHETH_V(x) ((x) << HASHETH_S)
2089#define HASHETH_F HASHETH_V(1U)
2090
2091#define TP_RSS_CONFIG_OFD_A 0x7df8
2092
2093#define RRCPLMAPEN_S 20
2094#define RRCPLMAPEN_V(x) ((x) << RRCPLMAPEN_S)
2095#define RRCPLMAPEN_F RRCPLMAPEN_V(1U)
2096
2097#define RRCPLQUEWIDTH_S 16
2098#define RRCPLQUEWIDTH_M 0xfU
2099#define RRCPLQUEWIDTH_V(x) ((x) << RRCPLQUEWIDTH_S)
2100#define RRCPLQUEWIDTH_G(x) (((x) >> RRCPLQUEWIDTH_S) & RRCPLQUEWIDTH_M)
2101
2102#define TP_RSS_CONFIG_SYN_A 0x7dfc
2103#define TP_RSS_CONFIG_VRT_A 0x7e00
2104
2105#define VFRDRG_S 25
2106#define VFRDRG_V(x) ((x) << VFRDRG_S)
2107#define VFRDRG_F VFRDRG_V(1U)
2108
2109#define VFRDEN_S 24
2110#define VFRDEN_V(x) ((x) << VFRDEN_S)
2111#define VFRDEN_F VFRDEN_V(1U)
2112
2113#define VFPERREN_S 23
2114#define VFPERREN_V(x) ((x) << VFPERREN_S)
2115#define VFPERREN_F VFPERREN_V(1U)
2116
2117#define KEYPERREN_S 22
2118#define KEYPERREN_V(x) ((x) << KEYPERREN_S)
2119#define KEYPERREN_F KEYPERREN_V(1U)
2120
2121#define DISABLEVLAN_S 21
2122#define DISABLEVLAN_V(x) ((x) << DISABLEVLAN_S)
2123#define DISABLEVLAN_F DISABLEVLAN_V(1U)
2124
2125#define ENABLEUP0_S 20
2126#define ENABLEUP0_V(x) ((x) << ENABLEUP0_S)
2127#define ENABLEUP0_F ENABLEUP0_V(1U)
2128
2129#define HASHDELAY_S 16
2130#define HASHDELAY_M 0xfU
2131#define HASHDELAY_V(x) ((x) << HASHDELAY_S)
2132#define HASHDELAY_G(x) (((x) >> HASHDELAY_S) & HASHDELAY_M)
2133
2134#define VFWRADDR_S 8
2135#define VFWRADDR_M 0x7fU
2136#define VFWRADDR_V(x) ((x) << VFWRADDR_S)
2137#define VFWRADDR_G(x) (((x) >> VFWRADDR_S) & VFWRADDR_M)
2138
2139#define KEYMODE_S 6
2140#define KEYMODE_M 0x3U
2141#define KEYMODE_V(x) ((x) << KEYMODE_S)
2142#define KEYMODE_G(x) (((x) >> KEYMODE_S) & KEYMODE_M)
2143
2144#define VFWREN_S 5
2145#define VFWREN_V(x) ((x) << VFWREN_S)
2146#define VFWREN_F VFWREN_V(1U)
2147
2148#define KEYWREN_S 4
2149#define KEYWREN_V(x) ((x) << KEYWREN_S)
2150#define KEYWREN_F KEYWREN_V(1U)
2151
2152#define KEYWRADDR_S 0
2153#define KEYWRADDR_M 0xfU
2154#define KEYWRADDR_V(x) ((x) << KEYWRADDR_S)
2155#define KEYWRADDR_G(x) (((x) >> KEYWRADDR_S) & KEYWRADDR_M)
2156
2157#define KEYWRADDRX_S 30
2158#define KEYWRADDRX_M 0x3U
2159#define KEYWRADDRX_V(x) ((x) << KEYWRADDRX_S)
2160#define KEYWRADDRX_G(x) (((x) >> KEYWRADDRX_S) & KEYWRADDRX_M)
2161
2162#define KEYEXTEND_S 26
2163#define KEYEXTEND_V(x) ((x) << KEYEXTEND_S)
2164#define KEYEXTEND_F KEYEXTEND_V(1U)
2165
2166#define LKPIDXSIZE_S 24
2167#define LKPIDXSIZE_M 0x3U
2168#define LKPIDXSIZE_V(x) ((x) << LKPIDXSIZE_S)
2169#define LKPIDXSIZE_G(x) (((x) >> LKPIDXSIZE_S) & LKPIDXSIZE_M)
2170
2171#define TP_RSS_VFL_CONFIG_A 0x3a
2172#define TP_RSS_VFH_CONFIG_A 0x3b
2173
2174#define ENABLEUDPHASH_S 31
2175#define ENABLEUDPHASH_V(x) ((x) << ENABLEUDPHASH_S)
2176#define ENABLEUDPHASH_F ENABLEUDPHASH_V(1U)
2177
2178#define VFUPEN_S 30
2179#define VFUPEN_V(x) ((x) << VFUPEN_S)
2180#define VFUPEN_F VFUPEN_V(1U)
2181
2182#define VFVLNEX_S 28
2183#define VFVLNEX_V(x) ((x) << VFVLNEX_S)
2184#define VFVLNEX_F VFVLNEX_V(1U)
2185
2186#define VFPRTEN_S 27
2187#define VFPRTEN_V(x) ((x) << VFPRTEN_S)
2188#define VFPRTEN_F VFPRTEN_V(1U)
2189
2190#define VFCHNEN_S 26
2191#define VFCHNEN_V(x) ((x) << VFCHNEN_S)
2192#define VFCHNEN_F VFCHNEN_V(1U)
2193
2194#define DEFAULTQUEUE_S 16
2195#define DEFAULTQUEUE_M 0x3ffU
2196#define DEFAULTQUEUE_G(x) (((x) >> DEFAULTQUEUE_S) & DEFAULTQUEUE_M)
2197
2198#define VFIP6TWOTUPEN_S 6
2199#define VFIP6TWOTUPEN_V(x) ((x) << VFIP6TWOTUPEN_S)
2200#define VFIP6TWOTUPEN_F VFIP6TWOTUPEN_V(1U)
2201
2202#define VFIP4FOURTUPEN_S 5
2203#define VFIP4FOURTUPEN_V(x) ((x) << VFIP4FOURTUPEN_S)
2204#define VFIP4FOURTUPEN_F VFIP4FOURTUPEN_V(1U)
2205
2206#define VFIP4TWOTUPEN_S 4
2207#define VFIP4TWOTUPEN_V(x) ((x) << VFIP4TWOTUPEN_S)
2208#define VFIP4TWOTUPEN_F VFIP4TWOTUPEN_V(1U)
2209
2210#define KEYINDEX_S 0
2211#define KEYINDEX_M 0xfU
2212#define KEYINDEX_G(x) (((x) >> KEYINDEX_S) & KEYINDEX_M)
2213
2214#define MAPENABLE_S 31
2215#define MAPENABLE_V(x) ((x) << MAPENABLE_S)
2216#define MAPENABLE_F MAPENABLE_V(1U)
2217
2218#define CHNENABLE_S 30
2219#define CHNENABLE_V(x) ((x) << CHNENABLE_S)
2220#define CHNENABLE_F CHNENABLE_V(1U)
2221
2222#define PRTENABLE_S 29
2223#define PRTENABLE_V(x) ((x) << PRTENABLE_S)
2224#define PRTENABLE_F PRTENABLE_V(1U)
2225
2226#define UDPFOURTUPEN_S 28
2227#define UDPFOURTUPEN_V(x) ((x) << UDPFOURTUPEN_S)
2228#define UDPFOURTUPEN_F UDPFOURTUPEN_V(1U)
2229
2230#define IP6FOURTUPEN_S 27
2231#define IP6FOURTUPEN_V(x) ((x) << IP6FOURTUPEN_S)
2232#define IP6FOURTUPEN_F IP6FOURTUPEN_V(1U)
2233
2234#define IP6TWOTUPEN_S 26
2235#define IP6TWOTUPEN_V(x) ((x) << IP6TWOTUPEN_S)
2236#define IP6TWOTUPEN_F IP6TWOTUPEN_V(1U)
2237
2238#define IP4FOURTUPEN_S 25
2239#define IP4FOURTUPEN_V(x) ((x) << IP4FOURTUPEN_S)
2240#define IP4FOURTUPEN_F IP4FOURTUPEN_V(1U)
2241
2242#define IP4TWOTUPEN_S 24
2243#define IP4TWOTUPEN_V(x) ((x) << IP4TWOTUPEN_S)
2244#define IP4TWOTUPEN_F IP4TWOTUPEN_V(1U)
2245
2246#define IVFWIDTH_S 20
2247#define IVFWIDTH_M 0xfU
2248#define IVFWIDTH_V(x) ((x) << IVFWIDTH_S)
2249#define IVFWIDTH_G(x) (((x) >> IVFWIDTH_S) & IVFWIDTH_M)
2250
2251#define CH1DEFAULTQUEUE_S 10
2252#define CH1DEFAULTQUEUE_M 0x3ffU
2253#define CH1DEFAULTQUEUE_V(x) ((x) << CH1DEFAULTQUEUE_S)
2254#define CH1DEFAULTQUEUE_G(x) (((x) >> CH1DEFAULTQUEUE_S) & CH1DEFAULTQUEUE_M)
2255
2256#define CH0DEFAULTQUEUE_S 0
2257#define CH0DEFAULTQUEUE_M 0x3ffU
2258#define CH0DEFAULTQUEUE_V(x) ((x) << CH0DEFAULTQUEUE_S)
2259#define CH0DEFAULTQUEUE_G(x) (((x) >> CH0DEFAULTQUEUE_S) & CH0DEFAULTQUEUE_M)
2260
2261#define VFLKPIDX_S 8
2262#define VFLKPIDX_M 0xffU
2263#define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M)
2264
2265#define T6_VFWRADDR_S 8
2266#define T6_VFWRADDR_M 0xffU
2267#define T6_VFWRADDR_V(x) ((x) << T6_VFWRADDR_S)
2268#define T6_VFWRADDR_G(x) (((x) >> T6_VFWRADDR_S) & T6_VFWRADDR_M)
2269
2270#define TP_RSS_CONFIG_CNG_A 0x7e04
2271#define TP_RSS_SECRET_KEY0_A 0x40
2272#define TP_RSS_PF0_CONFIG_A 0x30
2273#define TP_RSS_PF_MAP_A 0x38
2274#define TP_RSS_PF_MSK_A 0x39
2275
2276#define PF1LKPIDX_S 3
2277
2278#define PF0LKPIDX_M 0x7U
2279
2280#define PF1MSKSIZE_S 4
2281#define PF1MSKSIZE_M 0xfU
2282
2283#define CHNCOUNT3_S 31
2284#define CHNCOUNT3_V(x) ((x) << CHNCOUNT3_S)
2285#define CHNCOUNT3_F CHNCOUNT3_V(1U)
2286
2287#define CHNCOUNT2_S 30
2288#define CHNCOUNT2_V(x) ((x) << CHNCOUNT2_S)
2289#define CHNCOUNT2_F CHNCOUNT2_V(1U)
2290
2291#define CHNCOUNT1_S 29
2292#define CHNCOUNT1_V(x) ((x) << CHNCOUNT1_S)
2293#define CHNCOUNT1_F CHNCOUNT1_V(1U)
2294
2295#define CHNCOUNT0_S 28
2296#define CHNCOUNT0_V(x) ((x) << CHNCOUNT0_S)
2297#define CHNCOUNT0_F CHNCOUNT0_V(1U)
2298
2299#define CHNUNDFLOW3_S 27
2300#define CHNUNDFLOW3_V(x) ((x) << CHNUNDFLOW3_S)
2301#define CHNUNDFLOW3_F CHNUNDFLOW3_V(1U)
2302
2303#define CHNUNDFLOW2_S 26
2304#define CHNUNDFLOW2_V(x) ((x) << CHNUNDFLOW2_S)
2305#define CHNUNDFLOW2_F CHNUNDFLOW2_V(1U)
2306
2307#define CHNUNDFLOW1_S 25
2308#define CHNUNDFLOW1_V(x) ((x) << CHNUNDFLOW1_S)
2309#define CHNUNDFLOW1_F CHNUNDFLOW1_V(1U)
2310
2311#define CHNUNDFLOW0_S 24
2312#define CHNUNDFLOW0_V(x) ((x) << CHNUNDFLOW0_S)
2313#define CHNUNDFLOW0_F CHNUNDFLOW0_V(1U)
2314
2315#define RSTCHN3_S 19
2316#define RSTCHN3_V(x) ((x) << RSTCHN3_S)
2317#define RSTCHN3_F RSTCHN3_V(1U)
2318
2319#define RSTCHN2_S 18
2320#define RSTCHN2_V(x) ((x) << RSTCHN2_S)
2321#define RSTCHN2_F RSTCHN2_V(1U)
2322
2323#define RSTCHN1_S 17
2324#define RSTCHN1_V(x) ((x) << RSTCHN1_S)
2325#define RSTCHN1_F RSTCHN1_V(1U)
2326
2327#define RSTCHN0_S 16
2328#define RSTCHN0_V(x) ((x) << RSTCHN0_S)
2329#define RSTCHN0_F RSTCHN0_V(1U)
2330
2331#define UPDVLD_S 15
2332#define UPDVLD_V(x) ((x) << UPDVLD_S)
2333#define UPDVLD_F UPDVLD_V(1U)
2334
2335#define XOFF_S 14
2336#define XOFF_V(x) ((x) << XOFF_S)
2337#define XOFF_F XOFF_V(1U)
2338
2339#define UPDCHN3_S 13
2340#define UPDCHN3_V(x) ((x) << UPDCHN3_S)
2341#define UPDCHN3_F UPDCHN3_V(1U)
2342
2343#define UPDCHN2_S 12
2344#define UPDCHN2_V(x) ((x) << UPDCHN2_S)
2345#define UPDCHN2_F UPDCHN2_V(1U)
2346
2347#define UPDCHN1_S 11
2348#define UPDCHN1_V(x) ((x) << UPDCHN1_S)
2349#define UPDCHN1_F UPDCHN1_V(1U)
2350
2351#define UPDCHN0_S 10
2352#define UPDCHN0_V(x) ((x) << UPDCHN0_S)
2353#define UPDCHN0_F UPDCHN0_V(1U)
2354
2355#define QUEUE_S 0
2356#define QUEUE_M 0x3ffU
2357#define QUEUE_V(x) ((x) << QUEUE_S)
2358#define QUEUE_G(x) (((x) >> QUEUE_S) & QUEUE_M)
2359
2360#define MPS_TRC_INT_CAUSE_A 0x985c
2361
2362#define MISCPERR_S 8
2363#define MISCPERR_V(x) ((x) << MISCPERR_S)
2364#define MISCPERR_F MISCPERR_V(1U)
2365
2366#define PKTFIFO_S 4
2367#define PKTFIFO_M 0xfU
2368#define PKTFIFO_V(x) ((x) << PKTFIFO_S)
2369
2370#define FILTMEM_S 0
2371#define FILTMEM_M 0xfU
2372#define FILTMEM_V(x) ((x) << FILTMEM_S)
2373
2374#define MPS_CLS_INT_CAUSE_A 0xd028
2375
2376#define HASHSRAM_S 2
2377#define HASHSRAM_V(x) ((x) << HASHSRAM_S)
2378#define HASHSRAM_F HASHSRAM_V(1U)
2379
2380#define MATCHTCAM_S 1
2381#define MATCHTCAM_V(x) ((x) << MATCHTCAM_S)
2382#define MATCHTCAM_F MATCHTCAM_V(1U)
2383
2384#define MATCHSRAM_S 0
2385#define MATCHSRAM_V(x) ((x) << MATCHSRAM_S)
2386#define MATCHSRAM_F MATCHSRAM_V(1U)
2387
2388#define MPS_RX_PG_RSV0_A 0x11010
2389#define MPS_RX_PG_RSV4_A 0x11020
2390#define MPS_RX_PERR_INT_CAUSE_A 0x11074
2391#define MPS_RX_MAC_BG_PG_CNT0_A 0x11208
2392#define MPS_RX_LPBK_BG_PG_CNT0_A 0x11218
2393
2394#define MPS_CLS_TCAM_Y_L_A 0xf000
2395#define MPS_CLS_TCAM_DATA0_A 0xf000
2396#define MPS_CLS_TCAM_DATA1_A 0xf004
2397
2398#define USED_S 16
2399#define USED_M 0x7ffU
2400#define USED_G(x) (((x) >> USED_S) & USED_M)
2401
2402#define ALLOC_S 0
2403#define ALLOC_M 0x7ffU
2404#define ALLOC_G(x) (((x) >> ALLOC_S) & ALLOC_M)
2405
2406#define T5_USED_S 16
2407#define T5_USED_M 0xfffU
2408#define T5_USED_G(x) (((x) >> T5_USED_S) & T5_USED_M)
2409
2410#define T5_ALLOC_S 0
2411#define T5_ALLOC_M 0xfffU
2412#define T5_ALLOC_G(x) (((x) >> T5_ALLOC_S) & T5_ALLOC_M)
2413
2414#define DMACH_S 0
2415#define DMACH_M 0xffffU
2416#define DMACH_G(x) (((x) >> DMACH_S) & DMACH_M)
2417
2418#define MPS_CLS_TCAM_X_L_A 0xf008
2419#define MPS_CLS_TCAM_DATA2_CTL_A 0xf008
2420
2421#define CTLCMDTYPE_S 31
2422#define CTLCMDTYPE_V(x) ((x) << CTLCMDTYPE_S)
2423#define CTLCMDTYPE_F CTLCMDTYPE_V(1U)
2424
2425#define CTLTCAMSEL_S 25
2426#define CTLTCAMSEL_V(x) ((x) << CTLTCAMSEL_S)
2427
2428#define CTLTCAMINDEX_S 17
2429#define CTLTCAMINDEX_V(x) ((x) << CTLTCAMINDEX_S)
2430
2431#define CTLXYBITSEL_S 16
2432#define CTLXYBITSEL_V(x) ((x) << CTLXYBITSEL_S)
2433
2434#define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16)
2435#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
2436
2437#define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16)
2438#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
2439
2440#define MPS_CLS_SRAM_L_A 0xe000
2441
2442#define T6_MULTILISTEN0_S 26
2443
2444#define T6_SRAM_PRIO3_S 23
2445#define T6_SRAM_PRIO3_M 0x7U
2446#define T6_SRAM_PRIO3_G(x) (((x) >> T6_SRAM_PRIO3_S) & T6_SRAM_PRIO3_M)
2447
2448#define T6_SRAM_PRIO2_S 20
2449#define T6_SRAM_PRIO2_M 0x7U
2450#define T6_SRAM_PRIO2_G(x) (((x) >> T6_SRAM_PRIO2_S) & T6_SRAM_PRIO2_M)
2451
2452#define T6_SRAM_PRIO1_S 17
2453#define T6_SRAM_PRIO1_M 0x7U
2454#define T6_SRAM_PRIO1_G(x) (((x) >> T6_SRAM_PRIO1_S) & T6_SRAM_PRIO1_M)
2455
2456#define T6_SRAM_PRIO0_S 14
2457#define T6_SRAM_PRIO0_M 0x7U
2458#define T6_SRAM_PRIO0_G(x) (((x) >> T6_SRAM_PRIO0_S) & T6_SRAM_PRIO0_M)
2459
2460#define T6_SRAM_VLD_S 13
2461#define T6_SRAM_VLD_V(x) ((x) << T6_SRAM_VLD_S)
2462#define T6_SRAM_VLD_F T6_SRAM_VLD_V(1U)
2463
2464#define T6_REPLICATE_S 12
2465#define T6_REPLICATE_V(x) ((x) << T6_REPLICATE_S)
2466#define T6_REPLICATE_F T6_REPLICATE_V(1U)
2467
2468#define T6_PF_S 9
2469#define T6_PF_M 0x7U
2470#define T6_PF_G(x) (((x) >> T6_PF_S) & T6_PF_M)
2471
2472#define T6_VF_VALID_S 8
2473#define T6_VF_VALID_V(x) ((x) << T6_VF_VALID_S)
2474#define T6_VF_VALID_F T6_VF_VALID_V(1U)
2475
2476#define T6_VF_S 0
2477#define T6_VF_M 0xffU
2478#define T6_VF_G(x) (((x) >> T6_VF_S) & T6_VF_M)
2479
2480#define MPS_CLS_SRAM_H_A 0xe004
2481
2482#define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8)
2483#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
2484
2485#define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8)
2486#define NUM_MPS_CLS_SRAM_H_INSTANCES 336
2487
2488#define MULTILISTEN0_S 25
2489
2490#define REPLICATE_S 11
2491#define REPLICATE_V(x) ((x) << REPLICATE_S)
2492#define REPLICATE_F REPLICATE_V(1U)
2493
2494#define PF_S 8
2495#define PF_M 0x7U
2496#define PF_G(x) (((x) >> PF_S) & PF_M)
2497
2498#define VF_VALID_S 7
2499#define VF_VALID_V(x) ((x) << VF_VALID_S)
2500#define VF_VALID_F VF_VALID_V(1U)
2501
2502#define VF_S 0
2503#define VF_M 0x7fU
2504#define VF_G(x) (((x) >> VF_S) & VF_M)
2505
2506#define SRAM_PRIO3_S 22
2507#define SRAM_PRIO3_M 0x7U
2508#define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M)
2509
2510#define SRAM_PRIO2_S 19
2511#define SRAM_PRIO2_M 0x7U
2512#define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M)
2513
2514#define SRAM_PRIO1_S 16
2515#define SRAM_PRIO1_M 0x7U
2516#define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M)
2517
2518#define SRAM_PRIO0_S 13
2519#define SRAM_PRIO0_M 0x7U
2520#define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M)
2521
2522#define SRAM_VLD_S 12
2523#define SRAM_VLD_V(x) ((x) << SRAM_VLD_S)
2524#define SRAM_VLD_F SRAM_VLD_V(1U)
2525
2526#define PORTMAP_S 0
2527#define PORTMAP_M 0xfU
2528#define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M)
2529
2530#define CPL_INTR_CAUSE_A 0x19054
2531
2532#define CIM_OP_MAP_PERR_S 5
2533#define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S)
2534#define CIM_OP_MAP_PERR_F CIM_OP_MAP_PERR_V(1U)
2535
2536#define CIM_OVFL_ERROR_S 4
2537#define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S)
2538#define CIM_OVFL_ERROR_F CIM_OVFL_ERROR_V(1U)
2539
2540#define TP_FRAMING_ERROR_S 3
2541#define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S)
2542#define TP_FRAMING_ERROR_F TP_FRAMING_ERROR_V(1U)
2543
2544#define SGE_FRAMING_ERROR_S 2
2545#define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S)
2546#define SGE_FRAMING_ERROR_F SGE_FRAMING_ERROR_V(1U)
2547
2548#define CIM_FRAMING_ERROR_S 1
2549#define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S)
2550#define CIM_FRAMING_ERROR_F CIM_FRAMING_ERROR_V(1U)
2551
2552#define ZERO_SWITCH_ERROR_S 0
2553#define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S)
2554#define ZERO_SWITCH_ERROR_F ZERO_SWITCH_ERROR_V(1U)
2555
2556#define SMB_INT_CAUSE_A 0x19090
2557
2558#define MSTTXFIFOPARINT_S 21
2559#define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S)
2560#define MSTTXFIFOPARINT_F MSTTXFIFOPARINT_V(1U)
2561
2562#define MSTRXFIFOPARINT_S 20
2563#define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S)
2564#define MSTRXFIFOPARINT_F MSTRXFIFOPARINT_V(1U)
2565
2566#define SLVFIFOPARINT_S 19
2567#define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S)
2568#define SLVFIFOPARINT_F SLVFIFOPARINT_V(1U)
2569
2570#define ULP_RX_INT_CAUSE_A 0x19158
2571#define ULP_RX_ISCSI_LLIMIT_A 0x1915c
2572#define ULP_RX_ISCSI_ULIMIT_A 0x19160
2573#define ULP_RX_ISCSI_TAGMASK_A 0x19164
2574#define ULP_RX_ISCSI_PSZ_A 0x19168
2575#define ULP_RX_TDDP_LLIMIT_A 0x1916c
2576#define ULP_RX_TDDP_ULIMIT_A 0x19170
2577#define ULP_RX_STAG_LLIMIT_A 0x1917c
2578#define ULP_RX_STAG_ULIMIT_A 0x19180
2579#define ULP_RX_RQ_LLIMIT_A 0x19184
2580#define ULP_RX_RQ_ULIMIT_A 0x19188
2581#define ULP_RX_PBL_LLIMIT_A 0x1918c
2582#define ULP_RX_PBL_ULIMIT_A 0x19190
2583#define ULP_RX_CTX_BASE_A 0x19194
2584#define ULP_RX_RQUDP_LLIMIT_A 0x191a4
2585#define ULP_RX_RQUDP_ULIMIT_A 0x191a8
2586#define ULP_RX_LA_CTL_A 0x1923c
2587#define ULP_RX_LA_RDPTR_A 0x19240
2588#define ULP_RX_LA_RDDATA_A 0x19244
2589#define ULP_RX_LA_WRPTR_A 0x19248
2590
2591#define HPZ3_S 24
2592#define HPZ3_V(x) ((x) << HPZ3_S)
2593
2594#define HPZ2_S 16
2595#define HPZ2_V(x) ((x) << HPZ2_S)
2596
2597#define HPZ1_S 8
2598#define HPZ1_V(x) ((x) << HPZ1_S)
2599
2600#define HPZ0_S 0
2601#define HPZ0_V(x) ((x) << HPZ0_S)
2602
2603#define ULP_RX_TDDP_PSZ_A 0x19178
2604
2605
2606#define SF_DATA_A 0x193f8
2607#define SF_OP_A 0x193fc
2608
2609#define SF_BUSY_S 31
2610#define SF_BUSY_V(x) ((x) << SF_BUSY_S)
2611#define SF_BUSY_F SF_BUSY_V(1U)
2612
2613#define SF_LOCK_S 4
2614#define SF_LOCK_V(x) ((x) << SF_LOCK_S)
2615#define SF_LOCK_F SF_LOCK_V(1U)
2616
2617#define SF_CONT_S 3
2618#define SF_CONT_V(x) ((x) << SF_CONT_S)
2619#define SF_CONT_F SF_CONT_V(1U)
2620
2621#define BYTECNT_S 1
2622#define BYTECNT_V(x) ((x) << BYTECNT_S)
2623
2624#define OP_S 0
2625#define OP_V(x) ((x) << OP_S)
2626#define OP_F OP_V(1U)
2627
2628#define PL_PF_INT_CAUSE_A 0x3c0
2629
2630#define PFSW_S 3
2631#define PFSW_V(x) ((x) << PFSW_S)
2632#define PFSW_F PFSW_V(1U)
2633
2634#define PFCIM_S 1
2635#define PFCIM_V(x) ((x) << PFCIM_S)
2636#define PFCIM_F PFCIM_V(1U)
2637
2638#define PL_PF_INT_ENABLE_A 0x3c4
2639#define PL_PF_CTL_A 0x3c8
2640
2641#define PL_WHOAMI_A 0x19400
2642
2643#define SOURCEPF_S 8
2644#define SOURCEPF_M 0x7U
2645#define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M)
2646
2647#define T6_SOURCEPF_S 9
2648#define T6_SOURCEPF_M 0x7U
2649#define T6_SOURCEPF_G(x) (((x) >> T6_SOURCEPF_S) & T6_SOURCEPF_M)
2650
2651#define PL_INT_CAUSE_A 0x1940c
2652
2653#define ULP_TX_S 27
2654#define ULP_TX_V(x) ((x) << ULP_TX_S)
2655#define ULP_TX_F ULP_TX_V(1U)
2656
2657#define SGE_S 26
2658#define SGE_V(x) ((x) << SGE_S)
2659#define SGE_F SGE_V(1U)
2660
2661#define CPL_SWITCH_S 24
2662#define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S)
2663#define CPL_SWITCH_F CPL_SWITCH_V(1U)
2664
2665#define ULP_RX_S 23
2666#define ULP_RX_V(x) ((x) << ULP_RX_S)
2667#define ULP_RX_F ULP_RX_V(1U)
2668
2669#define PM_RX_S 22
2670#define PM_RX_V(x) ((x) << PM_RX_S)
2671#define PM_RX_F PM_RX_V(1U)
2672
2673#define PM_TX_S 21
2674#define PM_TX_V(x) ((x) << PM_TX_S)
2675#define PM_TX_F PM_TX_V(1U)
2676
2677#define MA_S 20
2678#define MA_V(x) ((x) << MA_S)
2679#define MA_F MA_V(1U)
2680
2681#define TP_S 19
2682#define TP_V(x) ((x) << TP_S)
2683#define TP_F TP_V(1U)
2684
2685#define LE_S 18
2686#define LE_V(x) ((x) << LE_S)
2687#define LE_F LE_V(1U)
2688
2689#define EDC1_S 17
2690#define EDC1_V(x) ((x) << EDC1_S)
2691#define EDC1_F EDC1_V(1U)
2692
2693#define EDC0_S 16
2694#define EDC0_V(x) ((x) << EDC0_S)
2695#define EDC0_F EDC0_V(1U)
2696
2697#define MC_S 15
2698#define MC_V(x) ((x) << MC_S)
2699#define MC_F MC_V(1U)
2700
2701#define PCIE_S 14
2702#define PCIE_V(x) ((x) << PCIE_S)
2703#define PCIE_F PCIE_V(1U)
2704
2705#define XGMAC_KR1_S 12
2706#define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S)
2707#define XGMAC_KR1_F XGMAC_KR1_V(1U)
2708
2709#define XGMAC_KR0_S 11
2710#define XGMAC_KR0_V(x) ((x) << XGMAC_KR0_S)
2711#define XGMAC_KR0_F XGMAC_KR0_V(1U)
2712
2713#define XGMAC1_S 10
2714#define XGMAC1_V(x) ((x) << XGMAC1_S)
2715#define XGMAC1_F XGMAC1_V(1U)
2716
2717#define XGMAC0_S 9
2718#define XGMAC0_V(x) ((x) << XGMAC0_S)
2719#define XGMAC0_F XGMAC0_V(1U)
2720
2721#define SMB_S 8
2722#define SMB_V(x) ((x) << SMB_S)
2723#define SMB_F SMB_V(1U)
2724
2725#define SF_S 7
2726#define SF_V(x) ((x) << SF_S)
2727#define SF_F SF_V(1U)
2728
2729#define PL_S 6
2730#define PL_V(x) ((x) << PL_S)
2731#define PL_F PL_V(1U)
2732
2733#define NCSI_S 5
2734#define NCSI_V(x) ((x) << NCSI_S)
2735#define NCSI_F NCSI_V(1U)
2736
2737#define MPS_S 4
2738#define MPS_V(x) ((x) << MPS_S)
2739#define MPS_F MPS_V(1U)
2740
2741#define CIM_S 0
2742#define CIM_V(x) ((x) << CIM_S)
2743#define CIM_F CIM_V(1U)
2744
2745#define MC1_S 31
2746#define MC1_V(x) ((x) << MC1_S)
2747#define MC1_F MC1_V(1U)
2748
2749#define PL_INT_ENABLE_A 0x19410
2750#define PL_INT_MAP0_A 0x19414
2751#define PL_RST_A 0x19428
2752
2753#define PIORST_S 1
2754#define PIORST_V(x) ((x) << PIORST_S)
2755#define PIORST_F PIORST_V(1U)
2756
2757#define PIORSTMODE_S 0
2758#define PIORSTMODE_V(x) ((x) << PIORSTMODE_S)
2759#define PIORSTMODE_F PIORSTMODE_V(1U)
2760
2761#define PL_PL_INT_CAUSE_A 0x19430
2762
2763#define FATALPERR_S 4
2764#define FATALPERR_V(x) ((x) << FATALPERR_S)
2765#define FATALPERR_F FATALPERR_V(1U)
2766
2767#define PERRVFID_S 0
2768#define PERRVFID_V(x) ((x) << PERRVFID_S)
2769#define PERRVFID_F PERRVFID_V(1U)
2770
2771#define PL_REV_A 0x1943c
2772
2773#define REV_S 0
2774#define REV_M 0xfU
2775#define REV_V(x) ((x) << REV_S)
2776#define REV_G(x) (((x) >> REV_S) & REV_M)
2777
2778#define T6_UNKNOWNCMD_S 3
2779#define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)
2780#define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U)
2781
2782#define T6_LIP0_S 2
2783#define T6_LIP0_V(x) ((x) << T6_LIP0_S)
2784#define T6_LIP0_F T6_LIP0_V(1U)
2785
2786#define T6_LIPMISS_S 1
2787#define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S)
2788#define T6_LIPMISS_F T6_LIPMISS_V(1U)
2789
2790#define LE_DB_CONFIG_A 0x19c04
2791#define LE_DB_SERVER_INDEX_A 0x19c18
2792#define LE_DB_SRVR_START_INDEX_A 0x19c18
2793#define LE_DB_ACT_CNT_IPV4_A 0x19c20
2794#define LE_DB_ACT_CNT_IPV6_A 0x19c24
2795#define LE_DB_HASH_TID_BASE_A 0x19c30
2796#define LE_DB_HASH_TBL_BASE_ADDR_A 0x19c30
2797#define LE_DB_INT_CAUSE_A 0x19c3c
2798#define LE_DB_TID_HASHBASE_A 0x19df8
2799#define T6_LE_DB_HASH_TID_BASE_A 0x19df8
2800
2801#define HASHEN_S 20
2802#define HASHEN_V(x) ((x) << HASHEN_S)
2803#define HASHEN_F HASHEN_V(1U)
2804
2805#define REQQPARERR_S 16
2806#define REQQPARERR_V(x) ((x) << REQQPARERR_S)
2807#define REQQPARERR_F REQQPARERR_V(1U)
2808
2809#define UNKNOWNCMD_S 15
2810#define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S)
2811#define UNKNOWNCMD_F UNKNOWNCMD_V(1U)
2812
2813#define PARITYERR_S 6
2814#define PARITYERR_V(x) ((x) << PARITYERR_S)
2815#define PARITYERR_F PARITYERR_V(1U)
2816
2817#define LIPMISS_S 5
2818#define LIPMISS_V(x) ((x) << LIPMISS_S)
2819#define LIPMISS_F LIPMISS_V(1U)
2820
2821#define LIP0_S 4
2822#define LIP0_V(x) ((x) << LIP0_S)
2823#define LIP0_F LIP0_V(1U)
2824
2825#define BASEADDR_S 3
2826#define BASEADDR_M 0x1fffffffU
2827#define BASEADDR_G(x) (((x) >> BASEADDR_S) & BASEADDR_M)
2828
2829#define TCAMINTPERR_S 13
2830#define TCAMINTPERR_V(x) ((x) << TCAMINTPERR_S)
2831#define TCAMINTPERR_F TCAMINTPERR_V(1U)
2832
2833#define SSRAMINTPERR_S 10
2834#define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S)
2835#define SSRAMINTPERR_F SSRAMINTPERR_V(1U)
2836
2837#define NCSI_INT_CAUSE_A 0x1a0d8
2838
2839#define CIM_DM_PRTY_ERR_S 8
2840#define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S)
2841#define CIM_DM_PRTY_ERR_F CIM_DM_PRTY_ERR_V(1U)
2842
2843#define MPS_DM_PRTY_ERR_S 7
2844#define MPS_DM_PRTY_ERR_V(x) ((x) << MPS_DM_PRTY_ERR_S)
2845#define MPS_DM_PRTY_ERR_F MPS_DM_PRTY_ERR_V(1U)
2846
2847#define TXFIFO_PRTY_ERR_S 1
2848#define TXFIFO_PRTY_ERR_V(x) ((x) << TXFIFO_PRTY_ERR_S)
2849#define TXFIFO_PRTY_ERR_F TXFIFO_PRTY_ERR_V(1U)
2850
2851#define RXFIFO_PRTY_ERR_S 0
2852#define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S)
2853#define RXFIFO_PRTY_ERR_F RXFIFO_PRTY_ERR_V(1U)
2854
2855#define XGMAC_PORT_CFG2_A 0x1018
2856
2857#define PATEN_S 18
2858#define PATEN_V(x) ((x) << PATEN_S)
2859#define PATEN_F PATEN_V(1U)
2860
2861#define MAGICEN_S 17
2862#define MAGICEN_V(x) ((x) << MAGICEN_S)
2863#define MAGICEN_F MAGICEN_V(1U)
2864
2865#define XGMAC_PORT_MAGIC_MACID_LO 0x1024
2866#define XGMAC_PORT_MAGIC_MACID_HI 0x1028
2867
2868#define XGMAC_PORT_EPIO_DATA0_A 0x10c0
2869#define XGMAC_PORT_EPIO_DATA1_A 0x10c4
2870#define XGMAC_PORT_EPIO_DATA2_A 0x10c8
2871#define XGMAC_PORT_EPIO_DATA3_A 0x10cc
2872#define XGMAC_PORT_EPIO_OP_A 0x10d0
2873
2874#define EPIOWR_S 8
2875#define EPIOWR_V(x) ((x) << EPIOWR_S)
2876#define EPIOWR_F EPIOWR_V(1U)
2877
2878#define ADDRESS_S 0
2879#define ADDRESS_V(x) ((x) << ADDRESS_S)
2880
2881#define MAC_PORT_INT_CAUSE_A 0x8dc
2882#define XGMAC_PORT_INT_CAUSE_A 0x10dc
2883
2884#define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28
2885
2886#define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30
2887#define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34
2888
2889#define TX_MOD_QUEUE_REQ_MAP_S 0
2890#define TX_MOD_QUEUE_REQ_MAP_V(x) ((x) << TX_MOD_QUEUE_REQ_MAP_S)
2891
2892#define TX_MODQ_WEIGHT3_S 24
2893#define TX_MODQ_WEIGHT3_V(x) ((x) << TX_MODQ_WEIGHT3_S)
2894
2895#define TX_MODQ_WEIGHT2_S 16
2896#define TX_MODQ_WEIGHT2_V(x) ((x) << TX_MODQ_WEIGHT2_S)
2897
2898#define TX_MODQ_WEIGHT1_S 8
2899#define TX_MODQ_WEIGHT1_V(x) ((x) << TX_MODQ_WEIGHT1_S)
2900
2901#define TX_MODQ_WEIGHT0_S 0
2902#define TX_MODQ_WEIGHT0_V(x) ((x) << TX_MODQ_WEIGHT0_S)
2903
2904#define TP_TX_SCHED_HDR_A 0x23
2905#define TP_TX_SCHED_FIFO_A 0x24
2906#define TP_TX_SCHED_PCMD_A 0x25
2907
2908#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
2909#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
2910
2911#define T5_PORT0_BASE 0x30000
2912#define T5_PORT_STRIDE 0x4000
2913#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
2914#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
2915
2916#define MC_0_BASE_ADDR 0x40000
2917#define MC_1_BASE_ADDR 0x48000
2918#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
2919#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
2920
2921#define MC_P_BIST_CMD_A 0x41400
2922#define MC_P_BIST_CMD_ADDR_A 0x41404
2923#define MC_P_BIST_CMD_LEN_A 0x41408
2924#define MC_P_BIST_DATA_PATTERN_A 0x4140c
2925#define MC_P_BIST_STATUS_RDATA_A 0x41488
2926
2927#define EDC_T50_BASE_ADDR 0x50000
2928
2929#define EDC_H_BIST_CMD_A 0x50004
2930#define EDC_H_BIST_CMD_ADDR_A 0x50008
2931#define EDC_H_BIST_CMD_LEN_A 0x5000c
2932#define EDC_H_BIST_DATA_PATTERN_A 0x50010
2933#define EDC_H_BIST_STATUS_RDATA_A 0x50028
2934
2935#define EDC_H_ECC_ERR_ADDR_A 0x50084
2936#define EDC_T51_BASE_ADDR 0x50800
2937
2938#define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
2939#define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
2940
2941#define PL_VF_REV_A 0x4
2942#define PL_VF_WHOAMI_A 0x0
2943#define PL_VF_REVISION_A 0x8
2944
2945
2946#define CIM_HOST_ACC_CTRL_A 0x7b50
2947#define CIM_HOST_ACC_DATA_A 0x7b54
2948#define UP_UP_DBG_LA_CFG_A 0x140
2949#define UP_UP_DBG_LA_DATA_A 0x144
2950
2951#define HOSTBUSY_S 17
2952#define HOSTBUSY_V(x) ((x) << HOSTBUSY_S)
2953#define HOSTBUSY_F HOSTBUSY_V(1U)
2954
2955#define HOSTWRITE_S 16
2956#define HOSTWRITE_V(x) ((x) << HOSTWRITE_S)
2957#define HOSTWRITE_F HOSTWRITE_V(1U)
2958
2959#define CIM_IBQ_DBG_CFG_A 0x7b60
2960
2961#define IBQDBGADDR_S 16
2962#define IBQDBGADDR_M 0xfffU
2963#define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S)
2964#define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M)
2965
2966#define IBQDBGBUSY_S 1
2967#define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S)
2968#define IBQDBGBUSY_F IBQDBGBUSY_V(1U)
2969
2970#define IBQDBGEN_S 0
2971#define IBQDBGEN_V(x) ((x) << IBQDBGEN_S)
2972#define IBQDBGEN_F IBQDBGEN_V(1U)
2973
2974#define CIM_OBQ_DBG_CFG_A 0x7b64
2975
2976#define OBQDBGADDR_S 16
2977#define OBQDBGADDR_M 0xfffU
2978#define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S)
2979#define OBQDBGADDR_G(x) (((x) >> OBQDBGADDR_S) & OBQDBGADDR_M)
2980
2981#define OBQDBGBUSY_S 1
2982#define OBQDBGBUSY_V(x) ((x) << OBQDBGBUSY_S)
2983#define OBQDBGBUSY_F OBQDBGBUSY_V(1U)
2984
2985#define OBQDBGEN_S 0
2986#define OBQDBGEN_V(x) ((x) << OBQDBGEN_S)
2987#define OBQDBGEN_F OBQDBGEN_V(1U)
2988
2989#define CIM_IBQ_DBG_DATA_A 0x7b68
2990#define CIM_OBQ_DBG_DATA_A 0x7b6c
2991#define CIM_DEBUGCFG_A 0x7b70
2992#define CIM_DEBUGSTS_A 0x7b74
2993
2994#define POLADBGRDPTR_S 23
2995#define POLADBGRDPTR_M 0x1ffU
2996#define POLADBGRDPTR_V(x) ((x) << POLADBGRDPTR_S)
2997
2998#define POLADBGWRPTR_S 16
2999#define POLADBGWRPTR_M 0x1ffU
3000#define POLADBGWRPTR_G(x) (((x) >> POLADBGWRPTR_S) & POLADBGWRPTR_M)
3001
3002#define PILADBGRDPTR_S 14
3003#define PILADBGRDPTR_M 0x1ffU
3004#define PILADBGRDPTR_V(x) ((x) << PILADBGRDPTR_S)
3005
3006#define PILADBGWRPTR_S 0
3007#define PILADBGWRPTR_M 0x1ffU
3008#define PILADBGWRPTR_G(x) (((x) >> PILADBGWRPTR_S) & PILADBGWRPTR_M)
3009
3010#define LADBGEN_S 12
3011#define LADBGEN_V(x) ((x) << LADBGEN_S)
3012#define LADBGEN_F LADBGEN_V(1U)
3013
3014#define CIM_PO_LA_DEBUGDATA_A 0x7b78
3015#define CIM_PI_LA_DEBUGDATA_A 0x7b7c
3016#define CIM_PO_LA_MADEBUGDATA_A 0x7b80
3017#define CIM_PI_LA_MADEBUGDATA_A 0x7b84
3018
3019#define UPDBGLARDEN_S 1
3020#define UPDBGLARDEN_V(x) ((x) << UPDBGLARDEN_S)
3021#define UPDBGLARDEN_F UPDBGLARDEN_V(1U)
3022
3023#define UPDBGLAEN_S 0
3024#define UPDBGLAEN_V(x) ((x) << UPDBGLAEN_S)
3025#define UPDBGLAEN_F UPDBGLAEN_V(1U)
3026
3027#define UPDBGLARDPTR_S 2
3028#define UPDBGLARDPTR_M 0xfffU
3029#define UPDBGLARDPTR_V(x) ((x) << UPDBGLARDPTR_S)
3030
3031#define UPDBGLAWRPTR_S 16
3032#define UPDBGLAWRPTR_M 0xfffU
3033#define UPDBGLAWRPTR_G(x) (((x) >> UPDBGLAWRPTR_S) & UPDBGLAWRPTR_M)
3034
3035#define UPDBGLACAPTPCONLY_S 30
3036#define UPDBGLACAPTPCONLY_V(x) ((x) << UPDBGLACAPTPCONLY_S)
3037#define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U)
3038
3039#define CIM_QUEUE_CONFIG_REF_A 0x7b48
3040#define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
3041
3042#define CIMQSIZE_S 24
3043#define CIMQSIZE_M 0x3fU
3044#define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M)
3045
3046#define CIMQBASE_S 16
3047#define CIMQBASE_M 0x3fU
3048#define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M)
3049
3050#define QUEFULLTHRSH_S 0
3051#define QUEFULLTHRSH_M 0x1ffU
3052#define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M)
3053
3054#define UP_IBQ_0_RDADDR_A 0x10
3055#define UP_IBQ_0_SHADOW_RDADDR_A 0x280
3056#define UP_OBQ_0_REALADDR_A 0x104
3057#define UP_OBQ_0_SHADOW_REALADDR_A 0x394
3058
3059#define IBQRDADDR_S 0
3060#define IBQRDADDR_M 0x1fffU
3061#define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M)
3062
3063#define IBQWRADDR_S 0
3064#define IBQWRADDR_M 0x1fffU
3065#define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M)
3066
3067#define QUERDADDR_S 0
3068#define QUERDADDR_M 0x7fffU
3069#define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M)
3070
3071#define QUEREMFLITS_S 0
3072#define QUEREMFLITS_M 0x7ffU
3073#define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M)
3074
3075#define QUEEOPCNT_S 16
3076#define QUEEOPCNT_M 0xfffU
3077#define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M)
3078
3079#define QUESOPCNT_S 0
3080#define QUESOPCNT_M 0xfffU
3081#define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M)
3082
3083#define OBQSELECT_S 4
3084#define OBQSELECT_V(x) ((x) << OBQSELECT_S)
3085#define OBQSELECT_F OBQSELECT_V(1U)
3086
3087#define IBQSELECT_S 3
3088#define IBQSELECT_V(x) ((x) << IBQSELECT_S)
3089#define IBQSELECT_F IBQSELECT_V(1U)
3090
3091#define QUENUMSELECT_S 0
3092#define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S)
3093
3094#endif
3095