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12#ifndef FEC_H
13#define FEC_H
14
15
16#include <linux/clocksource.h>
17#include <linux/net_tstamp.h>
18#include <linux/ptp_clock_kernel.h>
19#include <linux/timecounter.h>
20
21#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
22 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
23 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
24
25
26
27
28
29#define FEC_IEVENT 0x004
30#define FEC_IMASK 0x008
31#define FEC_R_DES_ACTIVE_0 0x010
32#define FEC_X_DES_ACTIVE_0 0x014
33#define FEC_ECNTRL 0x024
34#define FEC_MII_DATA 0x040
35#define FEC_MII_SPEED 0x044
36#define FEC_MIB_CTRLSTAT 0x064
37#define FEC_R_CNTRL 0x084
38#define FEC_X_CNTRL 0x0c4
39#define FEC_ADDR_LOW 0x0e4
40#define FEC_ADDR_HIGH 0x0e8
41#define FEC_OPD 0x0ec
42#define FEC_TXIC0 0x0f0
43#define FEC_TXIC1 0x0f4
44#define FEC_TXIC2 0x0f8
45#define FEC_RXIC0 0x100
46#define FEC_RXIC1 0x104
47#define FEC_RXIC2 0x108
48#define FEC_HASH_TABLE_HIGH 0x118
49#define FEC_HASH_TABLE_LOW 0x11c
50#define FEC_GRP_HASH_TABLE_HIGH 0x120
51#define FEC_GRP_HASH_TABLE_LOW 0x124
52#define FEC_X_WMRK 0x144
53#define FEC_R_BOUND 0x14c
54#define FEC_R_FSTART 0x150
55#define FEC_R_DES_START_1 0x160
56#define FEC_X_DES_START_1 0x164
57#define FEC_R_BUFF_SIZE_1 0x168
58#define FEC_R_DES_START_2 0x16c
59#define FEC_X_DES_START_2 0x170
60#define FEC_R_BUFF_SIZE_2 0x174
61#define FEC_R_DES_START_0 0x180
62#define FEC_X_DES_START_0 0x184
63#define FEC_R_BUFF_SIZE_0 0x188
64#define FEC_R_FIFO_RSFL 0x190
65#define FEC_R_FIFO_RSEM 0x194
66#define FEC_R_FIFO_RAEM 0x198
67#define FEC_R_FIFO_RAFL 0x19c
68#define FEC_RACC 0x1c4
69#define FEC_RCMR_1 0x1c8
70#define FEC_RCMR_2 0x1cc
71#define FEC_DMA_CFG_1 0x1d8
72#define FEC_DMA_CFG_2 0x1dc
73#define FEC_R_DES_ACTIVE_1 0x1e0
74#define FEC_X_DES_ACTIVE_1 0x1e4
75#define FEC_R_DES_ACTIVE_2 0x1e8
76#define FEC_X_DES_ACTIVE_2 0x1ec
77#define FEC_QOS_SCHEME 0x1f0
78#define FEC_MIIGSK_CFGR 0x300
79#define FEC_MIIGSK_ENR 0x308
80
81#define BM_MIIGSK_CFGR_MII 0x00
82#define BM_MIIGSK_CFGR_RMII 0x01
83#define BM_MIIGSK_CFGR_FRCONT_10M 0x40
84
85#define RMON_T_DROP 0x200
86#define RMON_T_PACKETS 0x204
87#define RMON_T_BC_PKT 0x208
88#define RMON_T_MC_PKT 0x20c
89#define RMON_T_CRC_ALIGN 0x210
90#define RMON_T_UNDERSIZE 0x214
91#define RMON_T_OVERSIZE 0x218
92#define RMON_T_FRAG 0x21c
93#define RMON_T_JAB 0x220
94#define RMON_T_COL 0x224
95#define RMON_T_P64 0x228
96#define RMON_T_P65TO127 0x22c
97#define RMON_T_P128TO255 0x230
98#define RMON_T_P256TO511 0x234
99#define RMON_T_P512TO1023 0x238
100#define RMON_T_P1024TO2047 0x23c
101#define RMON_T_P_GTE2048 0x240
102#define RMON_T_OCTETS 0x244
103#define IEEE_T_DROP 0x248
104#define IEEE_T_FRAME_OK 0x24c
105#define IEEE_T_1COL 0x250
106#define IEEE_T_MCOL 0x254
107#define IEEE_T_DEF 0x258
108#define IEEE_T_LCOL 0x25c
109#define IEEE_T_EXCOL 0x260
110#define IEEE_T_MACERR 0x264
111#define IEEE_T_CSERR 0x268
112#define IEEE_T_SQE 0x26c
113#define IEEE_T_FDXFC 0x270
114#define IEEE_T_OCTETS_OK 0x274
115#define RMON_R_PACKETS 0x284
116#define RMON_R_BC_PKT 0x288
117#define RMON_R_MC_PKT 0x28c
118#define RMON_R_CRC_ALIGN 0x290
119#define RMON_R_UNDERSIZE 0x294
120#define RMON_R_OVERSIZE 0x298
121#define RMON_R_FRAG 0x29c
122#define RMON_R_JAB 0x2a0
123#define RMON_R_RESVD_O 0x2a4
124#define RMON_R_P64 0x2a8
125#define RMON_R_P65TO127 0x2ac
126#define RMON_R_P128TO255 0x2b0
127#define RMON_R_P256TO511 0x2b4
128#define RMON_R_P512TO1023 0x2b8
129#define RMON_R_P1024TO2047 0x2bc
130#define RMON_R_P_GTE2048 0x2c0
131#define RMON_R_OCTETS 0x2c4
132#define IEEE_R_DROP 0x2c8
133#define IEEE_R_FRAME_OK 0x2cc
134#define IEEE_R_CRC 0x2d0
135#define IEEE_R_ALIGN 0x2d4
136#define IEEE_R_MACERR 0x2d8
137#define IEEE_R_FDXFC 0x2dc
138#define IEEE_R_OCTETS_OK 0x2e0
139
140#else
141
142#define FEC_ECNTRL 0x000
143#define FEC_IEVENT 0x004
144#define FEC_IMASK 0x008
145#define FEC_IVEC 0x00c
146#define FEC_R_DES_ACTIVE_0 0x010
147#define FEC_R_DES_ACTIVE_1 FEC_R_DES_ACTIVE_0
148#define FEC_R_DES_ACTIVE_2 FEC_R_DES_ACTIVE_0
149#define FEC_X_DES_ACTIVE_0 0x014
150#define FEC_X_DES_ACTIVE_1 FEC_X_DES_ACTIVE_0
151#define FEC_X_DES_ACTIVE_2 FEC_X_DES_ACTIVE_0
152#define FEC_MII_DATA 0x040
153#define FEC_MII_SPEED 0x044
154#define FEC_R_BOUND 0x08c
155#define FEC_R_FSTART 0x090
156#define FEC_X_WMRK 0x0a4
157#define FEC_X_FSTART 0x0ac
158#define FEC_R_CNTRL 0x104
159#define FEC_MAX_FRM_LEN 0x108
160#define FEC_X_CNTRL 0x144
161#define FEC_ADDR_LOW 0x3c0
162#define FEC_ADDR_HIGH 0x3c4
163#define FEC_GRP_HASH_TABLE_HIGH 0x3c8
164#define FEC_GRP_HASH_TABLE_LOW 0x3cc
165#define FEC_R_DES_START_0 0x3d0
166#define FEC_R_DES_START_1 FEC_R_DES_START_0
167#define FEC_R_DES_START_2 FEC_R_DES_START_0
168#define FEC_X_DES_START_0 0x3d4
169#define FEC_X_DES_START_1 FEC_X_DES_START_0
170#define FEC_X_DES_START_2 FEC_X_DES_START_0
171#define FEC_R_BUFF_SIZE_0 0x3d8
172#define FEC_R_BUFF_SIZE_1 FEC_R_BUFF_SIZE_0
173#define FEC_R_BUFF_SIZE_2 FEC_R_BUFF_SIZE_0
174#define FEC_FIFO_RAM 0x400
175
176
177
178#define FEC_RCMR_1 0xfff
179#define FEC_RCMR_2 0xfff
180#define FEC_DMA_CFG_1 0xfff
181#define FEC_DMA_CFG_2 0xfff
182#define FEC_TXIC0 0xfff
183#define FEC_TXIC1 0xfff
184#define FEC_TXIC2 0xfff
185#define FEC_RXIC0 0xfff
186#define FEC_RXIC1 0xfff
187#define FEC_RXIC2 0xfff
188#endif
189
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192
193
194#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
195struct bufdesc {
196 unsigned short cbd_datlen;
197 unsigned short cbd_sc;
198 unsigned long cbd_bufaddr;
199};
200#else
201struct bufdesc {
202 unsigned short cbd_sc;
203 unsigned short cbd_datlen;
204 unsigned long cbd_bufaddr;
205};
206#endif
207
208struct bufdesc_ex {
209 struct bufdesc desc;
210 unsigned long cbd_esc;
211 unsigned long cbd_prot;
212 unsigned long cbd_bdu;
213 unsigned long ts;
214 unsigned short res0[4];
215};
216
217
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219
220
221#define BD_SC_EMPTY ((ushort)0x8000)
222#define BD_SC_READY ((ushort)0x8000)
223#define BD_SC_WRAP ((ushort)0x2000)
224#define BD_SC_INTRPT ((ushort)0x1000)
225#define BD_SC_CM ((ushort)0x0200)
226#define BD_SC_ID ((ushort)0x0100)
227#define BD_SC_P ((ushort)0x0100)
228#define BD_SC_BR ((ushort)0x0020)
229#define BD_SC_FR ((ushort)0x0010)
230#define BD_SC_PR ((ushort)0x0008)
231#define BD_SC_OV ((ushort)0x0002)
232#define BD_SC_CD ((ushort)0x0001)
233
234
235
236#define BD_ENET_RX_EMPTY ((ushort)0x8000)
237#define BD_ENET_RX_WRAP ((ushort)0x2000)
238#define BD_ENET_RX_INTR ((ushort)0x1000)
239#define BD_ENET_RX_LAST ((ushort)0x0800)
240#define BD_ENET_RX_FIRST ((ushort)0x0400)
241#define BD_ENET_RX_MISS ((ushort)0x0100)
242#define BD_ENET_RX_LG ((ushort)0x0020)
243#define BD_ENET_RX_NO ((ushort)0x0010)
244#define BD_ENET_RX_SH ((ushort)0x0008)
245#define BD_ENET_RX_CR ((ushort)0x0004)
246#define BD_ENET_RX_OV ((ushort)0x0002)
247#define BD_ENET_RX_CL ((ushort)0x0001)
248#define BD_ENET_RX_STATS ((ushort)0x013f)
249
250
251#define BD_ENET_RX_VLAN 0x00000004
252
253
254
255#define BD_ENET_TX_READY ((ushort)0x8000)
256#define BD_ENET_TX_PAD ((ushort)0x4000)
257#define BD_ENET_TX_WRAP ((ushort)0x2000)
258#define BD_ENET_TX_INTR ((ushort)0x1000)
259#define BD_ENET_TX_LAST ((ushort)0x0800)
260#define BD_ENET_TX_TC ((ushort)0x0400)
261#define BD_ENET_TX_DEF ((ushort)0x0200)
262#define BD_ENET_TX_HB ((ushort)0x0100)
263#define BD_ENET_TX_LC ((ushort)0x0080)
264#define BD_ENET_TX_RL ((ushort)0x0040)
265#define BD_ENET_TX_RCMASK ((ushort)0x003c)
266#define BD_ENET_TX_UN ((ushort)0x0002)
267#define BD_ENET_TX_CSL ((ushort)0x0001)
268#define BD_ENET_TX_STATS ((ushort)0x0fff)
269
270
271#define BD_ENET_TX_INT 0x40000000
272#define BD_ENET_TX_TS 0x20000000
273#define BD_ENET_TX_PINS 0x10000000
274#define BD_ENET_TX_IINS 0x08000000
275
276
277
278#define FEC_IRQ_NUM 3
279
280
281
282
283
284#define FEC_ENET_MAX_TX_QS 3
285#define FEC_ENET_MAX_RX_QS 3
286
287#define FEC_R_DES_START(X) (((X) == 1) ? FEC_R_DES_START_1 : \
288 (((X) == 2) ? \
289 FEC_R_DES_START_2 : FEC_R_DES_START_0))
290#define FEC_X_DES_START(X) (((X) == 1) ? FEC_X_DES_START_1 : \
291 (((X) == 2) ? \
292 FEC_X_DES_START_2 : FEC_X_DES_START_0))
293#define FEC_R_BUFF_SIZE(X) (((X) == 1) ? FEC_R_BUFF_SIZE_1 : \
294 (((X) == 2) ? \
295 FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0))
296#define FEC_R_DES_ACTIVE(X) (((X) == 1) ? FEC_R_DES_ACTIVE_1 : \
297 (((X) == 2) ? \
298 FEC_R_DES_ACTIVE_2 : FEC_R_DES_ACTIVE_0))
299#define FEC_X_DES_ACTIVE(X) (((X) == 1) ? FEC_X_DES_ACTIVE_1 : \
300 (((X) == 2) ? \
301 FEC_X_DES_ACTIVE_2 : FEC_X_DES_ACTIVE_0))
302
303#define FEC_DMA_CFG(X) (((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
304
305#define DMA_CLASS_EN (1 << 16)
306#define FEC_RCMR(X) (((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
307#define IDLE_SLOPE_MASK 0xffff
308#define IDLE_SLOPE_1 0x200
309#define IDLE_SLOPE_2 0x200
310#define IDLE_SLOPE(X) (((X) == 1) ? \
311 (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \
312 (IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
313#define RCMR_MATCHEN (0x1 << 16)
314#define RCMR_CMP_CFG(v, n) (((v) & 0x7) << (n << 2))
315#define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
316 RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
317#define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
318 RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
319#define RCMR_CMP(X) (((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
320#define FEC_TX_BD_FTYPE(X) (((X) & 0xf) << 20)
321
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328
329#define FEC_ENET_RX_PAGES 256
330#define FEC_ENET_RX_FRSIZE 2048
331#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
332#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
333#define FEC_ENET_TX_FRSIZE 2048
334#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
335#define TX_RING_SIZE 512
336#define TX_RING_MOD_MASK 511
337
338#define BD_ENET_RX_INT 0x00800000
339#define BD_ENET_RX_PTP ((ushort)0x0400)
340#define BD_ENET_RX_ICE 0x00000020
341#define BD_ENET_RX_PCR 0x00000010
342#define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
343#define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
344
345
346#define FEC_ENET_HBERR ((uint)0x80000000)
347#define FEC_ENET_BABR ((uint)0x40000000)
348#define FEC_ENET_BABT ((uint)0x20000000)
349#define FEC_ENET_GRA ((uint)0x10000000)
350#define FEC_ENET_TXF_0 ((uint)0x08000000)
351#define FEC_ENET_TXF_1 ((uint)0x00000008)
352#define FEC_ENET_TXF_2 ((uint)0x00000080)
353#define FEC_ENET_TXB ((uint)0x04000000)
354#define FEC_ENET_RXF_0 ((uint)0x02000000)
355#define FEC_ENET_RXF_1 ((uint)0x00000002)
356#define FEC_ENET_RXF_2 ((uint)0x00000020)
357#define FEC_ENET_RXB ((uint)0x01000000)
358#define FEC_ENET_MII ((uint)0x00800000)
359#define FEC_ENET_EBERR ((uint)0x00400000)
360#define FEC_ENET_WAKEUP ((uint)0x00020000)
361#define FEC_ENET_TXF (FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
362#define FEC_ENET_RXF (FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
363#define FEC_ENET_TS_AVAIL ((uint)0x00010000)
364#define FEC_ENET_TS_TIMER ((uint)0x00008000)
365
366#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII | FEC_ENET_TS_TIMER)
367#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
368
369
370#define FEC_ITR_CLK_SEL (0x1 << 30)
371#define FEC_ITR_EN (0x1 << 31)
372#define FEC_ITR_ICFT(X) (((X) & 0xff) << 20)
373#define FEC_ITR_ICTT(X) ((X) & 0xffff)
374#define FEC_ITR_ICFT_DEFAULT 200
375#define FEC_ITR_ICTT_DEFAULT 1000
376
377#define FEC_VLAN_TAG_LEN 0x04
378#define FEC_ETHTYPE_LEN 0x02
379
380
381#define FEC_QUIRK_ENET_MAC (1 << 0)
382
383#define FEC_QUIRK_SWAP_FRAME (1 << 1)
384
385#define FEC_QUIRK_USE_GASKET (1 << 2)
386
387#define FEC_QUIRK_HAS_GBIT (1 << 3)
388
389#define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
390
391#define FEC_QUIRK_HAS_CSUM (1 << 5)
392
393#define FEC_QUIRK_HAS_VLAN (1 << 6)
394
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401
402
403#define FEC_QUIRK_ERR006358 (1 << 7)
404
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411
412
413#define FEC_QUIRK_HAS_AVB (1 << 8)
414
415
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417
418
419#define FEC_QUIRK_ERR007885 (1 << 9)
420
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423
424
425
426
427
428#define FEC_QUIRK_BUG_CAPTURE (1 << 10)
429
430#define FEC_QUIRK_SINGLE_MDIO (1 << 11)
431
432#define FEC_QUIRK_HAS_RACC (1 << 12)
433
434struct fec_enet_priv_tx_q {
435 int index;
436 unsigned char *tx_bounce[TX_RING_SIZE];
437 struct sk_buff *tx_skbuff[TX_RING_SIZE];
438
439 dma_addr_t bd_dma;
440 struct bufdesc *tx_bd_base;
441 uint tx_ring_size;
442
443 unsigned short tx_stop_threshold;
444 unsigned short tx_wake_threshold;
445
446 struct bufdesc *cur_tx;
447 struct bufdesc *dirty_tx;
448 char *tso_hdrs;
449 dma_addr_t tso_hdrs_dma;
450};
451
452struct fec_enet_priv_rx_q {
453 int index;
454 struct sk_buff *rx_skbuff[RX_RING_SIZE];
455
456 dma_addr_t bd_dma;
457 struct bufdesc *rx_bd_base;
458 uint rx_ring_size;
459
460 struct bufdesc *cur_rx;
461};
462
463
464
465
466
467
468
469
470
471struct fec_enet_private {
472
473 void __iomem *hwp;
474
475 struct net_device *netdev;
476
477 struct clk *clk_ipg;
478 struct clk *clk_ahb;
479 struct clk *clk_ref;
480 struct clk *clk_enet_out;
481 struct clk *clk_ptp;
482
483 bool ptp_clk_on;
484 struct mutex ptp_clk_mutex;
485 unsigned int num_tx_queues;
486 unsigned int num_rx_queues;
487
488
489 struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
490 struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
491
492 unsigned int total_tx_ring_size;
493 unsigned int total_rx_ring_size;
494
495 unsigned long work_tx;
496 unsigned long work_rx;
497 unsigned long work_ts;
498 unsigned long work_mdio;
499
500 unsigned short bufdesc_size;
501
502 struct platform_device *pdev;
503
504 int dev_id;
505
506
507 struct mii_bus *mii_bus;
508 struct phy_device *phy_dev;
509 int mii_timeout;
510 uint phy_speed;
511 phy_interface_t phy_interface;
512 struct device_node *phy_node;
513 int link;
514 int full_duplex;
515 int speed;
516 struct completion mdio_done;
517 int irq[FEC_IRQ_NUM];
518 bool bufdesc_ex;
519 int pause_flag;
520 int wol_flag;
521 u32 quirks;
522
523 struct napi_struct napi;
524 int csum_flags;
525
526 struct work_struct tx_timeout_work;
527
528 struct ptp_clock *ptp_clock;
529 struct ptp_clock_info ptp_caps;
530 unsigned long last_overflow_check;
531 spinlock_t tmreg_lock;
532 struct cyclecounter cc;
533 struct timecounter tc;
534 int rx_hwtstamp_filter;
535 u32 base_incval;
536 u32 cycle_speed;
537 int hwts_rx_en;
538 int hwts_tx_en;
539 struct delayed_work time_keep;
540 struct regulator *reg_phy;
541
542 unsigned int tx_align;
543 unsigned int rx_align;
544
545
546 unsigned int rx_pkts_itr;
547 unsigned int rx_time_itr;
548 unsigned int tx_pkts_itr;
549 unsigned int tx_time_itr;
550 unsigned int itr_clk_rate;
551
552 u32 rx_copybreak;
553
554
555 unsigned int ptp_inc;
556
557
558 int pps_channel;
559 unsigned int reload_period;
560 int pps_enable;
561 unsigned int next_counter;
562};
563
564void fec_ptp_init(struct platform_device *pdev);
565void fec_ptp_stop(struct platform_device *pdev);
566void fec_ptp_start_cyclecounter(struct net_device *ndev);
567int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr);
568int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr);
569uint fec_ptp_check_pps_event(struct fec_enet_private *fep);
570
571
572#endif
573