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21
22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
24#include <linux/module.h>
25#include <linux/types.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/vmalloc.h>
29#include <linux/pagemap.h>
30#include <linux/delay.h>
31#include <linux/netdevice.h>
32#include <linux/interrupt.h>
33#include <linux/tcp.h>
34#include <linux/ipv6.h>
35#include <linux/slab.h>
36#include <net/checksum.h>
37#include <net/ip6_checksum.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/cpu.h>
41#include <linux/smp.h>
42#include <linux/pm_qos.h>
43#include <linux/pm_runtime.h>
44#include <linux/aer.h>
45#include <linux/prefetch.h>
46
47#include "e1000.h"
48
49#define DRV_EXTRAVERSION "-k"
50
51#define DRV_VERSION "3.2.6" DRV_EXTRAVERSION
52char e1000e_driver_name[] = "e1000e";
53const char e1000e_driver_version[] = DRV_VERSION;
54
55#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
56static int debug = -1;
57module_param(debug, int, 0);
58MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
60static const struct e1000_info *e1000_info_tbl[] = {
61 [board_82571] = &e1000_82571_info,
62 [board_82572] = &e1000_82572_info,
63 [board_82573] = &e1000_82573_info,
64 [board_82574] = &e1000_82574_info,
65 [board_82583] = &e1000_82583_info,
66 [board_80003es2lan] = &e1000_es2_info,
67 [board_ich8lan] = &e1000_ich8_info,
68 [board_ich9lan] = &e1000_ich9_info,
69 [board_ich10lan] = &e1000_ich10_info,
70 [board_pchlan] = &e1000_pch_info,
71 [board_pch2lan] = &e1000_pch2_info,
72 [board_pch_lpt] = &e1000_pch_lpt_info,
73 [board_pch_spt] = &e1000_pch_spt_info,
74};
75
76struct e1000_reg_info {
77 u32 ofs;
78 char *name;
79};
80
81static const struct e1000_reg_info e1000_reg_info_tbl[] = {
82
83 {E1000_CTRL, "CTRL"},
84 {E1000_STATUS, "STATUS"},
85 {E1000_CTRL_EXT, "CTRL_EXT"},
86
87
88 {E1000_ICR, "ICR"},
89
90
91 {E1000_RCTL, "RCTL"},
92 {E1000_RDLEN(0), "RDLEN"},
93 {E1000_RDH(0), "RDH"},
94 {E1000_RDT(0), "RDT"},
95 {E1000_RDTR, "RDTR"},
96 {E1000_RXDCTL(0), "RXDCTL"},
97 {E1000_ERT, "ERT"},
98 {E1000_RDBAL(0), "RDBAL"},
99 {E1000_RDBAH(0), "RDBAH"},
100 {E1000_RDFH, "RDFH"},
101 {E1000_RDFT, "RDFT"},
102 {E1000_RDFHS, "RDFHS"},
103 {E1000_RDFTS, "RDFTS"},
104 {E1000_RDFPC, "RDFPC"},
105
106
107 {E1000_TCTL, "TCTL"},
108 {E1000_TDBAL(0), "TDBAL"},
109 {E1000_TDBAH(0), "TDBAH"},
110 {E1000_TDLEN(0), "TDLEN"},
111 {E1000_TDH(0), "TDH"},
112 {E1000_TDT(0), "TDT"},
113 {E1000_TIDV, "TIDV"},
114 {E1000_TXDCTL(0), "TXDCTL"},
115 {E1000_TADV, "TADV"},
116 {E1000_TARC(0), "TARC"},
117 {E1000_TDFH, "TDFH"},
118 {E1000_TDFT, "TDFT"},
119 {E1000_TDFHS, "TDFHS"},
120 {E1000_TDFTS, "TDFTS"},
121 {E1000_TDFPC, "TDFPC"},
122
123
124 {0, NULL}
125};
126
127
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136
137
138
139s32 __ew32_prepare(struct e1000_hw *hw)
140{
141 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
142
143 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
144 udelay(50);
145
146 return i;
147}
148
149void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
150{
151 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
152 __ew32_prepare(hw);
153
154 writel(val, hw->hw_addr + reg);
155}
156
157
158
159
160
161
162static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
163{
164 int n = 0;
165 char rname[16];
166 u32 regs[8];
167
168 switch (reginfo->ofs) {
169 case E1000_RXDCTL(0):
170 for (n = 0; n < 2; n++)
171 regs[n] = __er32(hw, E1000_RXDCTL(n));
172 break;
173 case E1000_TXDCTL(0):
174 for (n = 0; n < 2; n++)
175 regs[n] = __er32(hw, E1000_TXDCTL(n));
176 break;
177 case E1000_TARC(0):
178 for (n = 0; n < 2; n++)
179 regs[n] = __er32(hw, E1000_TARC(n));
180 break;
181 default:
182 pr_info("%-15s %08x\n",
183 reginfo->name, __er32(hw, reginfo->ofs));
184 return;
185 }
186
187 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
188 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
189}
190
191static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
192 struct e1000_buffer *bi)
193{
194 int i;
195 struct e1000_ps_page *ps_page;
196
197 for (i = 0; i < adapter->rx_ps_pages; i++) {
198 ps_page = &bi->ps_pages[i];
199
200 if (ps_page->page) {
201 pr_info("packet dump for ps_page %d:\n", i);
202 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
203 16, 1, page_address(ps_page->page),
204 PAGE_SIZE, true);
205 }
206 }
207}
208
209
210
211
212
213static void e1000e_dump(struct e1000_adapter *adapter)
214{
215 struct net_device *netdev = adapter->netdev;
216 struct e1000_hw *hw = &adapter->hw;
217 struct e1000_reg_info *reginfo;
218 struct e1000_ring *tx_ring = adapter->tx_ring;
219 struct e1000_tx_desc *tx_desc;
220 struct my_u0 {
221 __le64 a;
222 __le64 b;
223 } *u0;
224 struct e1000_buffer *buffer_info;
225 struct e1000_ring *rx_ring = adapter->rx_ring;
226 union e1000_rx_desc_packet_split *rx_desc_ps;
227 union e1000_rx_desc_extended *rx_desc;
228 struct my_u1 {
229 __le64 a;
230 __le64 b;
231 __le64 c;
232 __le64 d;
233 } *u1;
234 u32 staterr;
235 int i = 0;
236
237 if (!netif_msg_hw(adapter))
238 return;
239
240
241 if (netdev) {
242 dev_info(&adapter->pdev->dev, "Net device Info\n");
243 pr_info("Device Name state trans_start last_rx\n");
244 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
245 netdev->state, netdev->trans_start, netdev->last_rx);
246 }
247
248
249 dev_info(&adapter->pdev->dev, "Register Dump\n");
250 pr_info(" Register Name Value\n");
251 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
252 reginfo->name; reginfo++) {
253 e1000_regdump(hw, reginfo);
254 }
255
256
257 if (!netdev || !netif_running(netdev))
258 return;
259
260 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
261 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
262 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
263 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
264 0, tx_ring->next_to_use, tx_ring->next_to_clean,
265 (unsigned long long)buffer_info->dma,
266 buffer_info->length,
267 buffer_info->next_to_watch,
268 (unsigned long long)buffer_info->time_stamp);
269
270
271 if (!netif_msg_tx_done(adapter))
272 goto rx_ring_summary;
273
274 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
275
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302
303 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
304 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
305 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
306 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
307 const char *next_desc;
308 tx_desc = E1000_TX_DESC(*tx_ring, i);
309 buffer_info = &tx_ring->buffer_info[i];
310 u0 = (struct my_u0 *)tx_desc;
311 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
312 next_desc = " NTC/U";
313 else if (i == tx_ring->next_to_use)
314 next_desc = " NTU";
315 else if (i == tx_ring->next_to_clean)
316 next_desc = " NTC";
317 else
318 next_desc = "";
319 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
320 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
321 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
322 i,
323 (unsigned long long)le64_to_cpu(u0->a),
324 (unsigned long long)le64_to_cpu(u0->b),
325 (unsigned long long)buffer_info->dma,
326 buffer_info->length, buffer_info->next_to_watch,
327 (unsigned long long)buffer_info->time_stamp,
328 buffer_info->skb, next_desc);
329
330 if (netif_msg_pktdata(adapter) && buffer_info->skb)
331 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
332 16, 1, buffer_info->skb->data,
333 buffer_info->skb->len, true);
334 }
335
336
337rx_ring_summary:
338 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
339 pr_info("Queue [NTU] [NTC]\n");
340 pr_info(" %5d %5X %5X\n",
341 0, rx_ring->next_to_use, rx_ring->next_to_clean);
342
343
344 if (!netif_msg_rx_status(adapter))
345 return;
346
347 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
348 switch (adapter->rx_ps_pages) {
349 case 1:
350 case 2:
351 case 3:
352
353
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362
363
364 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
365
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375
376 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
377 for (i = 0; i < rx_ring->count; i++) {
378 const char *next_desc;
379 buffer_info = &rx_ring->buffer_info[i];
380 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
381 u1 = (struct my_u1 *)rx_desc_ps;
382 staterr =
383 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
384
385 if (i == rx_ring->next_to_use)
386 next_desc = " NTU";
387 else if (i == rx_ring->next_to_clean)
388 next_desc = " NTC";
389 else
390 next_desc = "";
391
392 if (staterr & E1000_RXD_STAT_DD) {
393
394 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
395 "RWB", i,
396 (unsigned long long)le64_to_cpu(u1->a),
397 (unsigned long long)le64_to_cpu(u1->b),
398 (unsigned long long)le64_to_cpu(u1->c),
399 (unsigned long long)le64_to_cpu(u1->d),
400 buffer_info->skb, next_desc);
401 } else {
402 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
403 "R ", i,
404 (unsigned long long)le64_to_cpu(u1->a),
405 (unsigned long long)le64_to_cpu(u1->b),
406 (unsigned long long)le64_to_cpu(u1->c),
407 (unsigned long long)le64_to_cpu(u1->d),
408 (unsigned long long)buffer_info->dma,
409 buffer_info->skb, next_desc);
410
411 if (netif_msg_pktdata(adapter))
412 e1000e_dump_ps_pages(adapter,
413 buffer_info);
414 }
415 }
416 break;
417 default:
418 case 0:
419
420
421
422
423
424
425
426
427 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
428
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439
440
441 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
442
443 for (i = 0; i < rx_ring->count; i++) {
444 const char *next_desc;
445
446 buffer_info = &rx_ring->buffer_info[i];
447 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
448 u1 = (struct my_u1 *)rx_desc;
449 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
450
451 if (i == rx_ring->next_to_use)
452 next_desc = " NTU";
453 else if (i == rx_ring->next_to_clean)
454 next_desc = " NTC";
455 else
456 next_desc = "";
457
458 if (staterr & E1000_RXD_STAT_DD) {
459
460 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
461 "RWB", i,
462 (unsigned long long)le64_to_cpu(u1->a),
463 (unsigned long long)le64_to_cpu(u1->b),
464 buffer_info->skb, next_desc);
465 } else {
466 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
467 "R ", i,
468 (unsigned long long)le64_to_cpu(u1->a),
469 (unsigned long long)le64_to_cpu(u1->b),
470 (unsigned long long)buffer_info->dma,
471 buffer_info->skb, next_desc);
472
473 if (netif_msg_pktdata(adapter) &&
474 buffer_info->skb)
475 print_hex_dump(KERN_INFO, "",
476 DUMP_PREFIX_ADDRESS, 16,
477 1,
478 buffer_info->skb->data,
479 adapter->rx_buffer_len,
480 true);
481 }
482 }
483 }
484}
485
486
487
488
489static int e1000_desc_unused(struct e1000_ring *ring)
490{
491 if (ring->next_to_clean > ring->next_to_use)
492 return ring->next_to_clean - ring->next_to_use - 1;
493
494 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
495}
496
497
498
499
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502
503
504
505
506
507
508
509
510
511static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
512 struct skb_shared_hwtstamps *hwtstamps,
513 u64 systim)
514{
515 u64 ns;
516 unsigned long flags;
517
518 spin_lock_irqsave(&adapter->systim_lock, flags);
519 ns = timecounter_cyc2time(&adapter->tc, systim);
520 spin_unlock_irqrestore(&adapter->systim_lock, flags);
521
522 memset(hwtstamps, 0, sizeof(*hwtstamps));
523 hwtstamps->hwtstamp = ns_to_ktime(ns);
524}
525
526
527
528
529
530
531
532
533
534
535
536static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
537 struct sk_buff *skb)
538{
539 struct e1000_hw *hw = &adapter->hw;
540 u64 rxstmp;
541
542 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
543 !(status & E1000_RXDEXT_STATERR_TST) ||
544 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
545 return;
546
547
548
549
550
551
552
553
554 rxstmp = (u64)er32(RXSTMPL);
555 rxstmp |= (u64)er32(RXSTMPH) << 32;
556 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
557
558 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
559}
560
561
562
563
564
565
566
567
568static void e1000_receive_skb(struct e1000_adapter *adapter,
569 struct net_device *netdev, struct sk_buff *skb,
570 u32 staterr, __le16 vlan)
571{
572 u16 tag = le16_to_cpu(vlan);
573
574 e1000e_rx_hwtstamp(adapter, staterr, skb);
575
576 skb->protocol = eth_type_trans(skb, netdev);
577
578 if (staterr & E1000_RXD_STAT_VP)
579 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
580
581 napi_gro_receive(&adapter->napi, skb);
582}
583
584
585
586
587
588
589
590
591static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
592 struct sk_buff *skb)
593{
594 u16 status = (u16)status_err;
595 u8 errors = (u8)(status_err >> 24);
596
597 skb_checksum_none_assert(skb);
598
599
600 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
601 return;
602
603
604 if (status & E1000_RXD_STAT_IXSM)
605 return;
606
607
608 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
609
610 adapter->hw_csum_err++;
611 return;
612 }
613
614
615 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
616 return;
617
618
619 skb->ip_summed = CHECKSUM_UNNECESSARY;
620 adapter->hw_csum_good++;
621}
622
623static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
624{
625 struct e1000_adapter *adapter = rx_ring->adapter;
626 struct e1000_hw *hw = &adapter->hw;
627 s32 ret_val = __ew32_prepare(hw);
628
629 writel(i, rx_ring->tail);
630
631 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
632 u32 rctl = er32(RCTL);
633
634 ew32(RCTL, rctl & ~E1000_RCTL_EN);
635 e_err("ME firmware caused invalid RDT - resetting\n");
636 schedule_work(&adapter->reset_task);
637 }
638}
639
640static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
641{
642 struct e1000_adapter *adapter = tx_ring->adapter;
643 struct e1000_hw *hw = &adapter->hw;
644 s32 ret_val = __ew32_prepare(hw);
645
646 writel(i, tx_ring->tail);
647
648 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
649 u32 tctl = er32(TCTL);
650
651 ew32(TCTL, tctl & ~E1000_TCTL_EN);
652 e_err("ME firmware caused invalid TDT - resetting\n");
653 schedule_work(&adapter->reset_task);
654 }
655}
656
657
658
659
660
661static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
662 int cleaned_count, gfp_t gfp)
663{
664 struct e1000_adapter *adapter = rx_ring->adapter;
665 struct net_device *netdev = adapter->netdev;
666 struct pci_dev *pdev = adapter->pdev;
667 union e1000_rx_desc_extended *rx_desc;
668 struct e1000_buffer *buffer_info;
669 struct sk_buff *skb;
670 unsigned int i;
671 unsigned int bufsz = adapter->rx_buffer_len;
672
673 i = rx_ring->next_to_use;
674 buffer_info = &rx_ring->buffer_info[i];
675
676 while (cleaned_count--) {
677 skb = buffer_info->skb;
678 if (skb) {
679 skb_trim(skb, 0);
680 goto map_skb;
681 }
682
683 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
684 if (!skb) {
685
686 adapter->alloc_rx_buff_failed++;
687 break;
688 }
689
690 buffer_info->skb = skb;
691map_skb:
692 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
693 adapter->rx_buffer_len,
694 DMA_FROM_DEVICE);
695 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
696 dev_err(&pdev->dev, "Rx DMA map failed\n");
697 adapter->rx_dma_failed++;
698 break;
699 }
700
701 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
702 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
703
704 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
705
706
707
708
709
710 wmb();
711 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
712 e1000e_update_rdt_wa(rx_ring, i);
713 else
714 writel(i, rx_ring->tail);
715 }
716 i++;
717 if (i == rx_ring->count)
718 i = 0;
719 buffer_info = &rx_ring->buffer_info[i];
720 }
721
722 rx_ring->next_to_use = i;
723}
724
725
726
727
728
729static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
730 int cleaned_count, gfp_t gfp)
731{
732 struct e1000_adapter *adapter = rx_ring->adapter;
733 struct net_device *netdev = adapter->netdev;
734 struct pci_dev *pdev = adapter->pdev;
735 union e1000_rx_desc_packet_split *rx_desc;
736 struct e1000_buffer *buffer_info;
737 struct e1000_ps_page *ps_page;
738 struct sk_buff *skb;
739 unsigned int i, j;
740
741 i = rx_ring->next_to_use;
742 buffer_info = &rx_ring->buffer_info[i];
743
744 while (cleaned_count--) {
745 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
746
747 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
748 ps_page = &buffer_info->ps_pages[j];
749 if (j >= adapter->rx_ps_pages) {
750
751 rx_desc->read.buffer_addr[j + 1] =
752 ~cpu_to_le64(0);
753 continue;
754 }
755 if (!ps_page->page) {
756 ps_page->page = alloc_page(gfp);
757 if (!ps_page->page) {
758 adapter->alloc_rx_buff_failed++;
759 goto no_buffers;
760 }
761 ps_page->dma = dma_map_page(&pdev->dev,
762 ps_page->page,
763 0, PAGE_SIZE,
764 DMA_FROM_DEVICE);
765 if (dma_mapping_error(&pdev->dev,
766 ps_page->dma)) {
767 dev_err(&adapter->pdev->dev,
768 "Rx DMA page map failed\n");
769 adapter->rx_dma_failed++;
770 goto no_buffers;
771 }
772 }
773
774
775
776
777 rx_desc->read.buffer_addr[j + 1] =
778 cpu_to_le64(ps_page->dma);
779 }
780
781 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
782 gfp);
783
784 if (!skb) {
785 adapter->alloc_rx_buff_failed++;
786 break;
787 }
788
789 buffer_info->skb = skb;
790 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
791 adapter->rx_ps_bsize0,
792 DMA_FROM_DEVICE);
793 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
794 dev_err(&pdev->dev, "Rx DMA map failed\n");
795 adapter->rx_dma_failed++;
796
797 dev_kfree_skb_any(skb);
798 buffer_info->skb = NULL;
799 break;
800 }
801
802 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
803
804 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
805
806
807
808
809
810 wmb();
811 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
812 e1000e_update_rdt_wa(rx_ring, i << 1);
813 else
814 writel(i << 1, rx_ring->tail);
815 }
816
817 i++;
818 if (i == rx_ring->count)
819 i = 0;
820 buffer_info = &rx_ring->buffer_info[i];
821 }
822
823no_buffers:
824 rx_ring->next_to_use = i;
825}
826
827
828
829
830
831
832
833static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
834 int cleaned_count, gfp_t gfp)
835{
836 struct e1000_adapter *adapter = rx_ring->adapter;
837 struct net_device *netdev = adapter->netdev;
838 struct pci_dev *pdev = adapter->pdev;
839 union e1000_rx_desc_extended *rx_desc;
840 struct e1000_buffer *buffer_info;
841 struct sk_buff *skb;
842 unsigned int i;
843 unsigned int bufsz = 256 - 16;
844
845 i = rx_ring->next_to_use;
846 buffer_info = &rx_ring->buffer_info[i];
847
848 while (cleaned_count--) {
849 skb = buffer_info->skb;
850 if (skb) {
851 skb_trim(skb, 0);
852 goto check_page;
853 }
854
855 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
856 if (unlikely(!skb)) {
857
858 adapter->alloc_rx_buff_failed++;
859 break;
860 }
861
862 buffer_info->skb = skb;
863check_page:
864
865 if (!buffer_info->page) {
866 buffer_info->page = alloc_page(gfp);
867 if (unlikely(!buffer_info->page)) {
868 adapter->alloc_rx_buff_failed++;
869 break;
870 }
871 }
872
873 if (!buffer_info->dma) {
874 buffer_info->dma = dma_map_page(&pdev->dev,
875 buffer_info->page, 0,
876 PAGE_SIZE,
877 DMA_FROM_DEVICE);
878 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
879 adapter->alloc_rx_buff_failed++;
880 break;
881 }
882 }
883
884 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
885 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
886
887 if (unlikely(++i == rx_ring->count))
888 i = 0;
889 buffer_info = &rx_ring->buffer_info[i];
890 }
891
892 if (likely(rx_ring->next_to_use != i)) {
893 rx_ring->next_to_use = i;
894 if (unlikely(i-- == 0))
895 i = (rx_ring->count - 1);
896
897
898
899
900
901
902 wmb();
903 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
904 e1000e_update_rdt_wa(rx_ring, i);
905 else
906 writel(i, rx_ring->tail);
907 }
908}
909
910static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
911 struct sk_buff *skb)
912{
913 if (netdev->features & NETIF_F_RXHASH)
914 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
915}
916
917
918
919
920
921
922
923
924static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
925 int work_to_do)
926{
927 struct e1000_adapter *adapter = rx_ring->adapter;
928 struct net_device *netdev = adapter->netdev;
929 struct pci_dev *pdev = adapter->pdev;
930 struct e1000_hw *hw = &adapter->hw;
931 union e1000_rx_desc_extended *rx_desc, *next_rxd;
932 struct e1000_buffer *buffer_info, *next_buffer;
933 u32 length, staterr;
934 unsigned int i;
935 int cleaned_count = 0;
936 bool cleaned = false;
937 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
938
939 i = rx_ring->next_to_clean;
940 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
941 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
942 buffer_info = &rx_ring->buffer_info[i];
943
944 while (staterr & E1000_RXD_STAT_DD) {
945 struct sk_buff *skb;
946
947 if (*work_done >= work_to_do)
948 break;
949 (*work_done)++;
950 dma_rmb();
951
952 skb = buffer_info->skb;
953 buffer_info->skb = NULL;
954
955 prefetch(skb->data - NET_IP_ALIGN);
956
957 i++;
958 if (i == rx_ring->count)
959 i = 0;
960 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
961 prefetch(next_rxd);
962
963 next_buffer = &rx_ring->buffer_info[i];
964
965 cleaned = true;
966 cleaned_count++;
967 dma_unmap_single(&pdev->dev, buffer_info->dma,
968 adapter->rx_buffer_len, DMA_FROM_DEVICE);
969 buffer_info->dma = 0;
970
971 length = le16_to_cpu(rx_desc->wb.upper.length);
972
973
974
975
976
977
978
979 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
980 adapter->flags2 |= FLAG2_IS_DISCARDING;
981
982 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
983
984 e_dbg("Receive packet consumed multiple buffers\n");
985
986 buffer_info->skb = skb;
987 if (staterr & E1000_RXD_STAT_EOP)
988 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
989 goto next_desc;
990 }
991
992 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
993 !(netdev->features & NETIF_F_RXALL))) {
994
995 buffer_info->skb = skb;
996 goto next_desc;
997 }
998
999
1000 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1001
1002
1003
1004
1005 if (netdev->features & NETIF_F_RXFCS)
1006 total_rx_bytes -= 4;
1007 else
1008 length -= 4;
1009 }
1010
1011 total_rx_bytes += length;
1012 total_rx_packets++;
1013
1014
1015
1016
1017
1018 if (length < copybreak) {
1019 struct sk_buff *new_skb =
1020 napi_alloc_skb(&adapter->napi, length);
1021 if (new_skb) {
1022 skb_copy_to_linear_data_offset(new_skb,
1023 -NET_IP_ALIGN,
1024 (skb->data -
1025 NET_IP_ALIGN),
1026 (length +
1027 NET_IP_ALIGN));
1028
1029 buffer_info->skb = skb;
1030 skb = new_skb;
1031 }
1032
1033 }
1034
1035 skb_put(skb, length);
1036
1037
1038 e1000_rx_checksum(adapter, staterr, skb);
1039
1040 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1041
1042 e1000_receive_skb(adapter, netdev, skb, staterr,
1043 rx_desc->wb.upper.vlan);
1044
1045next_desc:
1046 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1047
1048
1049 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1050 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1051 GFP_ATOMIC);
1052 cleaned_count = 0;
1053 }
1054
1055
1056 rx_desc = next_rxd;
1057 buffer_info = next_buffer;
1058
1059 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1060 }
1061 rx_ring->next_to_clean = i;
1062
1063 cleaned_count = e1000_desc_unused(rx_ring);
1064 if (cleaned_count)
1065 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1066
1067 adapter->total_rx_bytes += total_rx_bytes;
1068 adapter->total_rx_packets += total_rx_packets;
1069 return cleaned;
1070}
1071
1072static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1073 struct e1000_buffer *buffer_info)
1074{
1075 struct e1000_adapter *adapter = tx_ring->adapter;
1076
1077 if (buffer_info->dma) {
1078 if (buffer_info->mapped_as_page)
1079 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1080 buffer_info->length, DMA_TO_DEVICE);
1081 else
1082 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1083 buffer_info->length, DMA_TO_DEVICE);
1084 buffer_info->dma = 0;
1085 }
1086 if (buffer_info->skb) {
1087 dev_kfree_skb_any(buffer_info->skb);
1088 buffer_info->skb = NULL;
1089 }
1090 buffer_info->time_stamp = 0;
1091}
1092
1093static void e1000_print_hw_hang(struct work_struct *work)
1094{
1095 struct e1000_adapter *adapter = container_of(work,
1096 struct e1000_adapter,
1097 print_hang_task);
1098 struct net_device *netdev = adapter->netdev;
1099 struct e1000_ring *tx_ring = adapter->tx_ring;
1100 unsigned int i = tx_ring->next_to_clean;
1101 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1102 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1103 struct e1000_hw *hw = &adapter->hw;
1104 u16 phy_status, phy_1000t_status, phy_ext_status;
1105 u16 pci_status;
1106
1107 if (test_bit(__E1000_DOWN, &adapter->state))
1108 return;
1109
1110 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1111
1112
1113
1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1115
1116 e1e_flush();
1117
1118
1119
1120 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1121
1122 e1e_flush();
1123 adapter->tx_hang_recheck = true;
1124 return;
1125 }
1126 adapter->tx_hang_recheck = false;
1127
1128 if (er32(TDH(0)) == er32(TDT(0))) {
1129 e_dbg("false hang detected, ignoring\n");
1130 return;
1131 }
1132
1133
1134 netif_stop_queue(netdev);
1135
1136 e1e_rphy(hw, MII_BMSR, &phy_status);
1137 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1138 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1139
1140 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1141
1142
1143 e_err("Detected Hardware Unit Hang:\n"
1144 " TDH <%x>\n"
1145 " TDT <%x>\n"
1146 " next_to_use <%x>\n"
1147 " next_to_clean <%x>\n"
1148 "buffer_info[next_to_clean]:\n"
1149 " time_stamp <%lx>\n"
1150 " next_to_watch <%x>\n"
1151 " jiffies <%lx>\n"
1152 " next_to_watch.status <%x>\n"
1153 "MAC Status <%x>\n"
1154 "PHY Status <%x>\n"
1155 "PHY 1000BASE-T Status <%x>\n"
1156 "PHY Extended Status <%x>\n"
1157 "PCI Status <%x>\n",
1158 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1159 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1160 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1161 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1162
1163 e1000e_dump(adapter);
1164
1165
1166 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1167 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1168}
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1179{
1180 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1181 tx_hwtstamp_work);
1182 struct e1000_hw *hw = &adapter->hw;
1183
1184 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1185 struct skb_shared_hwtstamps shhwtstamps;
1186 u64 txstmp;
1187
1188 txstmp = er32(TXSTMPL);
1189 txstmp |= (u64)er32(TXSTMPH) << 32;
1190
1191 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1192
1193 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1194 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1195 adapter->tx_hwtstamp_skb = NULL;
1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1197 + adapter->tx_timeout_factor * HZ)) {
1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1199 adapter->tx_hwtstamp_skb = NULL;
1200 adapter->tx_hwtstamp_timeouts++;
1201 e_warn("clearing Tx timestamp hang\n");
1202 } else {
1203
1204 schedule_work(&adapter->tx_hwtstamp_work);
1205 }
1206}
1207
1208
1209
1210
1211
1212
1213
1214
1215static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1216{
1217 struct e1000_adapter *adapter = tx_ring->adapter;
1218 struct net_device *netdev = adapter->netdev;
1219 struct e1000_hw *hw = &adapter->hw;
1220 struct e1000_tx_desc *tx_desc, *eop_desc;
1221 struct e1000_buffer *buffer_info;
1222 unsigned int i, eop;
1223 unsigned int count = 0;
1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1225 unsigned int bytes_compl = 0, pkts_compl = 0;
1226
1227 i = tx_ring->next_to_clean;
1228 eop = tx_ring->buffer_info[i].next_to_watch;
1229 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1230
1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1232 (count < tx_ring->count)) {
1233 bool cleaned = false;
1234
1235 dma_rmb();
1236 for (; !cleaned; count++) {
1237 tx_desc = E1000_TX_DESC(*tx_ring, i);
1238 buffer_info = &tx_ring->buffer_info[i];
1239 cleaned = (i == eop);
1240
1241 if (cleaned) {
1242 total_tx_packets += buffer_info->segs;
1243 total_tx_bytes += buffer_info->bytecount;
1244 if (buffer_info->skb) {
1245 bytes_compl += buffer_info->skb->len;
1246 pkts_compl++;
1247 }
1248 }
1249
1250 e1000_put_txbuf(tx_ring, buffer_info);
1251 tx_desc->upper.data = 0;
1252
1253 i++;
1254 if (i == tx_ring->count)
1255 i = 0;
1256 }
1257
1258 if (i == tx_ring->next_to_use)
1259 break;
1260 eop = tx_ring->buffer_info[i].next_to_watch;
1261 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1262 }
1263
1264 tx_ring->next_to_clean = i;
1265
1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1267
1268#define TX_WAKE_THRESHOLD 32
1269 if (count && netif_carrier_ok(netdev) &&
1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1271
1272
1273
1274 smp_mb();
1275
1276 if (netif_queue_stopped(netdev) &&
1277 !(test_bit(__E1000_DOWN, &adapter->state))) {
1278 netif_wake_queue(netdev);
1279 ++adapter->restart_queue;
1280 }
1281 }
1282
1283 if (adapter->detect_tx_hung) {
1284
1285
1286
1287 adapter->detect_tx_hung = false;
1288 if (tx_ring->buffer_info[i].time_stamp &&
1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1290 + (adapter->tx_timeout_factor * HZ)) &&
1291 !(er32(STATUS) & E1000_STATUS_TXOFF))
1292 schedule_work(&adapter->print_hang_task);
1293 else
1294 adapter->tx_hang_recheck = false;
1295 }
1296 adapter->total_tx_bytes += total_tx_bytes;
1297 adapter->total_tx_packets += total_tx_packets;
1298 return count < tx_ring->count;
1299}
1300
1301
1302
1303
1304
1305
1306
1307
1308static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1309 int work_to_do)
1310{
1311 struct e1000_adapter *adapter = rx_ring->adapter;
1312 struct e1000_hw *hw = &adapter->hw;
1313 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1314 struct net_device *netdev = adapter->netdev;
1315 struct pci_dev *pdev = adapter->pdev;
1316 struct e1000_buffer *buffer_info, *next_buffer;
1317 struct e1000_ps_page *ps_page;
1318 struct sk_buff *skb;
1319 unsigned int i, j;
1320 u32 length, staterr;
1321 int cleaned_count = 0;
1322 bool cleaned = false;
1323 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1324
1325 i = rx_ring->next_to_clean;
1326 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1327 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1328 buffer_info = &rx_ring->buffer_info[i];
1329
1330 while (staterr & E1000_RXD_STAT_DD) {
1331 if (*work_done >= work_to_do)
1332 break;
1333 (*work_done)++;
1334 skb = buffer_info->skb;
1335 dma_rmb();
1336
1337
1338 prefetch(skb->data - NET_IP_ALIGN);
1339
1340 i++;
1341 if (i == rx_ring->count)
1342 i = 0;
1343 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1344 prefetch(next_rxd);
1345
1346 next_buffer = &rx_ring->buffer_info[i];
1347
1348 cleaned = true;
1349 cleaned_count++;
1350 dma_unmap_single(&pdev->dev, buffer_info->dma,
1351 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1352 buffer_info->dma = 0;
1353
1354
1355 if (!(staterr & E1000_RXD_STAT_EOP))
1356 adapter->flags2 |= FLAG2_IS_DISCARDING;
1357
1358 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1359 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1360 dev_kfree_skb_irq(skb);
1361 if (staterr & E1000_RXD_STAT_EOP)
1362 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1363 goto next_desc;
1364 }
1365
1366 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1367 !(netdev->features & NETIF_F_RXALL))) {
1368 dev_kfree_skb_irq(skb);
1369 goto next_desc;
1370 }
1371
1372 length = le16_to_cpu(rx_desc->wb.middle.length0);
1373
1374 if (!length) {
1375 e_dbg("Last part of the packet spanning multiple descriptors\n");
1376 dev_kfree_skb_irq(skb);
1377 goto next_desc;
1378 }
1379
1380
1381 skb_put(skb, length);
1382
1383 {
1384
1385
1386
1387 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1388
1389
1390
1391
1392
1393
1394 if (l1 && (l1 <= copybreak) &&
1395 ((length + l1) <= adapter->rx_ps_bsize0)) {
1396 u8 *vaddr;
1397
1398 ps_page = &buffer_info->ps_pages[0];
1399
1400
1401
1402
1403
1404 dma_sync_single_for_cpu(&pdev->dev,
1405 ps_page->dma,
1406 PAGE_SIZE,
1407 DMA_FROM_DEVICE);
1408 vaddr = kmap_atomic(ps_page->page);
1409 memcpy(skb_tail_pointer(skb), vaddr, l1);
1410 kunmap_atomic(vaddr);
1411 dma_sync_single_for_device(&pdev->dev,
1412 ps_page->dma,
1413 PAGE_SIZE,
1414 DMA_FROM_DEVICE);
1415
1416
1417 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1418 if (!(netdev->features & NETIF_F_RXFCS))
1419 l1 -= 4;
1420 }
1421
1422 skb_put(skb, l1);
1423 goto copydone;
1424 }
1425 }
1426
1427 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1428 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1429 if (!length)
1430 break;
1431
1432 ps_page = &buffer_info->ps_pages[j];
1433 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1434 DMA_FROM_DEVICE);
1435 ps_page->dma = 0;
1436 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1437 ps_page->page = NULL;
1438 skb->len += length;
1439 skb->data_len += length;
1440 skb->truesize += PAGE_SIZE;
1441 }
1442
1443
1444
1445
1446 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1447 if (!(netdev->features & NETIF_F_RXFCS))
1448 pskb_trim(skb, skb->len - 4);
1449 }
1450
1451copydone:
1452 total_rx_bytes += skb->len;
1453 total_rx_packets++;
1454
1455 e1000_rx_checksum(adapter, staterr, skb);
1456
1457 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1458
1459 if (rx_desc->wb.upper.header_status &
1460 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1461 adapter->rx_hdr_split++;
1462
1463 e1000_receive_skb(adapter, netdev, skb, staterr,
1464 rx_desc->wb.middle.vlan);
1465
1466next_desc:
1467 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1468 buffer_info->skb = NULL;
1469
1470
1471 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1472 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1473 GFP_ATOMIC);
1474 cleaned_count = 0;
1475 }
1476
1477
1478 rx_desc = next_rxd;
1479 buffer_info = next_buffer;
1480
1481 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1482 }
1483 rx_ring->next_to_clean = i;
1484
1485 cleaned_count = e1000_desc_unused(rx_ring);
1486 if (cleaned_count)
1487 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1488
1489 adapter->total_rx_bytes += total_rx_bytes;
1490 adapter->total_rx_packets += total_rx_packets;
1491 return cleaned;
1492}
1493
1494
1495
1496
1497static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1498 u16 length)
1499{
1500 bi->page = NULL;
1501 skb->len += length;
1502 skb->data_len += length;
1503 skb->truesize += PAGE_SIZE;
1504}
1505
1506
1507
1508
1509
1510
1511
1512
1513static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1514 int work_to_do)
1515{
1516 struct e1000_adapter *adapter = rx_ring->adapter;
1517 struct net_device *netdev = adapter->netdev;
1518 struct pci_dev *pdev = adapter->pdev;
1519 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1520 struct e1000_buffer *buffer_info, *next_buffer;
1521 u32 length, staterr;
1522 unsigned int i;
1523 int cleaned_count = 0;
1524 bool cleaned = false;
1525 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1526 struct skb_shared_info *shinfo;
1527
1528 i = rx_ring->next_to_clean;
1529 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1530 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1531 buffer_info = &rx_ring->buffer_info[i];
1532
1533 while (staterr & E1000_RXD_STAT_DD) {
1534 struct sk_buff *skb;
1535
1536 if (*work_done >= work_to_do)
1537 break;
1538 (*work_done)++;
1539 dma_rmb();
1540
1541 skb = buffer_info->skb;
1542 buffer_info->skb = NULL;
1543
1544 ++i;
1545 if (i == rx_ring->count)
1546 i = 0;
1547 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1548 prefetch(next_rxd);
1549
1550 next_buffer = &rx_ring->buffer_info[i];
1551
1552 cleaned = true;
1553 cleaned_count++;
1554 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1555 DMA_FROM_DEVICE);
1556 buffer_info->dma = 0;
1557
1558 length = le16_to_cpu(rx_desc->wb.upper.length);
1559
1560
1561 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1562 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1563 !(netdev->features & NETIF_F_RXALL)))) {
1564
1565 buffer_info->skb = skb;
1566
1567 if (rx_ring->rx_skb_top)
1568 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1569 rx_ring->rx_skb_top = NULL;
1570 goto next_desc;
1571 }
1572#define rxtop (rx_ring->rx_skb_top)
1573 if (!(staterr & E1000_RXD_STAT_EOP)) {
1574
1575 if (!rxtop) {
1576
1577 rxtop = skb;
1578 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1579 0, length);
1580 } else {
1581
1582 shinfo = skb_shinfo(rxtop);
1583 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1584 buffer_info->page, 0,
1585 length);
1586
1587 buffer_info->skb = skb;
1588 }
1589 e1000_consume_page(buffer_info, rxtop, length);
1590 goto next_desc;
1591 } else {
1592 if (rxtop) {
1593
1594 shinfo = skb_shinfo(rxtop);
1595 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1596 buffer_info->page, 0,
1597 length);
1598
1599
1600
1601 buffer_info->skb = skb;
1602 skb = rxtop;
1603 rxtop = NULL;
1604 e1000_consume_page(buffer_info, skb, length);
1605 } else {
1606
1607
1608
1609 if (length <= copybreak &&
1610 skb_tailroom(skb) >= length) {
1611 u8 *vaddr;
1612 vaddr = kmap_atomic(buffer_info->page);
1613 memcpy(skb_tail_pointer(skb), vaddr,
1614 length);
1615 kunmap_atomic(vaddr);
1616
1617
1618
1619 skb_put(skb, length);
1620 } else {
1621 skb_fill_page_desc(skb, 0,
1622 buffer_info->page, 0,
1623 length);
1624 e1000_consume_page(buffer_info, skb,
1625 length);
1626 }
1627 }
1628 }
1629
1630
1631 e1000_rx_checksum(adapter, staterr, skb);
1632
1633 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1634
1635
1636 total_rx_bytes += skb->len;
1637 total_rx_packets++;
1638
1639
1640 if (!pskb_may_pull(skb, ETH_HLEN)) {
1641 e_err("pskb_may_pull failed.\n");
1642 dev_kfree_skb_irq(skb);
1643 goto next_desc;
1644 }
1645
1646 e1000_receive_skb(adapter, netdev, skb, staterr,
1647 rx_desc->wb.upper.vlan);
1648
1649next_desc:
1650 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1651
1652
1653 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1654 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1655 GFP_ATOMIC);
1656 cleaned_count = 0;
1657 }
1658
1659
1660 rx_desc = next_rxd;
1661 buffer_info = next_buffer;
1662
1663 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1664 }
1665 rx_ring->next_to_clean = i;
1666
1667 cleaned_count = e1000_desc_unused(rx_ring);
1668 if (cleaned_count)
1669 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1670
1671 adapter->total_rx_bytes += total_rx_bytes;
1672 adapter->total_rx_packets += total_rx_packets;
1673 return cleaned;
1674}
1675
1676
1677
1678
1679
1680static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1681{
1682 struct e1000_adapter *adapter = rx_ring->adapter;
1683 struct e1000_buffer *buffer_info;
1684 struct e1000_ps_page *ps_page;
1685 struct pci_dev *pdev = adapter->pdev;
1686 unsigned int i, j;
1687
1688
1689 for (i = 0; i < rx_ring->count; i++) {
1690 buffer_info = &rx_ring->buffer_info[i];
1691 if (buffer_info->dma) {
1692 if (adapter->clean_rx == e1000_clean_rx_irq)
1693 dma_unmap_single(&pdev->dev, buffer_info->dma,
1694 adapter->rx_buffer_len,
1695 DMA_FROM_DEVICE);
1696 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1697 dma_unmap_page(&pdev->dev, buffer_info->dma,
1698 PAGE_SIZE, DMA_FROM_DEVICE);
1699 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1700 dma_unmap_single(&pdev->dev, buffer_info->dma,
1701 adapter->rx_ps_bsize0,
1702 DMA_FROM_DEVICE);
1703 buffer_info->dma = 0;
1704 }
1705
1706 if (buffer_info->page) {
1707 put_page(buffer_info->page);
1708 buffer_info->page = NULL;
1709 }
1710
1711 if (buffer_info->skb) {
1712 dev_kfree_skb(buffer_info->skb);
1713 buffer_info->skb = NULL;
1714 }
1715
1716 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1717 ps_page = &buffer_info->ps_pages[j];
1718 if (!ps_page->page)
1719 break;
1720 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1721 DMA_FROM_DEVICE);
1722 ps_page->dma = 0;
1723 put_page(ps_page->page);
1724 ps_page->page = NULL;
1725 }
1726 }
1727
1728
1729 if (rx_ring->rx_skb_top) {
1730 dev_kfree_skb(rx_ring->rx_skb_top);
1731 rx_ring->rx_skb_top = NULL;
1732 }
1733
1734
1735 memset(rx_ring->desc, 0, rx_ring->size);
1736
1737 rx_ring->next_to_clean = 0;
1738 rx_ring->next_to_use = 0;
1739 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1740}
1741
1742static void e1000e_downshift_workaround(struct work_struct *work)
1743{
1744 struct e1000_adapter *adapter = container_of(work,
1745 struct e1000_adapter,
1746 downshift_task);
1747
1748 if (test_bit(__E1000_DOWN, &adapter->state))
1749 return;
1750
1751 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1752}
1753
1754
1755
1756
1757
1758
1759static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1760{
1761 struct net_device *netdev = data;
1762 struct e1000_adapter *adapter = netdev_priv(netdev);
1763 struct e1000_hw *hw = &adapter->hw;
1764 u32 icr = er32(ICR);
1765
1766
1767 if (icr & E1000_ICR_LSC) {
1768 hw->mac.get_link_status = true;
1769
1770
1771
1772 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1773 (!(er32(STATUS) & E1000_STATUS_LU)))
1774 schedule_work(&adapter->downshift_task);
1775
1776
1777
1778
1779
1780 if (netif_carrier_ok(netdev) &&
1781 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1782
1783 u32 rctl = er32(RCTL);
1784
1785 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1786 adapter->flags |= FLAG_RESTART_NOW;
1787 }
1788
1789 if (!test_bit(__E1000_DOWN, &adapter->state))
1790 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1791 }
1792
1793
1794 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
1795 (hw->mac.type == e1000_pch_spt))) {
1796 u32 pbeccsts = er32(PBECCSTS);
1797
1798 adapter->corr_errors +=
1799 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1800 adapter->uncorr_errors +=
1801 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1802 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1803
1804
1805 schedule_work(&adapter->reset_task);
1806
1807
1808 return IRQ_HANDLED;
1809 }
1810
1811 if (napi_schedule_prep(&adapter->napi)) {
1812 adapter->total_tx_bytes = 0;
1813 adapter->total_tx_packets = 0;
1814 adapter->total_rx_bytes = 0;
1815 adapter->total_rx_packets = 0;
1816 __napi_schedule(&adapter->napi);
1817 }
1818
1819 return IRQ_HANDLED;
1820}
1821
1822
1823
1824
1825
1826
1827static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1828{
1829 struct net_device *netdev = data;
1830 struct e1000_adapter *adapter = netdev_priv(netdev);
1831 struct e1000_hw *hw = &adapter->hw;
1832 u32 rctl, icr = er32(ICR);
1833
1834 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1835 return IRQ_NONE;
1836
1837
1838
1839
1840 if (!(icr & E1000_ICR_INT_ASSERTED))
1841 return IRQ_NONE;
1842
1843
1844
1845
1846
1847
1848 if (icr & E1000_ICR_LSC) {
1849 hw->mac.get_link_status = true;
1850
1851
1852
1853 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1854 (!(er32(STATUS) & E1000_STATUS_LU)))
1855 schedule_work(&adapter->downshift_task);
1856
1857
1858
1859
1860
1861
1862 if (netif_carrier_ok(netdev) &&
1863 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1864
1865 rctl = er32(RCTL);
1866 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1867 adapter->flags |= FLAG_RESTART_NOW;
1868 }
1869
1870 if (!test_bit(__E1000_DOWN, &adapter->state))
1871 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1872 }
1873
1874
1875 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
1876 (hw->mac.type == e1000_pch_spt))) {
1877 u32 pbeccsts = er32(PBECCSTS);
1878
1879 adapter->corr_errors +=
1880 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1881 adapter->uncorr_errors +=
1882 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1883 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1884
1885
1886 schedule_work(&adapter->reset_task);
1887
1888
1889 return IRQ_HANDLED;
1890 }
1891
1892 if (napi_schedule_prep(&adapter->napi)) {
1893 adapter->total_tx_bytes = 0;
1894 adapter->total_tx_packets = 0;
1895 adapter->total_rx_bytes = 0;
1896 adapter->total_rx_packets = 0;
1897 __napi_schedule(&adapter->napi);
1898 }
1899
1900 return IRQ_HANDLED;
1901}
1902
1903static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1904{
1905 struct net_device *netdev = data;
1906 struct e1000_adapter *adapter = netdev_priv(netdev);
1907 struct e1000_hw *hw = &adapter->hw;
1908 u32 icr = er32(ICR);
1909
1910 if (!(icr & E1000_ICR_INT_ASSERTED)) {
1911 if (!test_bit(__E1000_DOWN, &adapter->state))
1912 ew32(IMS, E1000_IMS_OTHER);
1913 return IRQ_NONE;
1914 }
1915
1916 if (icr & adapter->eiac_mask)
1917 ew32(ICS, (icr & adapter->eiac_mask));
1918
1919 if (icr & E1000_ICR_OTHER) {
1920 if (!(icr & E1000_ICR_LSC))
1921 goto no_link_interrupt;
1922 hw->mac.get_link_status = true;
1923
1924 if (!test_bit(__E1000_DOWN, &adapter->state))
1925 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1926 }
1927
1928no_link_interrupt:
1929 if (!test_bit(__E1000_DOWN, &adapter->state))
1930 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
1931
1932 return IRQ_HANDLED;
1933}
1934
1935static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1936{
1937 struct net_device *netdev = data;
1938 struct e1000_adapter *adapter = netdev_priv(netdev);
1939 struct e1000_hw *hw = &adapter->hw;
1940 struct e1000_ring *tx_ring = adapter->tx_ring;
1941
1942 adapter->total_tx_bytes = 0;
1943 adapter->total_tx_packets = 0;
1944
1945 if (!e1000_clean_tx_irq(tx_ring))
1946
1947 ew32(ICS, tx_ring->ims_val);
1948
1949 return IRQ_HANDLED;
1950}
1951
1952static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1953{
1954 struct net_device *netdev = data;
1955 struct e1000_adapter *adapter = netdev_priv(netdev);
1956 struct e1000_ring *rx_ring = adapter->rx_ring;
1957
1958
1959
1960
1961 if (rx_ring->set_itr) {
1962 writel(1000000000 / (rx_ring->itr_val * 256),
1963 rx_ring->itr_register);
1964 rx_ring->set_itr = 0;
1965 }
1966
1967 if (napi_schedule_prep(&adapter->napi)) {
1968 adapter->total_rx_bytes = 0;
1969 adapter->total_rx_packets = 0;
1970 __napi_schedule(&adapter->napi);
1971 }
1972 return IRQ_HANDLED;
1973}
1974
1975
1976
1977
1978
1979
1980
1981static void e1000_configure_msix(struct e1000_adapter *adapter)
1982{
1983 struct e1000_hw *hw = &adapter->hw;
1984 struct e1000_ring *rx_ring = adapter->rx_ring;
1985 struct e1000_ring *tx_ring = adapter->tx_ring;
1986 int vector = 0;
1987 u32 ctrl_ext, ivar = 0;
1988
1989 adapter->eiac_mask = 0;
1990
1991
1992 if (hw->mac.type == e1000_82574) {
1993 u32 rfctl = er32(RFCTL);
1994
1995 rfctl |= E1000_RFCTL_ACK_DIS;
1996 ew32(RFCTL, rfctl);
1997 }
1998
1999
2000 rx_ring->ims_val = E1000_IMS_RXQ0;
2001 adapter->eiac_mask |= rx_ring->ims_val;
2002 if (rx_ring->itr_val)
2003 writel(1000000000 / (rx_ring->itr_val * 256),
2004 rx_ring->itr_register);
2005 else
2006 writel(1, rx_ring->itr_register);
2007 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
2008
2009
2010 tx_ring->ims_val = E1000_IMS_TXQ0;
2011 vector++;
2012 if (tx_ring->itr_val)
2013 writel(1000000000 / (tx_ring->itr_val * 256),
2014 tx_ring->itr_register);
2015 else
2016 writel(1, tx_ring->itr_register);
2017 adapter->eiac_mask |= tx_ring->ims_val;
2018 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2019
2020
2021 vector++;
2022 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2023 if (rx_ring->itr_val)
2024 writel(1000000000 / (rx_ring->itr_val * 256),
2025 hw->hw_addr + E1000_EITR_82574(vector));
2026 else
2027 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2028
2029
2030 ivar |= (1 << 31);
2031
2032 ew32(IVAR, ivar);
2033
2034
2035 ctrl_ext = er32(CTRL_EXT);
2036 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2037
2038
2039 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2040 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2041 ew32(CTRL_EXT, ctrl_ext);
2042 e1e_flush();
2043}
2044
2045void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2046{
2047 if (adapter->msix_entries) {
2048 pci_disable_msix(adapter->pdev);
2049 kfree(adapter->msix_entries);
2050 adapter->msix_entries = NULL;
2051 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2052 pci_disable_msi(adapter->pdev);
2053 adapter->flags &= ~FLAG_MSI_ENABLED;
2054 }
2055}
2056
2057
2058
2059
2060
2061
2062
2063void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2064{
2065 int err;
2066 int i;
2067
2068 switch (adapter->int_mode) {
2069 case E1000E_INT_MODE_MSIX:
2070 if (adapter->flags & FLAG_HAS_MSIX) {
2071 adapter->num_vectors = 3;
2072 adapter->msix_entries = kcalloc(adapter->num_vectors,
2073 sizeof(struct
2074 msix_entry),
2075 GFP_KERNEL);
2076 if (adapter->msix_entries) {
2077 struct e1000_adapter *a = adapter;
2078
2079 for (i = 0; i < adapter->num_vectors; i++)
2080 adapter->msix_entries[i].entry = i;
2081
2082 err = pci_enable_msix_range(a->pdev,
2083 a->msix_entries,
2084 a->num_vectors,
2085 a->num_vectors);
2086 if (err > 0)
2087 return;
2088 }
2089
2090 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2091 e1000e_reset_interrupt_capability(adapter);
2092 }
2093 adapter->int_mode = E1000E_INT_MODE_MSI;
2094
2095 case E1000E_INT_MODE_MSI:
2096 if (!pci_enable_msi(adapter->pdev)) {
2097 adapter->flags |= FLAG_MSI_ENABLED;
2098 } else {
2099 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2100 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2101 }
2102
2103 case E1000E_INT_MODE_LEGACY:
2104
2105 break;
2106 }
2107
2108
2109 adapter->num_vectors = 1;
2110}
2111
2112
2113
2114
2115
2116
2117
2118static int e1000_request_msix(struct e1000_adapter *adapter)
2119{
2120 struct net_device *netdev = adapter->netdev;
2121 int err = 0, vector = 0;
2122
2123 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2124 snprintf(adapter->rx_ring->name,
2125 sizeof(adapter->rx_ring->name) - 1,
2126 "%s-rx-0", netdev->name);
2127 else
2128 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2129 err = request_irq(adapter->msix_entries[vector].vector,
2130 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2131 netdev);
2132 if (err)
2133 return err;
2134 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2135 E1000_EITR_82574(vector);
2136 adapter->rx_ring->itr_val = adapter->itr;
2137 vector++;
2138
2139 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2140 snprintf(adapter->tx_ring->name,
2141 sizeof(adapter->tx_ring->name) - 1,
2142 "%s-tx-0", netdev->name);
2143 else
2144 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2145 err = request_irq(adapter->msix_entries[vector].vector,
2146 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2147 netdev);
2148 if (err)
2149 return err;
2150 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2151 E1000_EITR_82574(vector);
2152 adapter->tx_ring->itr_val = adapter->itr;
2153 vector++;
2154
2155 err = request_irq(adapter->msix_entries[vector].vector,
2156 e1000_msix_other, 0, netdev->name, netdev);
2157 if (err)
2158 return err;
2159
2160 e1000_configure_msix(adapter);
2161
2162 return 0;
2163}
2164
2165
2166
2167
2168
2169
2170
2171static int e1000_request_irq(struct e1000_adapter *adapter)
2172{
2173 struct net_device *netdev = adapter->netdev;
2174 int err;
2175
2176 if (adapter->msix_entries) {
2177 err = e1000_request_msix(adapter);
2178 if (!err)
2179 return err;
2180
2181 e1000e_reset_interrupt_capability(adapter);
2182 adapter->int_mode = E1000E_INT_MODE_MSI;
2183 e1000e_set_interrupt_capability(adapter);
2184 }
2185 if (adapter->flags & FLAG_MSI_ENABLED) {
2186 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2187 netdev->name, netdev);
2188 if (!err)
2189 return err;
2190
2191
2192 e1000e_reset_interrupt_capability(adapter);
2193 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2194 }
2195
2196 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2197 netdev->name, netdev);
2198 if (err)
2199 e_err("Unable to allocate interrupt, Error: %d\n", err);
2200
2201 return err;
2202}
2203
2204static void e1000_free_irq(struct e1000_adapter *adapter)
2205{
2206 struct net_device *netdev = adapter->netdev;
2207
2208 if (adapter->msix_entries) {
2209 int vector = 0;
2210
2211 free_irq(adapter->msix_entries[vector].vector, netdev);
2212 vector++;
2213
2214 free_irq(adapter->msix_entries[vector].vector, netdev);
2215 vector++;
2216
2217
2218 free_irq(adapter->msix_entries[vector].vector, netdev);
2219 return;
2220 }
2221
2222 free_irq(adapter->pdev->irq, netdev);
2223}
2224
2225
2226
2227
2228static void e1000_irq_disable(struct e1000_adapter *adapter)
2229{
2230 struct e1000_hw *hw = &adapter->hw;
2231
2232 ew32(IMC, ~0);
2233 if (adapter->msix_entries)
2234 ew32(EIAC_82574, 0);
2235 e1e_flush();
2236
2237 if (adapter->msix_entries) {
2238 int i;
2239
2240 for (i = 0; i < adapter->num_vectors; i++)
2241 synchronize_irq(adapter->msix_entries[i].vector);
2242 } else {
2243 synchronize_irq(adapter->pdev->irq);
2244 }
2245}
2246
2247
2248
2249
2250static void e1000_irq_enable(struct e1000_adapter *adapter)
2251{
2252 struct e1000_hw *hw = &adapter->hw;
2253
2254 if (adapter->msix_entries) {
2255 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2256 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2257 } else if ((hw->mac.type == e1000_pch_lpt) ||
2258 (hw->mac.type == e1000_pch_spt)) {
2259 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2260 } else {
2261 ew32(IMS, IMS_ENABLE_MASK);
2262 }
2263 e1e_flush();
2264}
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275void e1000e_get_hw_control(struct e1000_adapter *adapter)
2276{
2277 struct e1000_hw *hw = &adapter->hw;
2278 u32 ctrl_ext;
2279 u32 swsm;
2280
2281
2282 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2283 swsm = er32(SWSM);
2284 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2285 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2286 ctrl_ext = er32(CTRL_EXT);
2287 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2288 }
2289}
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301void e1000e_release_hw_control(struct e1000_adapter *adapter)
2302{
2303 struct e1000_hw *hw = &adapter->hw;
2304 u32 ctrl_ext;
2305 u32 swsm;
2306
2307
2308 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2309 swsm = er32(SWSM);
2310 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2311 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2312 ctrl_ext = er32(CTRL_EXT);
2313 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2314 }
2315}
2316
2317
2318
2319
2320static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2321 struct e1000_ring *ring)
2322{
2323 struct pci_dev *pdev = adapter->pdev;
2324
2325 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2326 GFP_KERNEL);
2327 if (!ring->desc)
2328 return -ENOMEM;
2329
2330 return 0;
2331}
2332
2333
2334
2335
2336
2337
2338
2339int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2340{
2341 struct e1000_adapter *adapter = tx_ring->adapter;
2342 int err = -ENOMEM, size;
2343
2344 size = sizeof(struct e1000_buffer) * tx_ring->count;
2345 tx_ring->buffer_info = vzalloc(size);
2346 if (!tx_ring->buffer_info)
2347 goto err;
2348
2349
2350 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2351 tx_ring->size = ALIGN(tx_ring->size, 4096);
2352
2353 err = e1000_alloc_ring_dma(adapter, tx_ring);
2354 if (err)
2355 goto err;
2356
2357 tx_ring->next_to_use = 0;
2358 tx_ring->next_to_clean = 0;
2359
2360 return 0;
2361err:
2362 vfree(tx_ring->buffer_info);
2363 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2364 return err;
2365}
2366
2367
2368
2369
2370
2371
2372
2373int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2374{
2375 struct e1000_adapter *adapter = rx_ring->adapter;
2376 struct e1000_buffer *buffer_info;
2377 int i, size, desc_len, err = -ENOMEM;
2378
2379 size = sizeof(struct e1000_buffer) * rx_ring->count;
2380 rx_ring->buffer_info = vzalloc(size);
2381 if (!rx_ring->buffer_info)
2382 goto err;
2383
2384 for (i = 0; i < rx_ring->count; i++) {
2385 buffer_info = &rx_ring->buffer_info[i];
2386 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2387 sizeof(struct e1000_ps_page),
2388 GFP_KERNEL);
2389 if (!buffer_info->ps_pages)
2390 goto err_pages;
2391 }
2392
2393 desc_len = sizeof(union e1000_rx_desc_packet_split);
2394
2395
2396 rx_ring->size = rx_ring->count * desc_len;
2397 rx_ring->size = ALIGN(rx_ring->size, 4096);
2398
2399 err = e1000_alloc_ring_dma(adapter, rx_ring);
2400 if (err)
2401 goto err_pages;
2402
2403 rx_ring->next_to_clean = 0;
2404 rx_ring->next_to_use = 0;
2405 rx_ring->rx_skb_top = NULL;
2406
2407 return 0;
2408
2409err_pages:
2410 for (i = 0; i < rx_ring->count; i++) {
2411 buffer_info = &rx_ring->buffer_info[i];
2412 kfree(buffer_info->ps_pages);
2413 }
2414err:
2415 vfree(rx_ring->buffer_info);
2416 e_err("Unable to allocate memory for the receive descriptor ring\n");
2417 return err;
2418}
2419
2420
2421
2422
2423
2424static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2425{
2426 struct e1000_adapter *adapter = tx_ring->adapter;
2427 struct e1000_buffer *buffer_info;
2428 unsigned long size;
2429 unsigned int i;
2430
2431 for (i = 0; i < tx_ring->count; i++) {
2432 buffer_info = &tx_ring->buffer_info[i];
2433 e1000_put_txbuf(tx_ring, buffer_info);
2434 }
2435
2436 netdev_reset_queue(adapter->netdev);
2437 size = sizeof(struct e1000_buffer) * tx_ring->count;
2438 memset(tx_ring->buffer_info, 0, size);
2439
2440 memset(tx_ring->desc, 0, tx_ring->size);
2441
2442 tx_ring->next_to_use = 0;
2443 tx_ring->next_to_clean = 0;
2444}
2445
2446
2447
2448
2449
2450
2451
2452void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2453{
2454 struct e1000_adapter *adapter = tx_ring->adapter;
2455 struct pci_dev *pdev = adapter->pdev;
2456
2457 e1000_clean_tx_ring(tx_ring);
2458
2459 vfree(tx_ring->buffer_info);
2460 tx_ring->buffer_info = NULL;
2461
2462 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2463 tx_ring->dma);
2464 tx_ring->desc = NULL;
2465}
2466
2467
2468
2469
2470
2471
2472
2473void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2474{
2475 struct e1000_adapter *adapter = rx_ring->adapter;
2476 struct pci_dev *pdev = adapter->pdev;
2477 int i;
2478
2479 e1000_clean_rx_ring(rx_ring);
2480
2481 for (i = 0; i < rx_ring->count; i++)
2482 kfree(rx_ring->buffer_info[i].ps_pages);
2483
2484 vfree(rx_ring->buffer_info);
2485 rx_ring->buffer_info = NULL;
2486
2487 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2488 rx_ring->dma);
2489 rx_ring->desc = NULL;
2490}
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2509{
2510 unsigned int retval = itr_setting;
2511
2512 if (packets == 0)
2513 return itr_setting;
2514
2515 switch (itr_setting) {
2516 case lowest_latency:
2517
2518 if (bytes / packets > 8000)
2519 retval = bulk_latency;
2520 else if ((packets < 5) && (bytes > 512))
2521 retval = low_latency;
2522 break;
2523 case low_latency:
2524 if (bytes > 10000) {
2525
2526 if (bytes / packets > 8000)
2527 retval = bulk_latency;
2528 else if ((packets < 10) || ((bytes / packets) > 1200))
2529 retval = bulk_latency;
2530 else if ((packets > 35))
2531 retval = lowest_latency;
2532 } else if (bytes / packets > 2000) {
2533 retval = bulk_latency;
2534 } else if (packets <= 2 && bytes < 512) {
2535 retval = lowest_latency;
2536 }
2537 break;
2538 case bulk_latency:
2539 if (bytes > 25000) {
2540 if (packets > 35)
2541 retval = low_latency;
2542 } else if (bytes < 6000) {
2543 retval = low_latency;
2544 }
2545 break;
2546 }
2547
2548 return retval;
2549}
2550
2551static void e1000_set_itr(struct e1000_adapter *adapter)
2552{
2553 u16 current_itr;
2554 u32 new_itr = adapter->itr;
2555
2556
2557 if (adapter->link_speed != SPEED_1000) {
2558 current_itr = 0;
2559 new_itr = 4000;
2560 goto set_itr_now;
2561 }
2562
2563 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2564 new_itr = 0;
2565 goto set_itr_now;
2566 }
2567
2568 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2569 adapter->total_tx_packets,
2570 adapter->total_tx_bytes);
2571
2572 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2573 adapter->tx_itr = low_latency;
2574
2575 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2576 adapter->total_rx_packets,
2577 adapter->total_rx_bytes);
2578
2579 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2580 adapter->rx_itr = low_latency;
2581
2582 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2583
2584
2585 switch (current_itr) {
2586 case lowest_latency:
2587 new_itr = 70000;
2588 break;
2589 case low_latency:
2590 new_itr = 20000;
2591 break;
2592 case bulk_latency:
2593 new_itr = 4000;
2594 break;
2595 default:
2596 break;
2597 }
2598
2599set_itr_now:
2600 if (new_itr != adapter->itr) {
2601
2602
2603
2604
2605 new_itr = new_itr > adapter->itr ?
2606 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2607 adapter->itr = new_itr;
2608 adapter->rx_ring->itr_val = new_itr;
2609 if (adapter->msix_entries)
2610 adapter->rx_ring->set_itr = 1;
2611 else
2612 e1000e_write_itr(adapter, new_itr);
2613 }
2614}
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2626{
2627 struct e1000_hw *hw = &adapter->hw;
2628 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2629
2630 if (adapter->msix_entries) {
2631 int vector;
2632
2633 for (vector = 0; vector < adapter->num_vectors; vector++)
2634 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2635 } else {
2636 ew32(ITR, new_itr);
2637 }
2638}
2639
2640
2641
2642
2643
2644static int e1000_alloc_queues(struct e1000_adapter *adapter)
2645{
2646 int size = sizeof(struct e1000_ring);
2647
2648 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2649 if (!adapter->tx_ring)
2650 goto err;
2651 adapter->tx_ring->count = adapter->tx_ring_count;
2652 adapter->tx_ring->adapter = adapter;
2653
2654 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2655 if (!adapter->rx_ring)
2656 goto err;
2657 adapter->rx_ring->count = adapter->rx_ring_count;
2658 adapter->rx_ring->adapter = adapter;
2659
2660 return 0;
2661err:
2662 e_err("Unable to allocate memory for queues\n");
2663 kfree(adapter->rx_ring);
2664 kfree(adapter->tx_ring);
2665 return -ENOMEM;
2666}
2667
2668
2669
2670
2671
2672
2673static int e1000e_poll(struct napi_struct *napi, int weight)
2674{
2675 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2676 napi);
2677 struct e1000_hw *hw = &adapter->hw;
2678 struct net_device *poll_dev = adapter->netdev;
2679 int tx_cleaned = 1, work_done = 0;
2680
2681 adapter = netdev_priv(poll_dev);
2682
2683 if (!adapter->msix_entries ||
2684 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2685 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2686
2687 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
2688
2689 if (!tx_cleaned)
2690 work_done = weight;
2691
2692
2693 if (work_done < weight) {
2694 if (adapter->itr_setting & 3)
2695 e1000_set_itr(adapter);
2696 napi_complete(napi);
2697 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2698 if (adapter->msix_entries)
2699 ew32(IMS, adapter->rx_ring->ims_val);
2700 else
2701 e1000_irq_enable(adapter);
2702 }
2703 }
2704
2705 return work_done;
2706}
2707
2708static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2709 __always_unused __be16 proto, u16 vid)
2710{
2711 struct e1000_adapter *adapter = netdev_priv(netdev);
2712 struct e1000_hw *hw = &adapter->hw;
2713 u32 vfta, index;
2714
2715
2716 if ((adapter->hw.mng_cookie.status &
2717 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2718 (vid == adapter->mng_vlan_id))
2719 return 0;
2720
2721
2722 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2723 index = (vid >> 5) & 0x7F;
2724 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2725 vfta |= (1 << (vid & 0x1F));
2726 hw->mac.ops.write_vfta(hw, index, vfta);
2727 }
2728
2729 set_bit(vid, adapter->active_vlans);
2730
2731 return 0;
2732}
2733
2734static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2735 __always_unused __be16 proto, u16 vid)
2736{
2737 struct e1000_adapter *adapter = netdev_priv(netdev);
2738 struct e1000_hw *hw = &adapter->hw;
2739 u32 vfta, index;
2740
2741 if ((adapter->hw.mng_cookie.status &
2742 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2743 (vid == adapter->mng_vlan_id)) {
2744
2745 e1000e_release_hw_control(adapter);
2746 return 0;
2747 }
2748
2749
2750 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2751 index = (vid >> 5) & 0x7F;
2752 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2753 vfta &= ~(1 << (vid & 0x1F));
2754 hw->mac.ops.write_vfta(hw, index, vfta);
2755 }
2756
2757 clear_bit(vid, adapter->active_vlans);
2758
2759 return 0;
2760}
2761
2762
2763
2764
2765
2766static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2767{
2768 struct net_device *netdev = adapter->netdev;
2769 struct e1000_hw *hw = &adapter->hw;
2770 u32 rctl;
2771
2772 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2773
2774 rctl = er32(RCTL);
2775 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2776 ew32(RCTL, rctl);
2777
2778 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2779 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2780 adapter->mng_vlan_id);
2781 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2782 }
2783 }
2784}
2785
2786
2787
2788
2789
2790static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2791{
2792 struct e1000_hw *hw = &adapter->hw;
2793 u32 rctl;
2794
2795 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2796
2797 rctl = er32(RCTL);
2798 rctl |= E1000_RCTL_VFE;
2799 rctl &= ~E1000_RCTL_CFIEN;
2800 ew32(RCTL, rctl);
2801 }
2802}
2803
2804
2805
2806
2807
2808static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2809{
2810 struct e1000_hw *hw = &adapter->hw;
2811 u32 ctrl;
2812
2813
2814 ctrl = er32(CTRL);
2815 ctrl &= ~E1000_CTRL_VME;
2816 ew32(CTRL, ctrl);
2817}
2818
2819
2820
2821
2822
2823static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2824{
2825 struct e1000_hw *hw = &adapter->hw;
2826 u32 ctrl;
2827
2828
2829 ctrl = er32(CTRL);
2830 ctrl |= E1000_CTRL_VME;
2831 ew32(CTRL, ctrl);
2832}
2833
2834static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2835{
2836 struct net_device *netdev = adapter->netdev;
2837 u16 vid = adapter->hw.mng_cookie.vlan_id;
2838 u16 old_vid = adapter->mng_vlan_id;
2839
2840 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2841 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2842 adapter->mng_vlan_id = vid;
2843 }
2844
2845 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2846 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2847}
2848
2849static void e1000_restore_vlan(struct e1000_adapter *adapter)
2850{
2851 u16 vid;
2852
2853 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2854
2855 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2856 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2857}
2858
2859static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2860{
2861 struct e1000_hw *hw = &adapter->hw;
2862 u32 manc, manc2h, mdef, i, j;
2863
2864 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2865 return;
2866
2867 manc = er32(MANC);
2868
2869
2870
2871
2872
2873 manc |= E1000_MANC_EN_MNG2HOST;
2874 manc2h = er32(MANC2H);
2875
2876 switch (hw->mac.type) {
2877 default:
2878 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2879 break;
2880 case e1000_82574:
2881 case e1000_82583:
2882
2883
2884
2885 for (i = 0, j = 0; i < 8; i++) {
2886 mdef = er32(MDEF(i));
2887
2888
2889 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2890 continue;
2891
2892
2893 if (mdef)
2894 manc2h |= (1 << i);
2895
2896 j |= mdef;
2897 }
2898
2899 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2900 break;
2901
2902
2903 for (i = 0, j = 0; i < 8; i++)
2904 if (er32(MDEF(i)) == 0) {
2905 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2906 E1000_MDEF_PORT_664));
2907 manc2h |= (1 << 1);
2908 j++;
2909 break;
2910 }
2911
2912 if (!j)
2913 e_warn("Unable to create IPMI pass-through filter\n");
2914 break;
2915 }
2916
2917 ew32(MANC2H, manc2h);
2918 ew32(MANC, manc);
2919}
2920
2921
2922
2923
2924
2925
2926
2927static void e1000_configure_tx(struct e1000_adapter *adapter)
2928{
2929 struct e1000_hw *hw = &adapter->hw;
2930 struct e1000_ring *tx_ring = adapter->tx_ring;
2931 u64 tdba;
2932 u32 tdlen, tctl, tarc;
2933
2934
2935 tdba = tx_ring->dma;
2936 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2937 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2938 ew32(TDBAH(0), (tdba >> 32));
2939 ew32(TDLEN(0), tdlen);
2940 ew32(TDH(0), 0);
2941 ew32(TDT(0), 0);
2942 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2943 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2944
2945 writel(0, tx_ring->head);
2946 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2947 e1000e_update_tdt_wa(tx_ring, 0);
2948 else
2949 writel(0, tx_ring->tail);
2950
2951
2952 ew32(TIDV, adapter->tx_int_delay);
2953
2954 ew32(TADV, adapter->tx_abs_int_delay);
2955
2956 if (adapter->flags2 & FLAG2_DMA_BURST) {
2957 u32 txdctl = er32(TXDCTL(0));
2958
2959 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2960 E1000_TXDCTL_WTHRESH);
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2971 ew32(TXDCTL(0), txdctl);
2972 }
2973
2974 ew32(TXDCTL(1), er32(TXDCTL(0)));
2975
2976
2977 tctl = er32(TCTL);
2978 tctl &= ~E1000_TCTL_CT;
2979 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2980 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2981
2982 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2983 tarc = er32(TARC(0));
2984
2985
2986
2987#define SPEED_MODE_BIT (1 << 21)
2988 tarc |= SPEED_MODE_BIT;
2989 ew32(TARC(0), tarc);
2990 }
2991
2992
2993 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2994 tarc = er32(TARC(0));
2995 tarc |= 1;
2996 ew32(TARC(0), tarc);
2997 tarc = er32(TARC(1));
2998 tarc |= 1;
2999 ew32(TARC(1), tarc);
3000 }
3001
3002
3003 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
3004
3005
3006 if (adapter->tx_int_delay)
3007 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3008
3009
3010 adapter->txd_cmd |= E1000_TXD_CMD_RS;
3011
3012 ew32(TCTL, tctl);
3013
3014 hw->mac.ops.config_collision_dist(hw);
3015
3016
3017 if (hw->mac.type == e1000_pch_spt) {
3018 u32 reg_val;
3019
3020 reg_val = er32(IOSFPC);
3021 reg_val |= E1000_RCTL_RDMTS_HEX;
3022 ew32(IOSFPC, reg_val);
3023
3024 reg_val = er32(TARC(0));
3025 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ;
3026 ew32(TARC(0), reg_val);
3027 }
3028}
3029
3030
3031
3032
3033
3034#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3035 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3036static void e1000_setup_rctl(struct e1000_adapter *adapter)
3037{
3038 struct e1000_hw *hw = &adapter->hw;
3039 u32 rctl, rfctl;
3040 u32 pages = 0;
3041
3042
3043
3044
3045
3046 if (hw->mac.type >= e1000_pch2lan) {
3047 s32 ret_val;
3048
3049 if (adapter->netdev->mtu > ETH_DATA_LEN)
3050 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3051 else
3052 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3053
3054 if (ret_val)
3055 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3056 }
3057
3058
3059 rctl = er32(RCTL);
3060 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3061 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3062 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3063 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3064
3065
3066 rctl &= ~E1000_RCTL_SBP;
3067
3068
3069 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3070 rctl &= ~E1000_RCTL_LPE;
3071 else
3072 rctl |= E1000_RCTL_LPE;
3073
3074
3075
3076
3077
3078 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3079 rctl |= E1000_RCTL_SECRC;
3080
3081
3082 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3083 u16 phy_data;
3084
3085 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3086 phy_data &= 0xfff8;
3087 phy_data |= (1 << 2);
3088 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3089
3090 e1e_rphy(hw, 22, &phy_data);
3091 phy_data &= 0x0fff;
3092 phy_data |= (1 << 14);
3093 e1e_wphy(hw, 0x10, 0x2823);
3094 e1e_wphy(hw, 0x11, 0x0003);
3095 e1e_wphy(hw, 22, phy_data);
3096 }
3097
3098
3099 rctl &= ~E1000_RCTL_SZ_4096;
3100 rctl |= E1000_RCTL_BSEX;
3101 switch (adapter->rx_buffer_len) {
3102 case 2048:
3103 default:
3104 rctl |= E1000_RCTL_SZ_2048;
3105 rctl &= ~E1000_RCTL_BSEX;
3106 break;
3107 case 4096:
3108 rctl |= E1000_RCTL_SZ_4096;
3109 break;
3110 case 8192:
3111 rctl |= E1000_RCTL_SZ_8192;
3112 break;
3113 case 16384:
3114 rctl |= E1000_RCTL_SZ_16384;
3115 break;
3116 }
3117
3118
3119 rfctl = er32(RFCTL);
3120 rfctl |= E1000_RFCTL_EXTEN;
3121 ew32(RFCTL, rfctl);
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3138 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3139 adapter->rx_ps_pages = pages;
3140 else
3141 adapter->rx_ps_pages = 0;
3142
3143 if (adapter->rx_ps_pages) {
3144 u32 psrctl = 0;
3145
3146
3147 rctl |= E1000_RCTL_DTYP_PS;
3148
3149 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3150
3151 switch (adapter->rx_ps_pages) {
3152 case 3:
3153 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3154
3155 case 2:
3156 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3157
3158 case 1:
3159 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3160 break;
3161 }
3162
3163 ew32(PSRCTL, psrctl);
3164 }
3165
3166
3167 if (adapter->netdev->features & NETIF_F_RXALL) {
3168
3169
3170
3171 rctl |= (E1000_RCTL_SBP |
3172 E1000_RCTL_BAM |
3173 E1000_RCTL_PMCF);
3174
3175 rctl &= ~(E1000_RCTL_VFE |
3176 E1000_RCTL_DPF |
3177 E1000_RCTL_CFIEN);
3178
3179
3180
3181 }
3182
3183 ew32(RCTL, rctl);
3184
3185 adapter->flags &= ~FLAG_RESTART_NOW;
3186}
3187
3188
3189
3190
3191
3192
3193
3194static void e1000_configure_rx(struct e1000_adapter *adapter)
3195{
3196 struct e1000_hw *hw = &adapter->hw;
3197 struct e1000_ring *rx_ring = adapter->rx_ring;
3198 u64 rdba;
3199 u32 rdlen, rctl, rxcsum, ctrl_ext;
3200
3201 if (adapter->rx_ps_pages) {
3202
3203 rdlen = rx_ring->count *
3204 sizeof(union e1000_rx_desc_packet_split);
3205 adapter->clean_rx = e1000_clean_rx_irq_ps;
3206 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3207 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3208 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3209 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3210 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3211 } else {
3212 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3213 adapter->clean_rx = e1000_clean_rx_irq;
3214 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3215 }
3216
3217
3218 rctl = er32(RCTL);
3219 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3220 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3221 e1e_flush();
3222 usleep_range(10000, 20000);
3223
3224 if (adapter->flags2 & FLAG2_DMA_BURST) {
3225
3226
3227
3228
3229
3230
3231
3232
3233 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3234 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3235
3236
3237
3238
3239 if (adapter->rx_int_delay == DEFAULT_RDTR)
3240 adapter->rx_int_delay = BURST_RDTR;
3241 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3242 adapter->rx_abs_int_delay = BURST_RADV;
3243 }
3244
3245
3246 ew32(RDTR, adapter->rx_int_delay);
3247
3248
3249 ew32(RADV, adapter->rx_abs_int_delay);
3250 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3251 e1000e_write_itr(adapter, adapter->itr);
3252
3253 ctrl_ext = er32(CTRL_EXT);
3254
3255 ctrl_ext |= E1000_CTRL_EXT_IAME;
3256 ew32(IAM, 0xffffffff);
3257 ew32(CTRL_EXT, ctrl_ext);
3258 e1e_flush();
3259
3260
3261
3262
3263 rdba = rx_ring->dma;
3264 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3265 ew32(RDBAH(0), (rdba >> 32));
3266 ew32(RDLEN(0), rdlen);
3267 ew32(RDH(0), 0);
3268 ew32(RDT(0), 0);
3269 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3270 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3271
3272 writel(0, rx_ring->head);
3273 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3274 e1000e_update_rdt_wa(rx_ring, 0);
3275 else
3276 writel(0, rx_ring->tail);
3277
3278
3279 rxcsum = er32(RXCSUM);
3280 if (adapter->netdev->features & NETIF_F_RXCSUM)
3281 rxcsum |= E1000_RXCSUM_TUOFL;
3282 else
3283 rxcsum &= ~E1000_RXCSUM_TUOFL;
3284 ew32(RXCSUM, rxcsum);
3285
3286
3287
3288
3289 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3290 u32 lat =
3291 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3292 adapter->max_frame_size) * 8 / 1000;
3293
3294 if (adapter->flags & FLAG_IS_ICH) {
3295 u32 rxdctl = er32(RXDCTL(0));
3296
3297 ew32(RXDCTL(0), rxdctl | 0x3);
3298 }
3299
3300 pm_qos_update_request(&adapter->pm_qos_req, lat);
3301 } else {
3302 pm_qos_update_request(&adapter->pm_qos_req,
3303 PM_QOS_DEFAULT_VALUE);
3304 }
3305
3306
3307 ew32(RCTL, rctl);
3308}
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319static int e1000e_write_mc_addr_list(struct net_device *netdev)
3320{
3321 struct e1000_adapter *adapter = netdev_priv(netdev);
3322 struct e1000_hw *hw = &adapter->hw;
3323 struct netdev_hw_addr *ha;
3324 u8 *mta_list;
3325 int i;
3326
3327 if (netdev_mc_empty(netdev)) {
3328
3329 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3330 return 0;
3331 }
3332
3333 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3334 if (!mta_list)
3335 return -ENOMEM;
3336
3337
3338 i = 0;
3339 netdev_for_each_mc_addr(ha, netdev)
3340 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3341
3342 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3343 kfree(mta_list);
3344
3345 return netdev_mc_count(netdev);
3346}
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357static int e1000e_write_uc_addr_list(struct net_device *netdev)
3358{
3359 struct e1000_adapter *adapter = netdev_priv(netdev);
3360 struct e1000_hw *hw = &adapter->hw;
3361 unsigned int rar_entries;
3362 int count = 0;
3363
3364 rar_entries = hw->mac.ops.rar_get_count(hw);
3365
3366
3367 rar_entries--;
3368
3369
3370 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3371 rar_entries--;
3372
3373
3374 if (netdev_uc_count(netdev) > rar_entries)
3375 return -ENOMEM;
3376
3377 if (!netdev_uc_empty(netdev) && rar_entries) {
3378 struct netdev_hw_addr *ha;
3379
3380
3381
3382
3383 netdev_for_each_uc_addr(ha, netdev) {
3384 int rval;
3385
3386 if (!rar_entries)
3387 break;
3388 rval = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3389 if (rval < 0)
3390 return -ENOMEM;
3391 count++;
3392 }
3393 }
3394
3395
3396 for (; rar_entries > 0; rar_entries--) {
3397 ew32(RAH(rar_entries), 0);
3398 ew32(RAL(rar_entries), 0);
3399 }
3400 e1e_flush();
3401
3402 return count;
3403}
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414static void e1000e_set_rx_mode(struct net_device *netdev)
3415{
3416 struct e1000_adapter *adapter = netdev_priv(netdev);
3417 struct e1000_hw *hw = &adapter->hw;
3418 u32 rctl;
3419
3420 if (pm_runtime_suspended(netdev->dev.parent))
3421 return;
3422
3423
3424 rctl = er32(RCTL);
3425
3426
3427 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3428
3429 if (netdev->flags & IFF_PROMISC) {
3430 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3431
3432 e1000e_vlan_filter_disable(adapter);
3433 } else {
3434 int count;
3435
3436 if (netdev->flags & IFF_ALLMULTI) {
3437 rctl |= E1000_RCTL_MPE;
3438 } else {
3439
3440
3441
3442
3443 count = e1000e_write_mc_addr_list(netdev);
3444 if (count < 0)
3445 rctl |= E1000_RCTL_MPE;
3446 }
3447 e1000e_vlan_filter_enable(adapter);
3448
3449
3450
3451
3452 count = e1000e_write_uc_addr_list(netdev);
3453 if (count < 0)
3454 rctl |= E1000_RCTL_UPE;
3455 }
3456
3457 ew32(RCTL, rctl);
3458
3459 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3460 e1000e_vlan_strip_enable(adapter);
3461 else
3462 e1000e_vlan_strip_disable(adapter);
3463}
3464
3465static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3466{
3467 struct e1000_hw *hw = &adapter->hw;
3468 u32 mrqc, rxcsum;
3469 u32 rss_key[10];
3470 int i;
3471
3472 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3473 for (i = 0; i < 10; i++)
3474 ew32(RSSRK(i), rss_key[i]);
3475
3476
3477 for (i = 0; i < 32; i++)
3478 ew32(RETA(i), 0);
3479
3480
3481
3482
3483 rxcsum = er32(RXCSUM);
3484 rxcsum |= E1000_RXCSUM_PCSD;
3485
3486 ew32(RXCSUM, rxcsum);
3487
3488 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3489 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3490 E1000_MRQC_RSS_FIELD_IPV6 |
3491 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3492 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3493
3494 ew32(MRQC, mrqc);
3495}
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3506{
3507 struct e1000_hw *hw = &adapter->hw;
3508 u32 incvalue, incperiod, shift;
3509
3510
3511
3512
3513 if (((hw->mac.type == e1000_pch_lpt) ||
3514 (hw->mac.type == e1000_pch_spt)) &&
3515 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3516 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3517 u32 fextnvm7 = er32(FEXTNVM7);
3518
3519 if (!(fextnvm7 & (1 << 0))) {
3520 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3521 e1e_flush();
3522 }
3523 }
3524
3525 switch (hw->mac.type) {
3526 case e1000_pch2lan:
3527 case e1000_pch_lpt:
3528 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3529
3530 incperiod = INCPERIOD_96MHz;
3531 incvalue = INCVALUE_96MHz;
3532 shift = INCVALUE_SHIFT_96MHz;
3533 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3534 } else {
3535
3536 incperiod = INCPERIOD_25MHz;
3537 incvalue = INCVALUE_25MHz;
3538 shift = INCVALUE_SHIFT_25MHz;
3539 adapter->cc.shift = shift;
3540 }
3541 break;
3542 case e1000_pch_spt:
3543 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3544
3545 incperiod = INCPERIOD_24MHz;
3546 incvalue = INCVALUE_24MHz;
3547 shift = INCVALUE_SHIFT_24MHz;
3548 adapter->cc.shift = shift;
3549 break;
3550 }
3551 return -EINVAL;
3552 case e1000_82574:
3553 case e1000_82583:
3554
3555 incperiod = INCPERIOD_25MHz;
3556 incvalue = INCVALUE_25MHz;
3557 shift = INCVALUE_SHIFT_25MHz;
3558 adapter->cc.shift = shift;
3559 break;
3560 default:
3561 return -EINVAL;
3562 }
3563
3564 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3565 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3566
3567 return 0;
3568}
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3586 struct hwtstamp_config *config)
3587{
3588 struct e1000_hw *hw = &adapter->hw;
3589 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3590 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3591 u32 rxmtrl = 0;
3592 u16 rxudp = 0;
3593 bool is_l4 = false;
3594 bool is_l2 = false;
3595 u32 regval;
3596 s32 ret_val;
3597
3598 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3599 return -EINVAL;
3600
3601
3602 if (config->flags)
3603 return -EINVAL;
3604
3605 switch (config->tx_type) {
3606 case HWTSTAMP_TX_OFF:
3607 tsync_tx_ctl = 0;
3608 break;
3609 case HWTSTAMP_TX_ON:
3610 break;
3611 default:
3612 return -ERANGE;
3613 }
3614
3615 switch (config->rx_filter) {
3616 case HWTSTAMP_FILTER_NONE:
3617 tsync_rx_ctl = 0;
3618 break;
3619 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3620 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3621 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3622 is_l4 = true;
3623 break;
3624 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3625 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3626 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3627 is_l4 = true;
3628 break;
3629 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3630
3631 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3632 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3633 is_l2 = true;
3634 break;
3635 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3636
3637 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3638 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3639 is_l2 = true;
3640 break;
3641 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3642
3643
3644
3645 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3646
3647 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3648 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3649 is_l2 = true;
3650 is_l4 = true;
3651 break;
3652 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3653
3654
3655
3656 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3657
3658 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3659 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3660 is_l2 = true;
3661 is_l4 = true;
3662 break;
3663 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3664 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3665
3666
3667
3668 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3669 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3670 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3671 is_l2 = true;
3672 is_l4 = true;
3673 break;
3674 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3675
3676
3677
3678
3679 case HWTSTAMP_FILTER_ALL:
3680 is_l2 = true;
3681 is_l4 = true;
3682 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3683 config->rx_filter = HWTSTAMP_FILTER_ALL;
3684 break;
3685 default:
3686 return -ERANGE;
3687 }
3688
3689 adapter->hwtstamp_config = *config;
3690
3691
3692 regval = er32(TSYNCTXCTL);
3693 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3694 regval |= tsync_tx_ctl;
3695 ew32(TSYNCTXCTL, regval);
3696 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3697 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3698 e_err("Timesync Tx Control register not set as expected\n");
3699 return -EAGAIN;
3700 }
3701
3702
3703 regval = er32(TSYNCRXCTL);
3704 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3705 regval |= tsync_rx_ctl;
3706 ew32(TSYNCRXCTL, regval);
3707 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3708 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3709 (regval & (E1000_TSYNCRXCTL_ENABLED |
3710 E1000_TSYNCRXCTL_TYPE_MASK))) {
3711 e_err("Timesync Rx Control register not set as expected\n");
3712 return -EAGAIN;
3713 }
3714
3715
3716 if (is_l2)
3717 rxmtrl |= ETH_P_1588;
3718
3719
3720 ew32(RXMTRL, rxmtrl);
3721
3722
3723 if (is_l4) {
3724 rxudp = PTP_EV_PORT;
3725 cpu_to_be16s(&rxudp);
3726 }
3727 ew32(RXUDP, rxudp);
3728
3729 e1e_flush();
3730
3731
3732 er32(RXSTMPH);
3733 er32(TXSTMPH);
3734
3735
3736 ret_val = e1000e_get_base_timinca(adapter, ®val);
3737 if (ret_val)
3738 return ret_val;
3739 ew32(TIMINCA, regval);
3740
3741
3742 timecounter_init(&adapter->tc, &adapter->cc,
3743 ktime_to_ns(ktime_get_real()));
3744
3745 return 0;
3746}
3747
3748
3749
3750
3751
3752static void e1000_configure(struct e1000_adapter *adapter)
3753{
3754 struct e1000_ring *rx_ring = adapter->rx_ring;
3755
3756 e1000e_set_rx_mode(adapter->netdev);
3757
3758 e1000_restore_vlan(adapter);
3759 e1000_init_manageability_pt(adapter);
3760
3761 e1000_configure_tx(adapter);
3762
3763 if (adapter->netdev->features & NETIF_F_RXHASH)
3764 e1000e_setup_rss_hash(adapter);
3765 e1000_setup_rctl(adapter);
3766 e1000_configure_rx(adapter);
3767 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3768}
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778void e1000e_power_up_phy(struct e1000_adapter *adapter)
3779{
3780 if (adapter->hw.phy.ops.power_up)
3781 adapter->hw.phy.ops.power_up(&adapter->hw);
3782
3783 adapter->hw.mac.ops.setup_link(&adapter->hw);
3784}
3785
3786
3787
3788
3789
3790
3791
3792static void e1000_power_down_phy(struct e1000_adapter *adapter)
3793{
3794 if (adapter->hw.phy.ops.power_down)
3795 adapter->hw.phy.ops.power_down(&adapter->hw);
3796}
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3807{
3808 struct e1000_hw *hw = &adapter->hw;
3809 struct e1000_ring *tx_ring = adapter->tx_ring;
3810 struct e1000_tx_desc *tx_desc = NULL;
3811 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3812 u16 size = 512;
3813
3814 tctl = er32(TCTL);
3815 ew32(TCTL, tctl | E1000_TCTL_EN);
3816 tdt = er32(TDT(0));
3817 BUG_ON(tdt != tx_ring->next_to_use);
3818 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3819 tx_desc->buffer_addr = tx_ring->dma;
3820
3821 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3822 tx_desc->upper.data = 0;
3823
3824 wmb();
3825 tx_ring->next_to_use++;
3826 if (tx_ring->next_to_use == tx_ring->count)
3827 tx_ring->next_to_use = 0;
3828 ew32(TDT(0), tx_ring->next_to_use);
3829 mmiowb();
3830 usleep_range(200, 250);
3831}
3832
3833
3834
3835
3836
3837
3838static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3839{
3840 u32 rctl, rxdctl;
3841 struct e1000_hw *hw = &adapter->hw;
3842
3843 rctl = er32(RCTL);
3844 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3845 e1e_flush();
3846 usleep_range(100, 150);
3847
3848 rxdctl = er32(RXDCTL(0));
3849
3850 rxdctl &= 0xffffc000;
3851
3852
3853
3854
3855 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3856
3857 ew32(RXDCTL(0), rxdctl);
3858
3859 ew32(RCTL, rctl | E1000_RCTL_EN);
3860 e1e_flush();
3861 usleep_range(100, 150);
3862 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3863}
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3877{
3878 u16 hang_state;
3879 u32 fext_nvm11, tdlen;
3880 struct e1000_hw *hw = &adapter->hw;
3881
3882
3883 fext_nvm11 = er32(FEXTNVM11);
3884 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3885 ew32(FEXTNVM11, fext_nvm11);
3886
3887 tdlen = er32(TDLEN(0));
3888 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3889 &hang_state);
3890 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3891 return;
3892 e1000_flush_tx_ring(adapter);
3893
3894 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3895 &hang_state);
3896 if (hang_state & FLUSH_DESC_REQUIRED)
3897 e1000_flush_rx_ring(adapter);
3898}
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908void e1000e_reset(struct e1000_adapter *adapter)
3909{
3910 struct e1000_mac_info *mac = &adapter->hw.mac;
3911 struct e1000_fc_info *fc = &adapter->hw.fc;
3912 struct e1000_hw *hw = &adapter->hw;
3913 u32 tx_space, min_tx_space, min_rx_space;
3914 u32 pba = adapter->pba;
3915 u16 hwm;
3916
3917
3918 ew32(PBA, pba);
3919
3920 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3921
3922
3923
3924
3925
3926
3927
3928 pba = er32(PBA);
3929
3930 tx_space = pba >> 16;
3931
3932 pba &= 0xffff;
3933
3934
3935
3936 min_tx_space = (adapter->max_frame_size +
3937 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3938 min_tx_space = ALIGN(min_tx_space, 1024);
3939 min_tx_space >>= 10;
3940
3941 min_rx_space = adapter->max_frame_size;
3942 min_rx_space = ALIGN(min_rx_space, 1024);
3943 min_rx_space >>= 10;
3944
3945
3946
3947
3948
3949 if ((tx_space < min_tx_space) &&
3950 ((min_tx_space - tx_space) < pba)) {
3951 pba -= min_tx_space - tx_space;
3952
3953
3954
3955
3956 if (pba < min_rx_space)
3957 pba = min_rx_space;
3958 }
3959
3960 ew32(PBA, pba);
3961 }
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3972 fc->pause_time = 0xFFFF;
3973 else
3974 fc->pause_time = E1000_FC_PAUSE_TIME;
3975 fc->send_xon = true;
3976 fc->current_mode = fc->requested_mode;
3977
3978 switch (hw->mac.type) {
3979 case e1000_ich9lan:
3980 case e1000_ich10lan:
3981 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3982 pba = 14;
3983 ew32(PBA, pba);
3984 fc->high_water = 0x2800;
3985 fc->low_water = fc->high_water - 8;
3986 break;
3987 }
3988
3989 default:
3990 hwm = min(((pba << 10) * 9 / 10),
3991 ((pba << 10) - adapter->max_frame_size));
3992
3993 fc->high_water = hwm & E1000_FCRTH_RTH;
3994 fc->low_water = fc->high_water - 8;
3995 break;
3996 case e1000_pchlan:
3997
3998
3999
4000 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4001 fc->high_water = 0x3500;
4002 fc->low_water = 0x1500;
4003 } else {
4004 fc->high_water = 0x5000;
4005 fc->low_water = 0x3000;
4006 }
4007 fc->refresh_time = 0x1000;
4008 break;
4009 case e1000_pch2lan:
4010 case e1000_pch_lpt:
4011 case e1000_pch_spt:
4012 fc->refresh_time = 0x0400;
4013
4014 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4015 fc->high_water = 0x05C20;
4016 fc->low_water = 0x05048;
4017 fc->pause_time = 0x0650;
4018 break;
4019 }
4020
4021 pba = 14;
4022 ew32(PBA, pba);
4023 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4024 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4025 break;
4026 }
4027
4028
4029
4030
4031
4032
4033 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4034 24 << 10);
4035
4036
4037
4038
4039 if (adapter->itr_setting & 0x3) {
4040 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4041 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4042 dev_info(&adapter->pdev->dev,
4043 "Interrupt Throttle Rate off\n");
4044 adapter->flags2 |= FLAG2_DISABLE_AIM;
4045 e1000e_write_itr(adapter, 0);
4046 }
4047 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4048 dev_info(&adapter->pdev->dev,
4049 "Interrupt Throttle Rate on\n");
4050 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4051 adapter->itr = 20000;
4052 e1000e_write_itr(adapter, adapter->itr);
4053 }
4054 }
4055
4056 if (hw->mac.type == e1000_pch_spt)
4057 e1000_flush_desc_rings(adapter);
4058
4059 mac->ops.reset_hw(hw);
4060
4061
4062
4063
4064 if (adapter->flags & FLAG_HAS_AMT)
4065 e1000e_get_hw_control(adapter);
4066
4067 ew32(WUC, 0);
4068
4069 if (mac->ops.init_hw(hw))
4070 e_err("Hardware Error\n");
4071
4072 e1000_update_mng_vlan(adapter);
4073
4074
4075 ew32(VET, ETH_P_8021Q);
4076
4077 e1000e_reset_adaptive(hw);
4078
4079
4080 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
4081
4082
4083 if (adapter->flags2 & FLAG2_HAS_EEE) {
4084 s32 ret_val;
4085 u16 adv_addr;
4086
4087 switch (hw->phy.type) {
4088 case e1000_phy_82579:
4089 adv_addr = I82579_EEE_ADVERTISEMENT;
4090 break;
4091 case e1000_phy_i217:
4092 adv_addr = I217_EEE_ADVERTISEMENT;
4093 break;
4094 default:
4095 dev_err(&adapter->pdev->dev,
4096 "Invalid PHY type setting EEE advertisement\n");
4097 return;
4098 }
4099
4100 ret_val = hw->phy.ops.acquire(hw);
4101 if (ret_val) {
4102 dev_err(&adapter->pdev->dev,
4103 "EEE advertisement - unable to acquire PHY\n");
4104 return;
4105 }
4106
4107 e1000_write_emi_reg_locked(hw, adv_addr,
4108 hw->dev_spec.ich8lan.eee_disable ?
4109 0 : adapter->eee_advert);
4110
4111 hw->phy.ops.release(hw);
4112 }
4113
4114 if (!netif_running(adapter->netdev) &&
4115 !test_bit(__E1000_TESTING, &adapter->state))
4116 e1000_power_down_phy(adapter);
4117
4118 e1000_get_phy_info(hw);
4119
4120 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4121 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4122 u16 phy_data = 0;
4123
4124
4125
4126
4127 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4128 phy_data &= ~IGP02E1000_PM_SPD;
4129 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4130 }
4131 if (hw->mac.type == e1000_pch_spt && adapter->int_mode == 0) {
4132 u32 reg;
4133
4134
4135 reg = er32(FEXTNVM7);
4136 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4137 ew32(FEXTNVM7, reg);
4138
4139 reg = er32(FEXTNVM9);
4140 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4141 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4142 ew32(FEXTNVM9, reg);
4143 }
4144
4145}
4146
4147int e1000e_up(struct e1000_adapter *adapter)
4148{
4149 struct e1000_hw *hw = &adapter->hw;
4150
4151
4152 e1000_configure(adapter);
4153
4154 clear_bit(__E1000_DOWN, &adapter->state);
4155
4156 if (adapter->msix_entries)
4157 e1000_configure_msix(adapter);
4158 e1000_irq_enable(adapter);
4159
4160 netif_start_queue(adapter->netdev);
4161
4162
4163 if (adapter->msix_entries)
4164 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4165 else
4166 ew32(ICS, E1000_ICS_LSC);
4167
4168 return 0;
4169}
4170
4171static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4172{
4173 struct e1000_hw *hw = &adapter->hw;
4174
4175 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4176 return;
4177
4178
4179 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4180 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4181
4182
4183 e1e_flush();
4184
4185
4186
4187
4188 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4189 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4190
4191
4192 e1e_flush();
4193}
4194
4195static void e1000e_update_stats(struct e1000_adapter *adapter);
4196
4197
4198
4199
4200
4201
4202void e1000e_down(struct e1000_adapter *adapter, bool reset)
4203{
4204 struct net_device *netdev = adapter->netdev;
4205 struct e1000_hw *hw = &adapter->hw;
4206 u32 tctl, rctl;
4207
4208
4209
4210
4211 set_bit(__E1000_DOWN, &adapter->state);
4212
4213 netif_carrier_off(netdev);
4214
4215
4216 rctl = er32(RCTL);
4217 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4218 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4219
4220
4221 netif_stop_queue(netdev);
4222
4223
4224 tctl = er32(TCTL);
4225 tctl &= ~E1000_TCTL_EN;
4226 ew32(TCTL, tctl);
4227
4228
4229 e1e_flush();
4230 usleep_range(10000, 20000);
4231
4232 e1000_irq_disable(adapter);
4233
4234 napi_synchronize(&adapter->napi);
4235
4236 del_timer_sync(&adapter->watchdog_timer);
4237 del_timer_sync(&adapter->phy_info_timer);
4238
4239 spin_lock(&adapter->stats64_lock);
4240 e1000e_update_stats(adapter);
4241 spin_unlock(&adapter->stats64_lock);
4242
4243 e1000e_flush_descriptors(adapter);
4244
4245 adapter->link_speed = 0;
4246 adapter->link_duplex = 0;
4247
4248
4249 if ((hw->mac.type >= e1000_pch2lan) &&
4250 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4251 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4252 e_dbg("failed to disable jumbo frame workaround mode\n");
4253
4254 if (!pci_channel_offline(adapter->pdev)) {
4255 if (reset)
4256 e1000e_reset(adapter);
4257 else if (hw->mac.type == e1000_pch_spt)
4258 e1000_flush_desc_rings(adapter);
4259 }
4260 e1000_clean_tx_ring(adapter->tx_ring);
4261 e1000_clean_rx_ring(adapter->rx_ring);
4262}
4263
4264void e1000e_reinit_locked(struct e1000_adapter *adapter)
4265{
4266 might_sleep();
4267 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4268 usleep_range(1000, 2000);
4269 e1000e_down(adapter, true);
4270 e1000e_up(adapter);
4271 clear_bit(__E1000_RESETTING, &adapter->state);
4272}
4273
4274
4275
4276
4277
4278static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4279{
4280 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4281 cc);
4282 struct e1000_hw *hw = &adapter->hw;
4283 u32 systimel_1, systimel_2, systimeh;
4284 cycle_t systim, systim_next;
4285
4286
4287
4288
4289
4290
4291 systimel_1 = er32(SYSTIML);
4292 systimeh = er32(SYSTIMH);
4293 systimel_2 = er32(SYSTIML);
4294
4295 if (systimel_1 < systimel_2) {
4296 systim = (cycle_t)systimel_1;
4297 systim |= (cycle_t)systimeh << 32;
4298 } else {
4299
4300
4301
4302 systimeh = er32(SYSTIMH);
4303 systim = (cycle_t)systimel_2;
4304 systim |= (cycle_t)systimeh << 32;
4305 }
4306
4307 if ((hw->mac.type == e1000_82574) || (hw->mac.type == e1000_82583)) {
4308 u64 incvalue, time_delta, rem, temp;
4309 int i;
4310
4311
4312
4313
4314
4315 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4316 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4317
4318 systim_next = (cycle_t)er32(SYSTIML);
4319 systim_next |= (cycle_t)er32(SYSTIMH) << 32;
4320
4321 time_delta = systim_next - systim;
4322 temp = time_delta;
4323 rem = do_div(temp, incvalue);
4324
4325 systim = systim_next;
4326
4327 if ((time_delta < E1000_82574_SYSTIM_EPSILON) &&
4328 (rem == 0))
4329 break;
4330 }
4331 }
4332 return systim;
4333}
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343static int e1000_sw_init(struct e1000_adapter *adapter)
4344{
4345 struct net_device *netdev = adapter->netdev;
4346
4347 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4348 adapter->rx_ps_bsize0 = 128;
4349 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4350 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4351 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4352 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4353
4354 spin_lock_init(&adapter->stats64_lock);
4355
4356 e1000e_set_interrupt_capability(adapter);
4357
4358 if (e1000_alloc_queues(adapter))
4359 return -ENOMEM;
4360
4361
4362 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4363 adapter->cc.read = e1000e_cyclecounter_read;
4364 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4365 adapter->cc.mult = 1;
4366
4367
4368 spin_lock_init(&adapter->systim_lock);
4369 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4370 }
4371
4372
4373 e1000_irq_disable(adapter);
4374
4375 set_bit(__E1000_DOWN, &adapter->state);
4376 return 0;
4377}
4378
4379
4380
4381
4382
4383
4384static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4385{
4386 struct net_device *netdev = data;
4387 struct e1000_adapter *adapter = netdev_priv(netdev);
4388 struct e1000_hw *hw = &adapter->hw;
4389 u32 icr = er32(ICR);
4390
4391 e_dbg("icr is %08X\n", icr);
4392 if (icr & E1000_ICR_RXSEQ) {
4393 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4394
4395
4396
4397 wmb();
4398 }
4399
4400 return IRQ_HANDLED;
4401}
4402
4403
4404
4405
4406
4407
4408
4409static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4410{
4411 struct net_device *netdev = adapter->netdev;
4412 struct e1000_hw *hw = &adapter->hw;
4413 int err;
4414
4415
4416
4417 er32(ICR);
4418
4419
4420 e1000_free_irq(adapter);
4421 e1000e_reset_interrupt_capability(adapter);
4422
4423
4424
4425
4426 adapter->flags |= FLAG_MSI_TEST_FAILED;
4427
4428 err = pci_enable_msi(adapter->pdev);
4429 if (err)
4430 goto msi_test_failed;
4431
4432 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4433 netdev->name, netdev);
4434 if (err) {
4435 pci_disable_msi(adapter->pdev);
4436 goto msi_test_failed;
4437 }
4438
4439
4440
4441
4442 wmb();
4443
4444 e1000_irq_enable(adapter);
4445
4446
4447 ew32(ICS, E1000_ICS_RXSEQ);
4448 e1e_flush();
4449 msleep(100);
4450
4451 e1000_irq_disable(adapter);
4452
4453 rmb();
4454
4455 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4456 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4457 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4458 } else {
4459 e_dbg("MSI interrupt test succeeded!\n");
4460 }
4461
4462 free_irq(adapter->pdev->irq, netdev);
4463 pci_disable_msi(adapter->pdev);
4464
4465msi_test_failed:
4466 e1000e_set_interrupt_capability(adapter);
4467 return e1000_request_irq(adapter);
4468}
4469
4470
4471
4472
4473
4474
4475
4476static int e1000_test_msi(struct e1000_adapter *adapter)
4477{
4478 int err;
4479 u16 pci_cmd;
4480
4481 if (!(adapter->flags & FLAG_MSI_ENABLED))
4482 return 0;
4483
4484
4485 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4486 if (pci_cmd & PCI_COMMAND_SERR)
4487 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4488 pci_cmd & ~PCI_COMMAND_SERR);
4489
4490 err = e1000_test_msi_interrupt(adapter);
4491
4492
4493 if (pci_cmd & PCI_COMMAND_SERR) {
4494 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4495 pci_cmd |= PCI_COMMAND_SERR;
4496 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4497 }
4498
4499 return err;
4500}
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514static int e1000_open(struct net_device *netdev)
4515{
4516 struct e1000_adapter *adapter = netdev_priv(netdev);
4517 struct e1000_hw *hw = &adapter->hw;
4518 struct pci_dev *pdev = adapter->pdev;
4519 int err;
4520
4521
4522 if (test_bit(__E1000_TESTING, &adapter->state))
4523 return -EBUSY;
4524
4525 pm_runtime_get_sync(&pdev->dev);
4526
4527 netif_carrier_off(netdev);
4528
4529
4530 err = e1000e_setup_tx_resources(adapter->tx_ring);
4531 if (err)
4532 goto err_setup_tx;
4533
4534
4535 err = e1000e_setup_rx_resources(adapter->rx_ring);
4536 if (err)
4537 goto err_setup_rx;
4538
4539
4540
4541
4542 if (adapter->flags & FLAG_HAS_AMT) {
4543 e1000e_get_hw_control(adapter);
4544 e1000e_reset(adapter);
4545 }
4546
4547 e1000e_power_up_phy(adapter);
4548
4549 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4550 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4551 e1000_update_mng_vlan(adapter);
4552
4553
4554 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4555 PM_QOS_DEFAULT_VALUE);
4556
4557
4558
4559
4560
4561
4562 e1000_configure(adapter);
4563
4564 err = e1000_request_irq(adapter);
4565 if (err)
4566 goto err_req_irq;
4567
4568
4569
4570
4571
4572 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4573 err = e1000_test_msi(adapter);
4574 if (err) {
4575 e_err("Interrupt allocation failed\n");
4576 goto err_req_irq;
4577 }
4578 }
4579
4580
4581 clear_bit(__E1000_DOWN, &adapter->state);
4582
4583 napi_enable(&adapter->napi);
4584
4585 e1000_irq_enable(adapter);
4586
4587 adapter->tx_hang_recheck = false;
4588 netif_start_queue(netdev);
4589
4590 hw->mac.get_link_status = true;
4591 pm_runtime_put(&pdev->dev);
4592
4593
4594 if (adapter->msix_entries)
4595 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4596 else
4597 ew32(ICS, E1000_ICS_LSC);
4598
4599 return 0;
4600
4601err_req_irq:
4602 pm_qos_remove_request(&adapter->pm_qos_req);
4603 e1000e_release_hw_control(adapter);
4604 e1000_power_down_phy(adapter);
4605 e1000e_free_rx_resources(adapter->rx_ring);
4606err_setup_rx:
4607 e1000e_free_tx_resources(adapter->tx_ring);
4608err_setup_tx:
4609 e1000e_reset(adapter);
4610 pm_runtime_put_sync(&pdev->dev);
4611
4612 return err;
4613}
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626static int e1000_close(struct net_device *netdev)
4627{
4628 struct e1000_adapter *adapter = netdev_priv(netdev);
4629 struct pci_dev *pdev = adapter->pdev;
4630 int count = E1000_CHECK_RESET_COUNT;
4631
4632 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4633 usleep_range(10000, 20000);
4634
4635 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4636
4637 pm_runtime_get_sync(&pdev->dev);
4638
4639 if (!test_bit(__E1000_DOWN, &adapter->state)) {
4640 e1000e_down(adapter, true);
4641 e1000_free_irq(adapter);
4642
4643
4644 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
4645 }
4646
4647 napi_disable(&adapter->napi);
4648
4649 e1000e_free_tx_resources(adapter->tx_ring);
4650 e1000e_free_rx_resources(adapter->rx_ring);
4651
4652
4653
4654
4655 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4656 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4657 adapter->mng_vlan_id);
4658
4659
4660
4661
4662 if ((adapter->flags & FLAG_HAS_AMT) &&
4663 !test_bit(__E1000_TESTING, &adapter->state))
4664 e1000e_release_hw_control(adapter);
4665
4666 pm_qos_remove_request(&adapter->pm_qos_req);
4667
4668 pm_runtime_put_sync(&pdev->dev);
4669
4670 return 0;
4671}
4672
4673
4674
4675
4676
4677
4678
4679
4680static int e1000_set_mac(struct net_device *netdev, void *p)
4681{
4682 struct e1000_adapter *adapter = netdev_priv(netdev);
4683 struct e1000_hw *hw = &adapter->hw;
4684 struct sockaddr *addr = p;
4685
4686 if (!is_valid_ether_addr(addr->sa_data))
4687 return -EADDRNOTAVAIL;
4688
4689 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4690 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4691
4692 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4693
4694 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4695
4696 e1000e_set_laa_state_82571(&adapter->hw, 1);
4697
4698
4699
4700
4701
4702
4703
4704
4705 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4706 adapter->hw.mac.rar_entry_count - 1);
4707 }
4708
4709 return 0;
4710}
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720static void e1000e_update_phy_task(struct work_struct *work)
4721{
4722 struct e1000_adapter *adapter = container_of(work,
4723 struct e1000_adapter,
4724 update_phy_task);
4725 struct e1000_hw *hw = &adapter->hw;
4726
4727 if (test_bit(__E1000_DOWN, &adapter->state))
4728 return;
4729
4730 e1000_get_phy_info(hw);
4731
4732
4733 if (hw->phy.type >= e1000_phy_82579)
4734 e1000_set_eee_pchlan(hw);
4735}
4736
4737
4738
4739
4740
4741
4742
4743
4744static void e1000_update_phy_info(unsigned long data)
4745{
4746 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
4747
4748 if (test_bit(__E1000_DOWN, &adapter->state))
4749 return;
4750
4751 schedule_work(&adapter->update_phy_task);
4752}
4753
4754
4755
4756
4757
4758
4759
4760static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4761{
4762 struct e1000_hw *hw = &adapter->hw;
4763 s32 ret_val;
4764 u16 phy_data;
4765
4766 ret_val = hw->phy.ops.acquire(hw);
4767 if (ret_val)
4768 return;
4769
4770
4771
4772
4773 hw->phy.addr = 1;
4774 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4775 &phy_data);
4776 if (ret_val)
4777 goto release;
4778 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4779 ret_val = hw->phy.ops.set_page(hw,
4780 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4781 if (ret_val)
4782 goto release;
4783 }
4784
4785
4786 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4787 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4788 if (!ret_val)
4789 adapter->stats.scc += phy_data;
4790
4791
4792 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4793 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4794 if (!ret_val)
4795 adapter->stats.ecol += phy_data;
4796
4797
4798 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4799 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4800 if (!ret_val)
4801 adapter->stats.mcc += phy_data;
4802
4803
4804 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4805 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4806 if (!ret_val)
4807 adapter->stats.latecol += phy_data;
4808
4809
4810 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4811 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4812 if (!ret_val)
4813 hw->mac.collision_delta = phy_data;
4814
4815
4816 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4817 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4818 if (!ret_val)
4819 adapter->stats.dc += phy_data;
4820
4821
4822 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4823 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4824 if (!ret_val)
4825 adapter->stats.tncrs += phy_data;
4826
4827release:
4828 hw->phy.ops.release(hw);
4829}
4830
4831
4832
4833
4834
4835static void e1000e_update_stats(struct e1000_adapter *adapter)
4836{
4837 struct net_device *netdev = adapter->netdev;
4838 struct e1000_hw *hw = &adapter->hw;
4839 struct pci_dev *pdev = adapter->pdev;
4840
4841
4842
4843
4844 if (adapter->link_speed == 0)
4845 return;
4846 if (pci_channel_offline(pdev))
4847 return;
4848
4849 adapter->stats.crcerrs += er32(CRCERRS);
4850 adapter->stats.gprc += er32(GPRC);
4851 adapter->stats.gorc += er32(GORCL);
4852 er32(GORCH);
4853 adapter->stats.bprc += er32(BPRC);
4854 adapter->stats.mprc += er32(MPRC);
4855 adapter->stats.roc += er32(ROC);
4856
4857 adapter->stats.mpc += er32(MPC);
4858
4859
4860 if (adapter->link_duplex == HALF_DUPLEX) {
4861 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4862 e1000e_update_phy_stats(adapter);
4863 } else {
4864 adapter->stats.scc += er32(SCC);
4865 adapter->stats.ecol += er32(ECOL);
4866 adapter->stats.mcc += er32(MCC);
4867 adapter->stats.latecol += er32(LATECOL);
4868 adapter->stats.dc += er32(DC);
4869
4870 hw->mac.collision_delta = er32(COLC);
4871
4872 if ((hw->mac.type != e1000_82574) &&
4873 (hw->mac.type != e1000_82583))
4874 adapter->stats.tncrs += er32(TNCRS);
4875 }
4876 adapter->stats.colc += hw->mac.collision_delta;
4877 }
4878
4879 adapter->stats.xonrxc += er32(XONRXC);
4880 adapter->stats.xontxc += er32(XONTXC);
4881 adapter->stats.xoffrxc += er32(XOFFRXC);
4882 adapter->stats.xofftxc += er32(XOFFTXC);
4883 adapter->stats.gptc += er32(GPTC);
4884 adapter->stats.gotc += er32(GOTCL);
4885 er32(GOTCH);
4886 adapter->stats.rnbc += er32(RNBC);
4887 adapter->stats.ruc += er32(RUC);
4888
4889 adapter->stats.mptc += er32(MPTC);
4890 adapter->stats.bptc += er32(BPTC);
4891
4892
4893
4894 hw->mac.tx_packet_delta = er32(TPT);
4895 adapter->stats.tpt += hw->mac.tx_packet_delta;
4896
4897 adapter->stats.algnerrc += er32(ALGNERRC);
4898 adapter->stats.rxerrc += er32(RXERRC);
4899 adapter->stats.cexterr += er32(CEXTERR);
4900 adapter->stats.tsctc += er32(TSCTC);
4901 adapter->stats.tsctfc += er32(TSCTFC);
4902
4903
4904 netdev->stats.multicast = adapter->stats.mprc;
4905 netdev->stats.collisions = adapter->stats.colc;
4906
4907
4908
4909
4910
4911
4912 netdev->stats.rx_errors = adapter->stats.rxerrc +
4913 adapter->stats.crcerrs + adapter->stats.algnerrc +
4914 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
4915 netdev->stats.rx_length_errors = adapter->stats.ruc +
4916 adapter->stats.roc;
4917 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4918 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4919 netdev->stats.rx_missed_errors = adapter->stats.mpc;
4920
4921
4922 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
4923 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4924 netdev->stats.tx_window_errors = adapter->stats.latecol;
4925 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
4926
4927
4928
4929
4930 adapter->stats.mgptc += er32(MGTPTC);
4931 adapter->stats.mgprc += er32(MGTPRC);
4932 adapter->stats.mgpdc += er32(MGTPDC);
4933
4934
4935 if ((hw->mac.type == e1000_pch_lpt) ||
4936 (hw->mac.type == e1000_pch_spt)) {
4937 u32 pbeccsts = er32(PBECCSTS);
4938
4939 adapter->corr_errors +=
4940 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4941 adapter->uncorr_errors +=
4942 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4943 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4944 }
4945}
4946
4947
4948
4949
4950
4951static void e1000_phy_read_status(struct e1000_adapter *adapter)
4952{
4953 struct e1000_hw *hw = &adapter->hw;
4954 struct e1000_phy_regs *phy = &adapter->phy_regs;
4955
4956 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
4957 (er32(STATUS) & E1000_STATUS_LU) &&
4958 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
4959 int ret_val;
4960
4961 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4962 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4963 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4964 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4965 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4966 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4967 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4968 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
4969 if (ret_val)
4970 e_warn("Error reading PHY register\n");
4971 } else {
4972
4973
4974
4975 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4976 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4977 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4978 BMSR_ERCAP);
4979 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4980 ADVERTISE_ALL | ADVERTISE_CSMA);
4981 phy->lpa = 0;
4982 phy->expansion = EXPANSION_ENABLENPAGE;
4983 phy->ctrl1000 = ADVERTISE_1000FULL;
4984 phy->stat1000 = 0;
4985 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4986 }
4987}
4988
4989static void e1000_print_link_info(struct e1000_adapter *adapter)
4990{
4991 struct e1000_hw *hw = &adapter->hw;
4992 u32 ctrl = er32(CTRL);
4993
4994
4995 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4996 adapter->netdev->name, adapter->link_speed,
4997 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4998 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4999 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5000 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5001}
5002
5003static bool e1000e_has_link(struct e1000_adapter *adapter)
5004{
5005 struct e1000_hw *hw = &adapter->hw;
5006 bool link_active = false;
5007 s32 ret_val = 0;
5008
5009
5010
5011
5012
5013
5014 switch (hw->phy.media_type) {
5015 case e1000_media_type_copper:
5016 if (hw->mac.get_link_status) {
5017 ret_val = hw->mac.ops.check_for_link(hw);
5018 link_active = !hw->mac.get_link_status;
5019 } else {
5020 link_active = true;
5021 }
5022 break;
5023 case e1000_media_type_fiber:
5024 ret_val = hw->mac.ops.check_for_link(hw);
5025 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5026 break;
5027 case e1000_media_type_internal_serdes:
5028 ret_val = hw->mac.ops.check_for_link(hw);
5029 link_active = adapter->hw.mac.serdes_has_link;
5030 break;
5031 default:
5032 case e1000_media_type_unknown:
5033 break;
5034 }
5035
5036 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5037 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5038
5039 e_info("Gigabit has been disabled, downgrading speed\n");
5040 }
5041
5042 return link_active;
5043}
5044
5045static void e1000e_enable_receives(struct e1000_adapter *adapter)
5046{
5047
5048 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5049 (adapter->flags & FLAG_RESTART_NOW)) {
5050 struct e1000_hw *hw = &adapter->hw;
5051 u32 rctl = er32(RCTL);
5052
5053 ew32(RCTL, rctl | E1000_RCTL_EN);
5054 adapter->flags &= ~FLAG_RESTART_NOW;
5055 }
5056}
5057
5058static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5059{
5060 struct e1000_hw *hw = &adapter->hw;
5061
5062
5063
5064
5065 if (e1000_check_phy_82574(hw))
5066 adapter->phy_hang_count++;
5067 else
5068 adapter->phy_hang_count = 0;
5069
5070 if (adapter->phy_hang_count > 1) {
5071 adapter->phy_hang_count = 0;
5072 e_dbg("PHY appears hung - resetting\n");
5073 schedule_work(&adapter->reset_task);
5074 }
5075}
5076
5077
5078
5079
5080
5081static void e1000_watchdog(unsigned long data)
5082{
5083 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
5084
5085
5086 schedule_work(&adapter->watchdog_task);
5087
5088
5089}
5090
5091static void e1000_watchdog_task(struct work_struct *work)
5092{
5093 struct e1000_adapter *adapter = container_of(work,
5094 struct e1000_adapter,
5095 watchdog_task);
5096 struct net_device *netdev = adapter->netdev;
5097 struct e1000_mac_info *mac = &adapter->hw.mac;
5098 struct e1000_phy_info *phy = &adapter->hw.phy;
5099 struct e1000_ring *tx_ring = adapter->tx_ring;
5100 struct e1000_hw *hw = &adapter->hw;
5101 u32 link, tctl;
5102
5103 if (test_bit(__E1000_DOWN, &adapter->state))
5104 return;
5105
5106 link = e1000e_has_link(adapter);
5107 if ((netif_carrier_ok(netdev)) && link) {
5108
5109 pm_runtime_resume(netdev->dev.parent);
5110
5111 e1000e_enable_receives(adapter);
5112 goto link_up;
5113 }
5114
5115 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5116 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5117 e1000_update_mng_vlan(adapter);
5118
5119 if (link) {
5120 if (!netif_carrier_ok(netdev)) {
5121 bool txb2b = true;
5122
5123
5124 pm_runtime_resume(netdev->dev.parent);
5125
5126
5127 e1000_phy_read_status(adapter);
5128 mac->ops.get_link_up_info(&adapter->hw,
5129 &adapter->link_speed,
5130 &adapter->link_duplex);
5131 e1000_print_link_info(adapter);
5132
5133
5134 e1000e_check_downshift(hw);
5135 if (phy->speed_downgraded)
5136 netdev_warn(netdev,
5137 "Link Speed was downgraded by SmartSpeed\n");
5138
5139
5140
5141
5142 if ((hw->phy.type == e1000_phy_igp_3 ||
5143 hw->phy.type == e1000_phy_bm) &&
5144 hw->mac.autoneg &&
5145 (adapter->link_speed == SPEED_10 ||
5146 adapter->link_speed == SPEED_100) &&
5147 (adapter->link_duplex == HALF_DUPLEX)) {
5148 u16 autoneg_exp;
5149
5150 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5151
5152 if (!(autoneg_exp & EXPANSION_NWAY))
5153 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5154 }
5155
5156
5157 adapter->tx_timeout_factor = 1;
5158 switch (adapter->link_speed) {
5159 case SPEED_10:
5160 txb2b = false;
5161 adapter->tx_timeout_factor = 16;
5162 break;
5163 case SPEED_100:
5164 txb2b = false;
5165 adapter->tx_timeout_factor = 10;
5166 break;
5167 }
5168
5169
5170
5171
5172 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5173 !txb2b) {
5174 u32 tarc0;
5175
5176 tarc0 = er32(TARC(0));
5177 tarc0 &= ~SPEED_MODE_BIT;
5178 ew32(TARC(0), tarc0);
5179 }
5180
5181
5182
5183
5184 if (!(adapter->flags & FLAG_TSO_FORCE)) {
5185 switch (adapter->link_speed) {
5186 case SPEED_10:
5187 case SPEED_100:
5188 e_info("10/100 speed: disabling TSO\n");
5189 netdev->features &= ~NETIF_F_TSO;
5190 netdev->features &= ~NETIF_F_TSO6;
5191 break;
5192 case SPEED_1000:
5193 netdev->features |= NETIF_F_TSO;
5194 netdev->features |= NETIF_F_TSO6;
5195 break;
5196 default:
5197
5198 break;
5199 }
5200 }
5201
5202
5203
5204
5205 tctl = er32(TCTL);
5206 tctl |= E1000_TCTL_EN;
5207 ew32(TCTL, tctl);
5208
5209
5210
5211
5212 if (phy->ops.cfg_on_link_up)
5213 phy->ops.cfg_on_link_up(hw);
5214
5215 netif_carrier_on(netdev);
5216
5217 if (!test_bit(__E1000_DOWN, &adapter->state))
5218 mod_timer(&adapter->phy_info_timer,
5219 round_jiffies(jiffies + 2 * HZ));
5220 }
5221 } else {
5222 if (netif_carrier_ok(netdev)) {
5223 adapter->link_speed = 0;
5224 adapter->link_duplex = 0;
5225
5226 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
5227 netif_carrier_off(netdev);
5228 if (!test_bit(__E1000_DOWN, &adapter->state))
5229 mod_timer(&adapter->phy_info_timer,
5230 round_jiffies(jiffies + 2 * HZ));
5231
5232
5233
5234
5235
5236 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5237 adapter->flags |= FLAG_RESTART_NOW;
5238 else
5239 pm_schedule_suspend(netdev->dev.parent,
5240 LINK_TIMEOUT);
5241 }
5242 }
5243
5244link_up:
5245 spin_lock(&adapter->stats64_lock);
5246 e1000e_update_stats(adapter);
5247
5248 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5249 adapter->tpt_old = adapter->stats.tpt;
5250 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5251 adapter->colc_old = adapter->stats.colc;
5252
5253 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5254 adapter->gorc_old = adapter->stats.gorc;
5255 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5256 adapter->gotc_old = adapter->stats.gotc;
5257 spin_unlock(&adapter->stats64_lock);
5258
5259
5260
5261
5262
5263 if (!netif_carrier_ok(netdev) &&
5264 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5265 adapter->flags |= FLAG_RESTART_NOW;
5266
5267
5268 if (adapter->flags & FLAG_RESTART_NOW) {
5269 schedule_work(&adapter->reset_task);
5270
5271 return;
5272 }
5273
5274 e1000e_update_adaptive(&adapter->hw);
5275
5276
5277 if (adapter->itr_setting == 4) {
5278
5279
5280
5281
5282 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5283 u32 dif = (adapter->gotc > adapter->gorc ?
5284 adapter->gotc - adapter->gorc :
5285 adapter->gorc - adapter->gotc) / 10000;
5286 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5287
5288 e1000e_write_itr(adapter, itr);
5289 }
5290
5291
5292 if (adapter->msix_entries)
5293 ew32(ICS, adapter->rx_ring->ims_val);
5294 else
5295 ew32(ICS, E1000_ICS_RXDMT0);
5296
5297
5298 e1000e_flush_descriptors(adapter);
5299
5300
5301 adapter->detect_tx_hung = true;
5302
5303
5304
5305
5306 if (e1000e_get_laa_state_82571(hw))
5307 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5308
5309 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5310 e1000e_check_82574_phy_workaround(adapter);
5311
5312
5313 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5314 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5315 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5316 er32(RXSTMPH);
5317 adapter->rx_hwtstamp_cleared++;
5318 } else {
5319 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5320 }
5321 }
5322
5323
5324 if (!test_bit(__E1000_DOWN, &adapter->state))
5325 mod_timer(&adapter->watchdog_timer,
5326 round_jiffies(jiffies + 2 * HZ));
5327}
5328
5329#define E1000_TX_FLAGS_CSUM 0x00000001
5330#define E1000_TX_FLAGS_VLAN 0x00000002
5331#define E1000_TX_FLAGS_TSO 0x00000004
5332#define E1000_TX_FLAGS_IPV4 0x00000008
5333#define E1000_TX_FLAGS_NO_FCS 0x00000010
5334#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5335#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5336#define E1000_TX_FLAGS_VLAN_SHIFT 16
5337
5338static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5339 __be16 protocol)
5340{
5341 struct e1000_context_desc *context_desc;
5342 struct e1000_buffer *buffer_info;
5343 unsigned int i;
5344 u32 cmd_length = 0;
5345 u16 ipcse = 0, mss;
5346 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5347 int err;
5348
5349 if (!skb_is_gso(skb))
5350 return 0;
5351
5352 err = skb_cow_head(skb, 0);
5353 if (err < 0)
5354 return err;
5355
5356 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5357 mss = skb_shinfo(skb)->gso_size;
5358 if (protocol == htons(ETH_P_IP)) {
5359 struct iphdr *iph = ip_hdr(skb);
5360 iph->tot_len = 0;
5361 iph->check = 0;
5362 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5363 0, IPPROTO_TCP, 0);
5364 cmd_length = E1000_TXD_CMD_IP;
5365 ipcse = skb_transport_offset(skb) - 1;
5366 } else if (skb_is_gso_v6(skb)) {
5367 ipv6_hdr(skb)->payload_len = 0;
5368 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5369 &ipv6_hdr(skb)->daddr,
5370 0, IPPROTO_TCP, 0);
5371 ipcse = 0;
5372 }
5373 ipcss = skb_network_offset(skb);
5374 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5375 tucss = skb_transport_offset(skb);
5376 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5377
5378 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5379 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5380
5381 i = tx_ring->next_to_use;
5382 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5383 buffer_info = &tx_ring->buffer_info[i];
5384
5385 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5386 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5387 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5388 context_desc->upper_setup.tcp_fields.tucss = tucss;
5389 context_desc->upper_setup.tcp_fields.tucso = tucso;
5390 context_desc->upper_setup.tcp_fields.tucse = 0;
5391 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5392 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5393 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5394
5395 buffer_info->time_stamp = jiffies;
5396 buffer_info->next_to_watch = i;
5397
5398 i++;
5399 if (i == tx_ring->count)
5400 i = 0;
5401 tx_ring->next_to_use = i;
5402
5403 return 1;
5404}
5405
5406static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5407 __be16 protocol)
5408{
5409 struct e1000_adapter *adapter = tx_ring->adapter;
5410 struct e1000_context_desc *context_desc;
5411 struct e1000_buffer *buffer_info;
5412 unsigned int i;
5413 u8 css;
5414 u32 cmd_len = E1000_TXD_CMD_DEXT;
5415
5416 if (skb->ip_summed != CHECKSUM_PARTIAL)
5417 return false;
5418
5419 switch (protocol) {
5420 case cpu_to_be16(ETH_P_IP):
5421 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5422 cmd_len |= E1000_TXD_CMD_TCP;
5423 break;
5424 case cpu_to_be16(ETH_P_IPV6):
5425
5426 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5427 cmd_len |= E1000_TXD_CMD_TCP;
5428 break;
5429 default:
5430 if (unlikely(net_ratelimit()))
5431 e_warn("checksum_partial proto=%x!\n",
5432 be16_to_cpu(protocol));
5433 break;
5434 }
5435
5436 css = skb_checksum_start_offset(skb);
5437
5438 i = tx_ring->next_to_use;
5439 buffer_info = &tx_ring->buffer_info[i];
5440 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5441
5442 context_desc->lower_setup.ip_config = 0;
5443 context_desc->upper_setup.tcp_fields.tucss = css;
5444 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5445 context_desc->upper_setup.tcp_fields.tucse = 0;
5446 context_desc->tcp_seg_setup.data = 0;
5447 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5448
5449 buffer_info->time_stamp = jiffies;
5450 buffer_info->next_to_watch = i;
5451
5452 i++;
5453 if (i == tx_ring->count)
5454 i = 0;
5455 tx_ring->next_to_use = i;
5456
5457 return true;
5458}
5459
5460static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5461 unsigned int first, unsigned int max_per_txd,
5462 unsigned int nr_frags)
5463{
5464 struct e1000_adapter *adapter = tx_ring->adapter;
5465 struct pci_dev *pdev = adapter->pdev;
5466 struct e1000_buffer *buffer_info;
5467 unsigned int len = skb_headlen(skb);
5468 unsigned int offset = 0, size, count = 0, i;
5469 unsigned int f, bytecount, segs;
5470
5471 i = tx_ring->next_to_use;
5472
5473 while (len) {
5474 buffer_info = &tx_ring->buffer_info[i];
5475 size = min(len, max_per_txd);
5476
5477 buffer_info->length = size;
5478 buffer_info->time_stamp = jiffies;
5479 buffer_info->next_to_watch = i;
5480 buffer_info->dma = dma_map_single(&pdev->dev,
5481 skb->data + offset,
5482 size, DMA_TO_DEVICE);
5483 buffer_info->mapped_as_page = false;
5484 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5485 goto dma_error;
5486
5487 len -= size;
5488 offset += size;
5489 count++;
5490
5491 if (len) {
5492 i++;
5493 if (i == tx_ring->count)
5494 i = 0;
5495 }
5496 }
5497
5498 for (f = 0; f < nr_frags; f++) {
5499 const struct skb_frag_struct *frag;
5500
5501 frag = &skb_shinfo(skb)->frags[f];
5502 len = skb_frag_size(frag);
5503 offset = 0;
5504
5505 while (len) {
5506 i++;
5507 if (i == tx_ring->count)
5508 i = 0;
5509
5510 buffer_info = &tx_ring->buffer_info[i];
5511 size = min(len, max_per_txd);
5512
5513 buffer_info->length = size;
5514 buffer_info->time_stamp = jiffies;
5515 buffer_info->next_to_watch = i;
5516 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5517 offset, size,
5518 DMA_TO_DEVICE);
5519 buffer_info->mapped_as_page = true;
5520 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5521 goto dma_error;
5522
5523 len -= size;
5524 offset += size;
5525 count++;
5526 }
5527 }
5528
5529 segs = skb_shinfo(skb)->gso_segs ? : 1;
5530
5531 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5532
5533 tx_ring->buffer_info[i].skb = skb;
5534 tx_ring->buffer_info[i].segs = segs;
5535 tx_ring->buffer_info[i].bytecount = bytecount;
5536 tx_ring->buffer_info[first].next_to_watch = i;
5537
5538 return count;
5539
5540dma_error:
5541 dev_err(&pdev->dev, "Tx DMA map failed\n");
5542 buffer_info->dma = 0;
5543 if (count)
5544 count--;
5545
5546 while (count--) {
5547 if (i == 0)
5548 i += tx_ring->count;
5549 i--;
5550 buffer_info = &tx_ring->buffer_info[i];
5551 e1000_put_txbuf(tx_ring, buffer_info);
5552 }
5553
5554 return 0;
5555}
5556
5557static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5558{
5559 struct e1000_adapter *adapter = tx_ring->adapter;
5560 struct e1000_tx_desc *tx_desc = NULL;
5561 struct e1000_buffer *buffer_info;
5562 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5563 unsigned int i;
5564
5565 if (tx_flags & E1000_TX_FLAGS_TSO) {
5566 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5567 E1000_TXD_CMD_TSE;
5568 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5569
5570 if (tx_flags & E1000_TX_FLAGS_IPV4)
5571 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5572 }
5573
5574 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5575 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5576 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5577 }
5578
5579 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5580 txd_lower |= E1000_TXD_CMD_VLE;
5581 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5582 }
5583
5584 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5585 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5586
5587 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5588 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5589 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5590 }
5591
5592 i = tx_ring->next_to_use;
5593
5594 do {
5595 buffer_info = &tx_ring->buffer_info[i];
5596 tx_desc = E1000_TX_DESC(*tx_ring, i);
5597 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5598 tx_desc->lower.data = cpu_to_le32(txd_lower |
5599 buffer_info->length);
5600 tx_desc->upper.data = cpu_to_le32(txd_upper);
5601
5602 i++;
5603 if (i == tx_ring->count)
5604 i = 0;
5605 } while (--count > 0);
5606
5607 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5608
5609
5610 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5611 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5612
5613
5614
5615
5616
5617
5618 wmb();
5619
5620 tx_ring->next_to_use = i;
5621}
5622
5623#define MINIMUM_DHCP_PACKET_SIZE 282
5624static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5625 struct sk_buff *skb)
5626{
5627 struct e1000_hw *hw = &adapter->hw;
5628 u16 length, offset;
5629
5630 if (skb_vlan_tag_present(skb) &&
5631 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5632 (adapter->hw.mng_cookie.status &
5633 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5634 return 0;
5635
5636 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5637 return 0;
5638
5639 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5640 return 0;
5641
5642 {
5643 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5644 struct udphdr *udp;
5645
5646 if (ip->protocol != IPPROTO_UDP)
5647 return 0;
5648
5649 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5650 if (ntohs(udp->dest) != 67)
5651 return 0;
5652
5653 offset = (u8 *)udp + 8 - skb->data;
5654 length = skb->len - offset;
5655 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5656 }
5657
5658 return 0;
5659}
5660
5661static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5662{
5663 struct e1000_adapter *adapter = tx_ring->adapter;
5664
5665 netif_stop_queue(adapter->netdev);
5666
5667
5668
5669
5670 smp_mb();
5671
5672
5673
5674
5675 if (e1000_desc_unused(tx_ring) < size)
5676 return -EBUSY;
5677
5678
5679 netif_start_queue(adapter->netdev);
5680 ++adapter->restart_queue;
5681 return 0;
5682}
5683
5684static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5685{
5686 BUG_ON(size > tx_ring->count);
5687
5688 if (e1000_desc_unused(tx_ring) >= size)
5689 return 0;
5690 return __e1000_maybe_stop_tx(tx_ring, size);
5691}
5692
5693static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5694 struct net_device *netdev)
5695{
5696 struct e1000_adapter *adapter = netdev_priv(netdev);
5697 struct e1000_ring *tx_ring = adapter->tx_ring;
5698 unsigned int first;
5699 unsigned int tx_flags = 0;
5700 unsigned int len = skb_headlen(skb);
5701 unsigned int nr_frags;
5702 unsigned int mss;
5703 int count = 0;
5704 int tso;
5705 unsigned int f;
5706 __be16 protocol = vlan_get_protocol(skb);
5707
5708 if (test_bit(__E1000_DOWN, &adapter->state)) {
5709 dev_kfree_skb_any(skb);
5710 return NETDEV_TX_OK;
5711 }
5712
5713 if (skb->len <= 0) {
5714 dev_kfree_skb_any(skb);
5715 return NETDEV_TX_OK;
5716 }
5717
5718
5719
5720
5721 if (skb_put_padto(skb, 17))
5722 return NETDEV_TX_OK;
5723
5724 mss = skb_shinfo(skb)->gso_size;
5725 if (mss) {
5726 u8 hdr_len;
5727
5728
5729
5730
5731
5732 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5733
5734
5735
5736 if (skb->data_len && (hdr_len == len)) {
5737 unsigned int pull_size;
5738
5739 pull_size = min_t(unsigned int, 4, skb->data_len);
5740 if (!__pskb_pull_tail(skb, pull_size)) {
5741 e_err("__pskb_pull_tail failed.\n");
5742 dev_kfree_skb_any(skb);
5743 return NETDEV_TX_OK;
5744 }
5745 len = skb_headlen(skb);
5746 }
5747 }
5748
5749
5750 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5751 count++;
5752 count++;
5753
5754 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5755
5756 nr_frags = skb_shinfo(skb)->nr_frags;
5757 for (f = 0; f < nr_frags; f++)
5758 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5759 adapter->tx_fifo_limit);
5760
5761 if (adapter->hw.mac.tx_pkt_filtering)
5762 e1000_transfer_dhcp_info(adapter, skb);
5763
5764
5765
5766
5767 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5768 return NETDEV_TX_BUSY;
5769
5770 if (skb_vlan_tag_present(skb)) {
5771 tx_flags |= E1000_TX_FLAGS_VLAN;
5772 tx_flags |= (skb_vlan_tag_get(skb) <<
5773 E1000_TX_FLAGS_VLAN_SHIFT);
5774 }
5775
5776 first = tx_ring->next_to_use;
5777
5778 tso = e1000_tso(tx_ring, skb, protocol);
5779 if (tso < 0) {
5780 dev_kfree_skb_any(skb);
5781 return NETDEV_TX_OK;
5782 }
5783
5784 if (tso)
5785 tx_flags |= E1000_TX_FLAGS_TSO;
5786 else if (e1000_tx_csum(tx_ring, skb, protocol))
5787 tx_flags |= E1000_TX_FLAGS_CSUM;
5788
5789
5790
5791
5792
5793 if (protocol == htons(ETH_P_IP))
5794 tx_flags |= E1000_TX_FLAGS_IPV4;
5795
5796 if (unlikely(skb->no_fcs))
5797 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5798
5799
5800 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5801 nr_frags);
5802 if (count) {
5803 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5804 (adapter->flags & FLAG_HAS_HW_TIMESTAMP) &&
5805 !adapter->tx_hwtstamp_skb) {
5806 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5807 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5808 adapter->tx_hwtstamp_skb = skb_get(skb);
5809 adapter->tx_hwtstamp_start = jiffies;
5810 schedule_work(&adapter->tx_hwtstamp_work);
5811 } else {
5812 skb_tx_timestamp(skb);
5813 }
5814
5815 netdev_sent_queue(netdev, skb->len);
5816 e1000_tx_queue(tx_ring, tx_flags, count);
5817
5818 e1000_maybe_stop_tx(tx_ring,
5819 (MAX_SKB_FRAGS *
5820 DIV_ROUND_UP(PAGE_SIZE,
5821 adapter->tx_fifo_limit) + 2));
5822
5823 if (!skb->xmit_more ||
5824 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5825 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5826 e1000e_update_tdt_wa(tx_ring,
5827 tx_ring->next_to_use);
5828 else
5829 writel(tx_ring->next_to_use, tx_ring->tail);
5830
5831
5832
5833
5834
5835 mmiowb();
5836 }
5837 } else {
5838 dev_kfree_skb_any(skb);
5839 tx_ring->buffer_info[first].time_stamp = 0;
5840 tx_ring->next_to_use = first;
5841 }
5842
5843 return NETDEV_TX_OK;
5844}
5845
5846
5847
5848
5849
5850static void e1000_tx_timeout(struct net_device *netdev)
5851{
5852 struct e1000_adapter *adapter = netdev_priv(netdev);
5853
5854
5855 adapter->tx_timeout_count++;
5856 schedule_work(&adapter->reset_task);
5857}
5858
5859static void e1000_reset_task(struct work_struct *work)
5860{
5861 struct e1000_adapter *adapter;
5862 adapter = container_of(work, struct e1000_adapter, reset_task);
5863
5864
5865 if (test_bit(__E1000_DOWN, &adapter->state))
5866 return;
5867
5868 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5869 e1000e_dump(adapter);
5870 e_err("Reset adapter unexpectedly\n");
5871 }
5872 e1000e_reinit_locked(adapter);
5873}
5874
5875
5876
5877
5878
5879
5880
5881
5882struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5883 struct rtnl_link_stats64 *stats)
5884{
5885 struct e1000_adapter *adapter = netdev_priv(netdev);
5886
5887 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5888 spin_lock(&adapter->stats64_lock);
5889 e1000e_update_stats(adapter);
5890
5891 stats->rx_bytes = adapter->stats.gorc;
5892 stats->rx_packets = adapter->stats.gprc;
5893 stats->tx_bytes = adapter->stats.gotc;
5894 stats->tx_packets = adapter->stats.gptc;
5895 stats->multicast = adapter->stats.mprc;
5896 stats->collisions = adapter->stats.colc;
5897
5898
5899
5900
5901
5902
5903 stats->rx_errors = adapter->stats.rxerrc +
5904 adapter->stats.crcerrs + adapter->stats.algnerrc +
5905 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5906 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
5907 stats->rx_crc_errors = adapter->stats.crcerrs;
5908 stats->rx_frame_errors = adapter->stats.algnerrc;
5909 stats->rx_missed_errors = adapter->stats.mpc;
5910
5911
5912 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5913 stats->tx_aborted_errors = adapter->stats.ecol;
5914 stats->tx_window_errors = adapter->stats.latecol;
5915 stats->tx_carrier_errors = adapter->stats.tncrs;
5916
5917
5918
5919 spin_unlock(&adapter->stats64_lock);
5920 return stats;
5921}
5922
5923
5924
5925
5926
5927
5928
5929
5930static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5931{
5932 struct e1000_adapter *adapter = netdev_priv(netdev);
5933 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
5934
5935
5936 if ((max_frame > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) &&
5937 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5938 e_err("Jumbo Frames not supported.\n");
5939 return -EINVAL;
5940 }
5941
5942
5943 if ((new_mtu < (VLAN_ETH_ZLEN + ETH_FCS_LEN)) ||
5944 (max_frame > adapter->max_hw_frame_size)) {
5945 e_err("Unsupported MTU setting\n");
5946 return -EINVAL;
5947 }
5948
5949
5950 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
5951 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5952 (new_mtu > ETH_DATA_LEN)) {
5953 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
5954 return -EINVAL;
5955 }
5956
5957 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
5958 usleep_range(1000, 2000);
5959
5960 adapter->max_frame_size = max_frame;
5961 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5962 netdev->mtu = new_mtu;
5963
5964 pm_runtime_get_sync(netdev->dev.parent);
5965
5966 if (netif_running(netdev))
5967 e1000e_down(adapter, true);
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977 if (max_frame <= 2048)
5978 adapter->rx_buffer_len = 2048;
5979 else
5980 adapter->rx_buffer_len = 4096;
5981
5982
5983 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
5984 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
5985
5986 if (netif_running(netdev))
5987 e1000e_up(adapter);
5988 else
5989 e1000e_reset(adapter);
5990
5991 pm_runtime_put_sync(netdev->dev.parent);
5992
5993 clear_bit(__E1000_RESETTING, &adapter->state);
5994
5995 return 0;
5996}
5997
5998static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5999 int cmd)
6000{
6001 struct e1000_adapter *adapter = netdev_priv(netdev);
6002 struct mii_ioctl_data *data = if_mii(ifr);
6003
6004 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6005 return -EOPNOTSUPP;
6006
6007 switch (cmd) {
6008 case SIOCGMIIPHY:
6009 data->phy_id = adapter->hw.phy.addr;
6010 break;
6011 case SIOCGMIIREG:
6012 e1000_phy_read_status(adapter);
6013
6014 switch (data->reg_num & 0x1F) {
6015 case MII_BMCR:
6016 data->val_out = adapter->phy_regs.bmcr;
6017 break;
6018 case MII_BMSR:
6019 data->val_out = adapter->phy_regs.bmsr;
6020 break;
6021 case MII_PHYSID1:
6022 data->val_out = (adapter->hw.phy.id >> 16);
6023 break;
6024 case MII_PHYSID2:
6025 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6026 break;
6027 case MII_ADVERTISE:
6028 data->val_out = adapter->phy_regs.advertise;
6029 break;
6030 case MII_LPA:
6031 data->val_out = adapter->phy_regs.lpa;
6032 break;
6033 case MII_EXPANSION:
6034 data->val_out = adapter->phy_regs.expansion;
6035 break;
6036 case MII_CTRL1000:
6037 data->val_out = adapter->phy_regs.ctrl1000;
6038 break;
6039 case MII_STAT1000:
6040 data->val_out = adapter->phy_regs.stat1000;
6041 break;
6042 case MII_ESTATUS:
6043 data->val_out = adapter->phy_regs.estatus;
6044 break;
6045 default:
6046 return -EIO;
6047 }
6048 break;
6049 case SIOCSMIIREG:
6050 default:
6051 return -EOPNOTSUPP;
6052 }
6053 return 0;
6054}
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6073{
6074 struct e1000_adapter *adapter = netdev_priv(netdev);
6075 struct hwtstamp_config config;
6076 int ret_val;
6077
6078 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6079 return -EFAULT;
6080
6081 ret_val = e1000e_config_hwtstamp(adapter, &config);
6082 if (ret_val)
6083 return ret_val;
6084
6085 switch (config.rx_filter) {
6086 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6087 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6088 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6089 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6090 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6091 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6092
6093
6094
6095
6096
6097 config.rx_filter = HWTSTAMP_FILTER_SOME;
6098 break;
6099 default:
6100 break;
6101 }
6102
6103 return copy_to_user(ifr->ifr_data, &config,
6104 sizeof(config)) ? -EFAULT : 0;
6105}
6106
6107static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6108{
6109 struct e1000_adapter *adapter = netdev_priv(netdev);
6110
6111 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6112 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6113}
6114
6115static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6116{
6117 switch (cmd) {
6118 case SIOCGMIIPHY:
6119 case SIOCGMIIREG:
6120 case SIOCSMIIREG:
6121 return e1000_mii_ioctl(netdev, ifr, cmd);
6122 case SIOCSHWTSTAMP:
6123 return e1000e_hwtstamp_set(netdev, ifr);
6124 case SIOCGHWTSTAMP:
6125 return e1000e_hwtstamp_get(netdev, ifr);
6126 default:
6127 return -EOPNOTSUPP;
6128 }
6129}
6130
6131static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6132{
6133 struct e1000_hw *hw = &adapter->hw;
6134 u32 i, mac_reg, wuc;
6135 u16 phy_reg, wuc_enable;
6136 int retval;
6137
6138
6139 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6140
6141 retval = hw->phy.ops.acquire(hw);
6142 if (retval) {
6143 e_err("Could not acquire PHY\n");
6144 return retval;
6145 }
6146
6147
6148 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6149 if (retval)
6150 goto release;
6151
6152
6153 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6154 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6155 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6156 (u16)(mac_reg & 0xFFFF));
6157 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6158 (u16)((mac_reg >> 16) & 0xFFFF));
6159 }
6160
6161
6162 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6163 mac_reg = er32(RCTL);
6164 if (mac_reg & E1000_RCTL_UPE)
6165 phy_reg |= BM_RCTL_UPE;
6166 if (mac_reg & E1000_RCTL_MPE)
6167 phy_reg |= BM_RCTL_MPE;
6168 phy_reg &= ~(BM_RCTL_MO_MASK);
6169 if (mac_reg & E1000_RCTL_MO_3)
6170 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
6171 << BM_RCTL_MO_SHIFT);
6172 if (mac_reg & E1000_RCTL_BAM)
6173 phy_reg |= BM_RCTL_BAM;
6174 if (mac_reg & E1000_RCTL_PMCF)
6175 phy_reg |= BM_RCTL_PMCF;
6176 mac_reg = er32(CTRL);
6177 if (mac_reg & E1000_CTRL_RFCE)
6178 phy_reg |= BM_RCTL_RFCE;
6179 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6180
6181 wuc = E1000_WUC_PME_EN;
6182 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6183 wuc |= E1000_WUC_APME;
6184
6185
6186 ew32(WUFC, wufc);
6187 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6188 E1000_WUC_PME_STATUS | wuc));
6189
6190
6191 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6192 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6193
6194
6195 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6196 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6197 if (retval)
6198 e_err("Could not set PHY Host Wakeup bit\n");
6199release:
6200 hw->phy.ops.release(hw);
6201
6202 return retval;
6203}
6204
6205static void e1000e_flush_lpic(struct pci_dev *pdev)
6206{
6207 struct net_device *netdev = pci_get_drvdata(pdev);
6208 struct e1000_adapter *adapter = netdev_priv(netdev);
6209 struct e1000_hw *hw = &adapter->hw;
6210 u32 ret_val;
6211
6212 pm_runtime_get_sync(netdev->dev.parent);
6213
6214 ret_val = hw->phy.ops.acquire(hw);
6215 if (ret_val)
6216 goto fl_out;
6217
6218 pr_info("EEE TX LPI TIMER: %08X\n",
6219 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6220
6221 hw->phy.ops.release(hw);
6222
6223fl_out:
6224 pm_runtime_put_sync(netdev->dev.parent);
6225}
6226
6227static int e1000e_pm_freeze(struct device *dev)
6228{
6229 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6230 struct e1000_adapter *adapter = netdev_priv(netdev);
6231
6232 netif_device_detach(netdev);
6233
6234 if (netif_running(netdev)) {
6235 int count = E1000_CHECK_RESET_COUNT;
6236
6237 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6238 usleep_range(10000, 20000);
6239
6240 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6241
6242
6243 e1000e_down(adapter, false);
6244 e1000_free_irq(adapter);
6245 }
6246 e1000e_reset_interrupt_capability(adapter);
6247
6248
6249 e1000e_disable_pcie_master(&adapter->hw);
6250
6251 return 0;
6252}
6253
6254static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6255{
6256 struct net_device *netdev = pci_get_drvdata(pdev);
6257 struct e1000_adapter *adapter = netdev_priv(netdev);
6258 struct e1000_hw *hw = &adapter->hw;
6259 u32 ctrl, ctrl_ext, rctl, status;
6260
6261 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6262 int retval = 0;
6263
6264 status = er32(STATUS);
6265 if (status & E1000_STATUS_LU)
6266 wufc &= ~E1000_WUFC_LNKC;
6267
6268 if (wufc) {
6269 e1000_setup_rctl(adapter);
6270 e1000e_set_rx_mode(netdev);
6271
6272
6273 if (wufc & E1000_WUFC_MC) {
6274 rctl = er32(RCTL);
6275 rctl |= E1000_RCTL_MPE;
6276 ew32(RCTL, rctl);
6277 }
6278
6279 ctrl = er32(CTRL);
6280 ctrl |= E1000_CTRL_ADVD3WUC;
6281 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6282 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6283 ew32(CTRL, ctrl);
6284
6285 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6286 adapter->hw.phy.media_type ==
6287 e1000_media_type_internal_serdes) {
6288
6289 ctrl_ext = er32(CTRL_EXT);
6290 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6291 ew32(CTRL_EXT, ctrl_ext);
6292 }
6293
6294 if (!runtime)
6295 e1000e_power_up_phy(adapter);
6296
6297 if (adapter->flags & FLAG_IS_ICH)
6298 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6299
6300 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6301
6302 retval = e1000_init_phy_wakeup(adapter, wufc);
6303 if (retval)
6304 return retval;
6305 } else {
6306
6307 ew32(WUFC, wufc);
6308 ew32(WUC, E1000_WUC_PME_EN);
6309 }
6310 } else {
6311 ew32(WUC, 0);
6312 ew32(WUFC, 0);
6313
6314 e1000_power_down_phy(adapter);
6315 }
6316
6317 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6318 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6319 } else if ((hw->mac.type == e1000_pch_lpt) ||
6320 (hw->mac.type == e1000_pch_spt)) {
6321 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6322
6323
6324
6325 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6326
6327 if (retval)
6328 return retval;
6329 }
6330
6331
6332
6333
6334 if ((hw->phy.type >= e1000_phy_i217) &&
6335 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6336 u16 lpi_ctrl = 0;
6337
6338 retval = hw->phy.ops.acquire(hw);
6339 if (!retval) {
6340 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6341 &lpi_ctrl);
6342 if (!retval) {
6343 if (adapter->eee_advert &
6344 hw->dev_spec.ich8lan.eee_lp_ability &
6345 I82579_EEE_100_SUPPORTED)
6346 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6347 if (adapter->eee_advert &
6348 hw->dev_spec.ich8lan.eee_lp_ability &
6349 I82579_EEE_1000_SUPPORTED)
6350 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6351
6352 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6353 lpi_ctrl);
6354 }
6355 }
6356 hw->phy.ops.release(hw);
6357 }
6358
6359
6360
6361
6362 e1000e_release_hw_control(adapter);
6363
6364 pci_clear_master(pdev);
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6376 struct pci_dev *us_dev = pdev->bus->self;
6377 u16 devctl;
6378
6379 if (!us_dev)
6380 return 0;
6381
6382 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6383 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6384 (devctl & ~PCI_EXP_DEVCTL_CERE));
6385
6386 pci_save_state(pdev);
6387 pci_prepare_to_sleep(pdev);
6388
6389 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6390 }
6391
6392 return 0;
6393}
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6404{
6405 struct pci_dev *parent = pdev->bus->self;
6406 u16 aspm_dis_mask = 0;
6407 u16 pdev_aspmc, parent_aspmc;
6408
6409 switch (state) {
6410 case PCIE_LINK_STATE_L0S:
6411 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6412 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6413
6414 case PCIE_LINK_STATE_L1:
6415 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6416 break;
6417 default:
6418 return;
6419 }
6420
6421 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6422 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6423
6424 if (parent) {
6425 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6426 &parent_aspmc);
6427 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6428 }
6429
6430
6431 if (!(pdev_aspmc & aspm_dis_mask) &&
6432 (!parent || !(parent_aspmc & aspm_dis_mask)))
6433 return;
6434
6435 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6436 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6437 "L0s" : "",
6438 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6439 "L1" : "");
6440
6441#ifdef CONFIG_PCIEASPM
6442 if (locked)
6443 pci_disable_link_state_locked(pdev, state);
6444 else
6445 pci_disable_link_state(pdev, state);
6446
6447
6448
6449
6450
6451 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6452 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6453
6454 if (!(aspm_dis_mask & pdev_aspmc))
6455 return;
6456#endif
6457
6458
6459
6460
6461 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6462
6463 if (parent)
6464 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6465 aspm_dis_mask);
6466}
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6477{
6478 __e1000e_disable_aspm(pdev, state, 0);
6479}
6480
6481
6482
6483
6484
6485
6486
6487
6488
6489static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6490{
6491 __e1000e_disable_aspm(pdev, state, 1);
6492}
6493
6494#ifdef CONFIG_PM
6495static int __e1000_resume(struct pci_dev *pdev)
6496{
6497 struct net_device *netdev = pci_get_drvdata(pdev);
6498 struct e1000_adapter *adapter = netdev_priv(netdev);
6499 struct e1000_hw *hw = &adapter->hw;
6500 u16 aspm_disable_flag = 0;
6501
6502 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6503 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6504 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6505 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6506 if (aspm_disable_flag)
6507 e1000e_disable_aspm(pdev, aspm_disable_flag);
6508
6509 pci_set_master(pdev);
6510
6511 if (hw->mac.type >= e1000_pch2lan)
6512 e1000_resume_workarounds_pchlan(&adapter->hw);
6513
6514 e1000e_power_up_phy(adapter);
6515
6516
6517 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6518 u16 phy_data;
6519
6520 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6521 if (phy_data) {
6522 e_info("PHY Wakeup cause - %s\n",
6523 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6524 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6525 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6526 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6527 phy_data & E1000_WUS_LNKC ?
6528 "Link Status Change" : "other");
6529 }
6530 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6531 } else {
6532 u32 wus = er32(WUS);
6533
6534 if (wus) {
6535 e_info("MAC Wakeup cause - %s\n",
6536 wus & E1000_WUS_EX ? "Unicast Packet" :
6537 wus & E1000_WUS_MC ? "Multicast Packet" :
6538 wus & E1000_WUS_BC ? "Broadcast Packet" :
6539 wus & E1000_WUS_MAG ? "Magic Packet" :
6540 wus & E1000_WUS_LNKC ? "Link Status Change" :
6541 "other");
6542 }
6543 ew32(WUS, ~0);
6544 }
6545
6546 e1000e_reset(adapter);
6547
6548 e1000_init_manageability_pt(adapter);
6549
6550
6551
6552
6553
6554 if (!(adapter->flags & FLAG_HAS_AMT))
6555 e1000e_get_hw_control(adapter);
6556
6557 return 0;
6558}
6559
6560#ifdef CONFIG_PM_SLEEP
6561static int e1000e_pm_thaw(struct device *dev)
6562{
6563 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6564 struct e1000_adapter *adapter = netdev_priv(netdev);
6565
6566 e1000e_set_interrupt_capability(adapter);
6567 if (netif_running(netdev)) {
6568 u32 err = e1000_request_irq(adapter);
6569
6570 if (err)
6571 return err;
6572
6573 e1000e_up(adapter);
6574 }
6575
6576 netif_device_attach(netdev);
6577
6578 return 0;
6579}
6580
6581static int e1000e_pm_suspend(struct device *dev)
6582{
6583 struct pci_dev *pdev = to_pci_dev(dev);
6584
6585 e1000e_flush_lpic(pdev);
6586
6587 e1000e_pm_freeze(dev);
6588
6589 return __e1000_shutdown(pdev, false);
6590}
6591
6592static int e1000e_pm_resume(struct device *dev)
6593{
6594 struct pci_dev *pdev = to_pci_dev(dev);
6595 int rc;
6596
6597 rc = __e1000_resume(pdev);
6598 if (rc)
6599 return rc;
6600
6601 return e1000e_pm_thaw(dev);
6602}
6603#endif
6604
6605static int e1000e_pm_runtime_idle(struct device *dev)
6606{
6607 struct pci_dev *pdev = to_pci_dev(dev);
6608 struct net_device *netdev = pci_get_drvdata(pdev);
6609 struct e1000_adapter *adapter = netdev_priv(netdev);
6610 u16 eee_lp;
6611
6612 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
6613
6614 if (!e1000e_has_link(adapter)) {
6615 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
6616 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
6617 }
6618
6619 return -EBUSY;
6620}
6621
6622static int e1000e_pm_runtime_resume(struct device *dev)
6623{
6624 struct pci_dev *pdev = to_pci_dev(dev);
6625 struct net_device *netdev = pci_get_drvdata(pdev);
6626 struct e1000_adapter *adapter = netdev_priv(netdev);
6627 int rc;
6628
6629 rc = __e1000_resume(pdev);
6630 if (rc)
6631 return rc;
6632
6633 if (netdev->flags & IFF_UP)
6634 rc = e1000e_up(adapter);
6635
6636 return rc;
6637}
6638
6639static int e1000e_pm_runtime_suspend(struct device *dev)
6640{
6641 struct pci_dev *pdev = to_pci_dev(dev);
6642 struct net_device *netdev = pci_get_drvdata(pdev);
6643 struct e1000_adapter *adapter = netdev_priv(netdev);
6644
6645 if (netdev->flags & IFF_UP) {
6646 int count = E1000_CHECK_RESET_COUNT;
6647
6648 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6649 usleep_range(10000, 20000);
6650
6651 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6652
6653
6654 e1000e_down(adapter, false);
6655 }
6656
6657 if (__e1000_shutdown(pdev, true)) {
6658 e1000e_pm_runtime_resume(dev);
6659 return -EBUSY;
6660 }
6661
6662 return 0;
6663}
6664#endif
6665
6666static void e1000_shutdown(struct pci_dev *pdev)
6667{
6668 e1000e_flush_lpic(pdev);
6669
6670 e1000e_pm_freeze(&pdev->dev);
6671
6672 __e1000_shutdown(pdev, false);
6673}
6674
6675#ifdef CONFIG_NET_POLL_CONTROLLER
6676
6677static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
6678{
6679 struct net_device *netdev = data;
6680 struct e1000_adapter *adapter = netdev_priv(netdev);
6681
6682 if (adapter->msix_entries) {
6683 int vector, msix_irq;
6684
6685 vector = 0;
6686 msix_irq = adapter->msix_entries[vector].vector;
6687 disable_irq(msix_irq);
6688 e1000_intr_msix_rx(msix_irq, netdev);
6689 enable_irq(msix_irq);
6690
6691 vector++;
6692 msix_irq = adapter->msix_entries[vector].vector;
6693 disable_irq(msix_irq);
6694 e1000_intr_msix_tx(msix_irq, netdev);
6695 enable_irq(msix_irq);
6696
6697 vector++;
6698 msix_irq = adapter->msix_entries[vector].vector;
6699 disable_irq(msix_irq);
6700 e1000_msix_other(msix_irq, netdev);
6701 enable_irq(msix_irq);
6702 }
6703
6704 return IRQ_HANDLED;
6705}
6706
6707
6708
6709
6710
6711
6712
6713
6714
6715static void e1000_netpoll(struct net_device *netdev)
6716{
6717 struct e1000_adapter *adapter = netdev_priv(netdev);
6718
6719 switch (adapter->int_mode) {
6720 case E1000E_INT_MODE_MSIX:
6721 e1000_intr_msix(adapter->pdev->irq, netdev);
6722 break;
6723 case E1000E_INT_MODE_MSI:
6724 disable_irq(adapter->pdev->irq);
6725 e1000_intr_msi(adapter->pdev->irq, netdev);
6726 enable_irq(adapter->pdev->irq);
6727 break;
6728 default:
6729 disable_irq(adapter->pdev->irq);
6730 e1000_intr(adapter->pdev->irq, netdev);
6731 enable_irq(adapter->pdev->irq);
6732 break;
6733 }
6734}
6735#endif
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6746 pci_channel_state_t state)
6747{
6748 struct net_device *netdev = pci_get_drvdata(pdev);
6749 struct e1000_adapter *adapter = netdev_priv(netdev);
6750
6751 netif_device_detach(netdev);
6752
6753 if (state == pci_channel_io_perm_failure)
6754 return PCI_ERS_RESULT_DISCONNECT;
6755
6756 if (netif_running(netdev))
6757 e1000e_down(adapter, true);
6758 pci_disable_device(pdev);
6759
6760
6761 return PCI_ERS_RESULT_NEED_RESET;
6762}
6763
6764
6765
6766
6767
6768
6769
6770
6771static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6772{
6773 struct net_device *netdev = pci_get_drvdata(pdev);
6774 struct e1000_adapter *adapter = netdev_priv(netdev);
6775 struct e1000_hw *hw = &adapter->hw;
6776 u16 aspm_disable_flag = 0;
6777 int err;
6778 pci_ers_result_t result;
6779
6780 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6781 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6782 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6783 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6784 if (aspm_disable_flag)
6785 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
6786
6787 err = pci_enable_device_mem(pdev);
6788 if (err) {
6789 dev_err(&pdev->dev,
6790 "Cannot re-enable PCI device after reset.\n");
6791 result = PCI_ERS_RESULT_DISCONNECT;
6792 } else {
6793 pdev->state_saved = true;
6794 pci_restore_state(pdev);
6795 pci_set_master(pdev);
6796
6797 pci_enable_wake(pdev, PCI_D3hot, 0);
6798 pci_enable_wake(pdev, PCI_D3cold, 0);
6799
6800 e1000e_reset(adapter);
6801 ew32(WUS, ~0);
6802 result = PCI_ERS_RESULT_RECOVERED;
6803 }
6804
6805 pci_cleanup_aer_uncorrect_error_status(pdev);
6806
6807 return result;
6808}
6809
6810
6811
6812
6813
6814
6815
6816
6817
6818static void e1000_io_resume(struct pci_dev *pdev)
6819{
6820 struct net_device *netdev = pci_get_drvdata(pdev);
6821 struct e1000_adapter *adapter = netdev_priv(netdev);
6822
6823 e1000_init_manageability_pt(adapter);
6824
6825 if (netif_running(netdev)) {
6826 if (e1000e_up(adapter)) {
6827 dev_err(&pdev->dev,
6828 "can't bring device back up after reset\n");
6829 return;
6830 }
6831 }
6832
6833 netif_device_attach(netdev);
6834
6835
6836
6837
6838
6839 if (!(adapter->flags & FLAG_HAS_AMT))
6840 e1000e_get_hw_control(adapter);
6841}
6842
6843static void e1000_print_device_info(struct e1000_adapter *adapter)
6844{
6845 struct e1000_hw *hw = &adapter->hw;
6846 struct net_device *netdev = adapter->netdev;
6847 u32 ret_val;
6848 u8 pba_str[E1000_PBANUM_LENGTH];
6849
6850
6851 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
6852
6853 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
6854 "Width x1"),
6855
6856 netdev->dev_addr);
6857 e_info("Intel(R) PRO/%s Network Connection\n",
6858 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
6859 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6860 E1000_PBANUM_LENGTH);
6861 if (ret_val)
6862 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
6863 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6864 hw->mac.type, hw->phy.type, pba_str);
6865}
6866
6867static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6868{
6869 struct e1000_hw *hw = &adapter->hw;
6870 int ret_val;
6871 u16 buf = 0;
6872
6873 if (hw->mac.type != e1000_82573)
6874 return;
6875
6876 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
6877 le16_to_cpus(&buf);
6878 if (!ret_val && (!(buf & (1 << 0)))) {
6879
6880 dev_warn(&adapter->pdev->dev,
6881 "Warning: detected DSPD enabled in EEPROM\n");
6882 }
6883}
6884
6885static netdev_features_t e1000_fix_features(struct net_device *netdev,
6886 netdev_features_t features)
6887{
6888 struct e1000_adapter *adapter = netdev_priv(netdev);
6889 struct e1000_hw *hw = &adapter->hw;
6890
6891
6892 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
6893 features &= ~NETIF_F_RXFCS;
6894
6895 return features;
6896}
6897
6898static int e1000_set_features(struct net_device *netdev,
6899 netdev_features_t features)
6900{
6901 struct e1000_adapter *adapter = netdev_priv(netdev);
6902 netdev_features_t changed = features ^ netdev->features;
6903
6904 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6905 adapter->flags |= FLAG_TSO_FORCE;
6906
6907 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6908 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6909 NETIF_F_RXALL)))
6910 return 0;
6911
6912 if (changed & NETIF_F_RXFCS) {
6913 if (features & NETIF_F_RXFCS) {
6914 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6915 } else {
6916
6917
6918
6919 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6920 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6921 else
6922 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6923 }
6924 }
6925
6926 netdev->features = features;
6927
6928 if (netif_running(netdev))
6929 e1000e_reinit_locked(adapter);
6930 else
6931 e1000e_reset(adapter);
6932
6933 return 0;
6934}
6935
6936static const struct net_device_ops e1000e_netdev_ops = {
6937 .ndo_open = e1000_open,
6938 .ndo_stop = e1000_close,
6939 .ndo_start_xmit = e1000_xmit_frame,
6940 .ndo_get_stats64 = e1000e_get_stats64,
6941 .ndo_set_rx_mode = e1000e_set_rx_mode,
6942 .ndo_set_mac_address = e1000_set_mac,
6943 .ndo_change_mtu = e1000_change_mtu,
6944 .ndo_do_ioctl = e1000_ioctl,
6945 .ndo_tx_timeout = e1000_tx_timeout,
6946 .ndo_validate_addr = eth_validate_addr,
6947
6948 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6949 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6950#ifdef CONFIG_NET_POLL_CONTROLLER
6951 .ndo_poll_controller = e1000_netpoll,
6952#endif
6953 .ndo_set_features = e1000_set_features,
6954 .ndo_fix_features = e1000_fix_features,
6955};
6956
6957
6958
6959
6960
6961
6962
6963
6964
6965
6966
6967
6968static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
6969{
6970 struct net_device *netdev;
6971 struct e1000_adapter *adapter;
6972 struct e1000_hw *hw;
6973 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
6974 resource_size_t mmio_start, mmio_len;
6975 resource_size_t flash_start, flash_len;
6976 static int cards_found;
6977 u16 aspm_disable_flag = 0;
6978 int bars, i, err, pci_using_dac;
6979 u16 eeprom_data = 0;
6980 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6981 s32 rval = 0;
6982
6983 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6984 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6985 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
6986 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6987 if (aspm_disable_flag)
6988 e1000e_disable_aspm(pdev, aspm_disable_flag);
6989
6990 err = pci_enable_device_mem(pdev);
6991 if (err)
6992 return err;
6993
6994 pci_using_dac = 0;
6995 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6996 if (!err) {
6997 pci_using_dac = 1;
6998 } else {
6999 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7000 if (err) {
7001 dev_err(&pdev->dev,
7002 "No usable DMA configuration, aborting\n");
7003 goto err_dma;
7004 }
7005 }
7006
7007 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7008 err = pci_request_selected_regions_exclusive(pdev, bars,
7009 e1000e_driver_name);
7010 if (err)
7011 goto err_pci_reg;
7012
7013
7014 pci_enable_pcie_error_reporting(pdev);
7015
7016 pci_set_master(pdev);
7017
7018 err = pci_save_state(pdev);
7019 if (err)
7020 goto err_alloc_etherdev;
7021
7022 err = -ENOMEM;
7023 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7024 if (!netdev)
7025 goto err_alloc_etherdev;
7026
7027 SET_NETDEV_DEV(netdev, &pdev->dev);
7028
7029 netdev->irq = pdev->irq;
7030
7031 pci_set_drvdata(pdev, netdev);
7032 adapter = netdev_priv(netdev);
7033 hw = &adapter->hw;
7034 adapter->netdev = netdev;
7035 adapter->pdev = pdev;
7036 adapter->ei = ei;
7037 adapter->pba = ei->pba;
7038 adapter->flags = ei->flags;
7039 adapter->flags2 = ei->flags2;
7040 adapter->hw.adapter = adapter;
7041 adapter->hw.mac.type = ei->mac;
7042 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7043 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7044
7045 mmio_start = pci_resource_start(pdev, 0);
7046 mmio_len = pci_resource_len(pdev, 0);
7047
7048 err = -EIO;
7049 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7050 if (!adapter->hw.hw_addr)
7051 goto err_ioremap;
7052
7053 if ((adapter->flags & FLAG_HAS_FLASH) &&
7054 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7055 (hw->mac.type < e1000_pch_spt)) {
7056 flash_start = pci_resource_start(pdev, 1);
7057 flash_len = pci_resource_len(pdev, 1);
7058 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7059 if (!adapter->hw.flash_address)
7060 goto err_flashmap;
7061 }
7062
7063
7064 if (adapter->flags2 & FLAG2_HAS_EEE)
7065 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7066
7067
7068 netdev->netdev_ops = &e1000e_netdev_ops;
7069 e1000e_set_ethtool_ops(netdev);
7070 netdev->watchdog_timeo = 5 * HZ;
7071 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
7072 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7073
7074 netdev->mem_start = mmio_start;
7075 netdev->mem_end = mmio_start + mmio_len;
7076
7077 adapter->bd_number = cards_found++;
7078
7079 e1000e_check_options(adapter);
7080
7081
7082 err = e1000_sw_init(adapter);
7083 if (err)
7084 goto err_sw_init;
7085
7086 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7087 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7088 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7089
7090 err = ei->get_variants(adapter);
7091 if (err)
7092 goto err_hw_init;
7093
7094 if ((adapter->flags & FLAG_IS_ICH) &&
7095 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7096 (hw->mac.type < e1000_pch_spt))
7097 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7098
7099 hw->mac.ops.get_bus_info(&adapter->hw);
7100
7101 adapter->hw.phy.autoneg_wait_to_complete = 0;
7102
7103
7104 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7105 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7106 adapter->hw.phy.disable_polarity_correction = 0;
7107 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7108 }
7109
7110 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7111 dev_info(&pdev->dev,
7112 "PHY reset is blocked due to SOL/IDER session.\n");
7113
7114
7115 netdev->features = (NETIF_F_SG |
7116 NETIF_F_HW_VLAN_CTAG_RX |
7117 NETIF_F_HW_VLAN_CTAG_TX |
7118 NETIF_F_TSO |
7119 NETIF_F_TSO6 |
7120 NETIF_F_RXHASH |
7121 NETIF_F_RXCSUM |
7122 NETIF_F_HW_CSUM);
7123
7124
7125 netdev->hw_features = netdev->features;
7126 netdev->hw_features |= NETIF_F_RXFCS;
7127 netdev->priv_flags |= IFF_SUPP_NOFCS;
7128 netdev->hw_features |= NETIF_F_RXALL;
7129
7130 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7131 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7132
7133 netdev->vlan_features |= (NETIF_F_SG |
7134 NETIF_F_TSO |
7135 NETIF_F_TSO6 |
7136 NETIF_F_HW_CSUM);
7137
7138 netdev->priv_flags |= IFF_UNICAST_FLT;
7139
7140 if (pci_using_dac) {
7141 netdev->features |= NETIF_F_HIGHDMA;
7142 netdev->vlan_features |= NETIF_F_HIGHDMA;
7143 }
7144
7145 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7146 adapter->flags |= FLAG_MNG_PT_ENABLED;
7147
7148
7149
7150
7151 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7152
7153
7154
7155
7156 for (i = 0;; i++) {
7157 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7158 break;
7159 if (i == 2) {
7160 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7161 err = -EIO;
7162 goto err_eeprom;
7163 }
7164 }
7165
7166 e1000_eeprom_checks(adapter);
7167
7168
7169 if (e1000e_read_mac_addr(&adapter->hw))
7170 dev_err(&pdev->dev,
7171 "NVM Read Error while reading MAC address\n");
7172
7173 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
7174
7175 if (!is_valid_ether_addr(netdev->dev_addr)) {
7176 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7177 netdev->dev_addr);
7178 err = -EIO;
7179 goto err_eeprom;
7180 }
7181
7182 init_timer(&adapter->watchdog_timer);
7183 adapter->watchdog_timer.function = e1000_watchdog;
7184 adapter->watchdog_timer.data = (unsigned long)adapter;
7185
7186 init_timer(&adapter->phy_info_timer);
7187 adapter->phy_info_timer.function = e1000_update_phy_info;
7188 adapter->phy_info_timer.data = (unsigned long)adapter;
7189
7190 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7191 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7192 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7193 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7194 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7195
7196
7197 adapter->hw.mac.autoneg = 1;
7198 adapter->fc_autoneg = true;
7199 adapter->hw.fc.requested_mode = e1000_fc_default;
7200 adapter->hw.fc.current_mode = e1000_fc_default;
7201 adapter->hw.phy.autoneg_advertised = 0x2f;
7202
7203
7204
7205
7206 if (adapter->flags & FLAG_APME_IN_WUC) {
7207
7208 eeprom_data = er32(WUC);
7209 eeprom_apme_mask = E1000_WUC_APME;
7210 if ((hw->mac.type > e1000_ich10lan) &&
7211 (eeprom_data & E1000_WUC_PHY_WAKE))
7212 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7213 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7214 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7215 (adapter->hw.bus.func == 1))
7216 rval = e1000_read_nvm(&adapter->hw,
7217 NVM_INIT_CONTROL3_PORT_B,
7218 1, &eeprom_data);
7219 else
7220 rval = e1000_read_nvm(&adapter->hw,
7221 NVM_INIT_CONTROL3_PORT_A,
7222 1, &eeprom_data);
7223 }
7224
7225
7226 if (rval)
7227 e_dbg("NVM read error getting WoL initial values: %d\n", rval);
7228 else if (eeprom_data & eeprom_apme_mask)
7229 adapter->eeprom_wol |= E1000_WUFC_MAG;
7230
7231
7232
7233
7234
7235 if (!(adapter->flags & FLAG_HAS_WOL))
7236 adapter->eeprom_wol = 0;
7237
7238
7239 adapter->wol = adapter->eeprom_wol;
7240
7241
7242 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7243 (hw->mac.ops.check_mng_mode(hw)))
7244 device_wakeup_enable(&pdev->dev);
7245
7246
7247 rval = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7248
7249 if (rval) {
7250 e_dbg("NVM read error getting EEPROM version: %d\n", rval);
7251 adapter->eeprom_vers = 0;
7252 }
7253
7254
7255 e1000e_reset(adapter);
7256
7257
7258
7259
7260
7261 if (!(adapter->flags & FLAG_HAS_AMT))
7262 e1000e_get_hw_control(adapter);
7263
7264 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
7265 err = register_netdev(netdev);
7266 if (err)
7267 goto err_register;
7268
7269
7270 netif_carrier_off(netdev);
7271
7272
7273 e1000e_ptp_init(adapter);
7274
7275 e1000_print_device_info(adapter);
7276
7277 if (pci_dev_run_wake(pdev))
7278 pm_runtime_put_noidle(&pdev->dev);
7279
7280 return 0;
7281
7282err_register:
7283 if (!(adapter->flags & FLAG_HAS_AMT))
7284 e1000e_release_hw_control(adapter);
7285err_eeprom:
7286 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7287 e1000_phy_hw_reset(&adapter->hw);
7288err_hw_init:
7289 kfree(adapter->tx_ring);
7290 kfree(adapter->rx_ring);
7291err_sw_init:
7292 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7293 iounmap(adapter->hw.flash_address);
7294 e1000e_reset_interrupt_capability(adapter);
7295err_flashmap:
7296 iounmap(adapter->hw.hw_addr);
7297err_ioremap:
7298 free_netdev(netdev);
7299err_alloc_etherdev:
7300 pci_release_selected_regions(pdev,
7301 pci_select_bars(pdev, IORESOURCE_MEM));
7302err_pci_reg:
7303err_dma:
7304 pci_disable_device(pdev);
7305 return err;
7306}
7307
7308
7309
7310
7311
7312
7313
7314
7315
7316
7317static void e1000_remove(struct pci_dev *pdev)
7318{
7319 struct net_device *netdev = pci_get_drvdata(pdev);
7320 struct e1000_adapter *adapter = netdev_priv(netdev);
7321 bool down = test_bit(__E1000_DOWN, &adapter->state);
7322
7323 e1000e_ptp_remove(adapter);
7324
7325
7326
7327
7328 if (!down)
7329 set_bit(__E1000_DOWN, &adapter->state);
7330 del_timer_sync(&adapter->watchdog_timer);
7331 del_timer_sync(&adapter->phy_info_timer);
7332
7333 cancel_work_sync(&adapter->reset_task);
7334 cancel_work_sync(&adapter->watchdog_task);
7335 cancel_work_sync(&adapter->downshift_task);
7336 cancel_work_sync(&adapter->update_phy_task);
7337 cancel_work_sync(&adapter->print_hang_task);
7338
7339 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7340 cancel_work_sync(&adapter->tx_hwtstamp_work);
7341 if (adapter->tx_hwtstamp_skb) {
7342 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
7343 adapter->tx_hwtstamp_skb = NULL;
7344 }
7345 }
7346
7347
7348 if (!down)
7349 clear_bit(__E1000_DOWN, &adapter->state);
7350 unregister_netdev(netdev);
7351
7352 if (pci_dev_run_wake(pdev))
7353 pm_runtime_get_noresume(&pdev->dev);
7354
7355
7356
7357
7358 e1000e_release_hw_control(adapter);
7359
7360 e1000e_reset_interrupt_capability(adapter);
7361 kfree(adapter->tx_ring);
7362 kfree(adapter->rx_ring);
7363
7364 iounmap(adapter->hw.hw_addr);
7365 if ((adapter->hw.flash_address) &&
7366 (adapter->hw.mac.type < e1000_pch_spt))
7367 iounmap(adapter->hw.flash_address);
7368 pci_release_selected_regions(pdev,
7369 pci_select_bars(pdev, IORESOURCE_MEM));
7370
7371 free_netdev(netdev);
7372
7373
7374 pci_disable_pcie_error_reporting(pdev);
7375
7376 pci_disable_device(pdev);
7377}
7378
7379
7380static const struct pci_error_handlers e1000_err_handler = {
7381 .error_detected = e1000_io_error_detected,
7382 .slot_reset = e1000_io_slot_reset,
7383 .resume = e1000_io_resume,
7384};
7385
7386static const struct pci_device_id e1000_pci_tbl[] = {
7387 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7388 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7389 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7390 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7391 board_82571 },
7392 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7393 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7394 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7395 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7396 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7397
7398 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7399 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7400 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7401 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7402
7403 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7404 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7405 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7406
7407 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7408 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7409 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7410
7411 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7412 board_80003es2lan },
7413 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7414 board_80003es2lan },
7415 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7416 board_80003es2lan },
7417 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7418 board_80003es2lan },
7419
7420 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7421 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7422 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7423 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7424 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7425 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7426 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7427 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7428
7429 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7430 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7431 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7432 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7433 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7434 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7435 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7436 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7437 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7438
7439 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7440 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7441 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7442
7443 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7444 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7445 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7446
7447 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7448 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7449 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7450 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7451
7452 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7453 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7454
7455 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7456 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7457 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7458 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7459 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7460 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7461 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7462 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7463 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7464 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7465 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7466 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7467
7468 { 0, 0, 0, 0, 0, 0, 0 }
7469};
7470MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7471
7472static const struct dev_pm_ops e1000_pm_ops = {
7473#ifdef CONFIG_PM_SLEEP
7474 .suspend = e1000e_pm_suspend,
7475 .resume = e1000e_pm_resume,
7476 .freeze = e1000e_pm_freeze,
7477 .thaw = e1000e_pm_thaw,
7478 .poweroff = e1000e_pm_suspend,
7479 .restore = e1000e_pm_resume,
7480#endif
7481 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7482 e1000e_pm_runtime_idle)
7483};
7484
7485
7486static struct pci_driver e1000_driver = {
7487 .name = e1000e_driver_name,
7488 .id_table = e1000_pci_tbl,
7489 .probe = e1000_probe,
7490 .remove = e1000_remove,
7491 .driver = {
7492 .pm = &e1000_pm_ops,
7493 },
7494 .shutdown = e1000_shutdown,
7495 .err_handler = &e1000_err_handler
7496};
7497
7498
7499
7500
7501
7502
7503
7504static int __init e1000_init_module(void)
7505{
7506 int ret;
7507
7508 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7509 e1000e_driver_version);
7510 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7511 ret = pci_register_driver(&e1000_driver);
7512
7513 return ret;
7514}
7515module_init(e1000_init_module);
7516
7517
7518
7519
7520
7521
7522
7523static void __exit e1000_exit_module(void)
7524{
7525 pci_unregister_driver(&e1000_driver);
7526}
7527module_exit(e1000_exit_module);
7528
7529MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7530MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7531MODULE_LICENSE("GPL");
7532MODULE_VERSION(DRV_VERSION);
7533
7534
7535