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27#ifndef _I40E_TYPE_H_
28#define _I40E_TYPE_H_
29
30#include "i40e_status.h"
31#include "i40e_osdep.h"
32#include "i40e_register.h"
33#include "i40e_adminq.h"
34#include "i40e_hmc.h"
35#include "i40e_lan_hmc.h"
36
37
38#define I40E_DEV_ID_SFP_XL710 0x1572
39#define I40E_DEV_ID_QEMU 0x1574
40#define I40E_DEV_ID_KX_A 0x157F
41#define I40E_DEV_ID_KX_B 0x1580
42#define I40E_DEV_ID_KX_C 0x1581
43#define I40E_DEV_ID_QSFP_A 0x1583
44#define I40E_DEV_ID_QSFP_B 0x1584
45#define I40E_DEV_ID_QSFP_C 0x1585
46#define I40E_DEV_ID_10G_BASE_T 0x1586
47#define I40E_DEV_ID_20G_KR2 0x1587
48#define I40E_DEV_ID_VF 0x154C
49#define I40E_DEV_ID_VF_HV 0x1571
50#define I40E_DEV_ID_SFP_X722 0x37D0
51#define I40E_DEV_ID_1G_BASE_T_X722 0x37D1
52#define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
53#define I40E_DEV_ID_X722_VF 0x37CD
54#define I40E_DEV_ID_X722_VF_HV 0x37D9
55
56#define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
57 (d) == I40E_DEV_ID_QSFP_B || \
58 (d) == I40E_DEV_ID_QSFP_C)
59
60
61#define I40E_MASK(mask, shift) (mask << shift)
62
63#define I40E_MAX_VSI_QP 16
64#define I40E_MAX_VF_VSI 3
65#define I40E_MAX_CHAINED_RX_BUFFERS 5
66#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
67
68
69#define I40E_MAX_NVM_TIMEOUT 18000
70
71
72#define I40E_MS_TO_GTIME(time) ((time) * 1000)
73
74
75struct i40e_hw;
76typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
77
78
79
80#define I40E_DESC_UNUSED(R) \
81 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
82 (R)->next_to_clean - (R)->next_to_use - 1)
83
84
85#define I40E_QTX_CTL_VF_QUEUE 0x0
86#define I40E_QTX_CTL_VM_QUEUE 0x1
87#define I40E_QTX_CTL_PF_QUEUE 0x2
88
89
90enum i40e_debug_mask {
91 I40E_DEBUG_INIT = 0x00000001,
92 I40E_DEBUG_RELEASE = 0x00000002,
93
94 I40E_DEBUG_LINK = 0x00000010,
95 I40E_DEBUG_PHY = 0x00000020,
96 I40E_DEBUG_HMC = 0x00000040,
97 I40E_DEBUG_NVM = 0x00000080,
98 I40E_DEBUG_LAN = 0x00000100,
99 I40E_DEBUG_FLOW = 0x00000200,
100 I40E_DEBUG_DCB = 0x00000400,
101 I40E_DEBUG_DIAG = 0x00000800,
102 I40E_DEBUG_FD = 0x00001000,
103
104 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
105 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
106 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
107 I40E_DEBUG_AQ_COMMAND = 0x06000000,
108 I40E_DEBUG_AQ = 0x0F000000,
109
110 I40E_DEBUG_USER = 0xF0000000,
111
112 I40E_DEBUG_ALL = 0xFFFFFFFF
113};
114
115
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118
119
120
121
122
123enum i40e_mac_type {
124 I40E_MAC_UNKNOWN = 0,
125 I40E_MAC_X710,
126 I40E_MAC_XL710,
127 I40E_MAC_VF,
128 I40E_MAC_X722,
129 I40E_MAC_X722_VF,
130 I40E_MAC_GENERIC,
131};
132
133enum i40e_media_type {
134 I40E_MEDIA_TYPE_UNKNOWN = 0,
135 I40E_MEDIA_TYPE_FIBER,
136 I40E_MEDIA_TYPE_BASET,
137 I40E_MEDIA_TYPE_BACKPLANE,
138 I40E_MEDIA_TYPE_CX4,
139 I40E_MEDIA_TYPE_DA,
140 I40E_MEDIA_TYPE_VIRTUAL
141};
142
143enum i40e_fc_mode {
144 I40E_FC_NONE = 0,
145 I40E_FC_RX_PAUSE,
146 I40E_FC_TX_PAUSE,
147 I40E_FC_FULL,
148 I40E_FC_PFC,
149 I40E_FC_DEFAULT
150};
151
152enum i40e_set_fc_aq_failures {
153 I40E_SET_FC_AQ_FAIL_NONE = 0,
154 I40E_SET_FC_AQ_FAIL_GET = 1,
155 I40E_SET_FC_AQ_FAIL_SET = 2,
156 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
157 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
158};
159
160enum i40e_vsi_type {
161 I40E_VSI_MAIN = 0,
162 I40E_VSI_VMDQ1,
163 I40E_VSI_VMDQ2,
164 I40E_VSI_CTRL,
165 I40E_VSI_FCOE,
166 I40E_VSI_MIRROR,
167 I40E_VSI_SRIOV,
168 I40E_VSI_FDIR,
169 I40E_VSI_TYPE_UNKNOWN
170};
171
172enum i40e_queue_type {
173 I40E_QUEUE_TYPE_RX = 0,
174 I40E_QUEUE_TYPE_TX,
175 I40E_QUEUE_TYPE_PE_CEQ,
176 I40E_QUEUE_TYPE_UNKNOWN
177};
178
179struct i40e_link_status {
180 enum i40e_aq_phy_type phy_type;
181 enum i40e_aq_link_speed link_speed;
182 u8 link_info;
183 u8 an_info;
184 u8 ext_info;
185 u8 loopback;
186
187 bool lse_enable;
188 u16 max_frame_size;
189 bool crc_enable;
190 u8 pacing;
191 u8 requested_speeds;
192};
193
194struct i40e_phy_info {
195 struct i40e_link_status link_info;
196 struct i40e_link_status link_info_old;
197 u32 autoneg_advertised;
198 u32 phy_id;
199 u32 module_type;
200 bool get_link_info;
201 enum i40e_media_type media_type;
202};
203
204#define I40E_HW_CAP_MAX_GPIO 30
205
206struct i40e_hw_capabilities {
207 u32 switch_mode;
208#define I40E_NVM_IMAGE_TYPE_EVB 0x0
209#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
210#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
211
212 u32 management_mode;
213 u32 npar_enable;
214 u32 os2bmc;
215 u32 valid_functions;
216 bool sr_iov_1_1;
217 bool vmdq;
218 bool evb_802_1_qbg;
219 bool evb_802_1_qbh;
220 bool dcb;
221 bool fcoe;
222 bool iscsi;
223 bool flex10_enable;
224 bool flex10_capable;
225 u32 flex10_mode;
226#define I40E_FLEX10_MODE_UNKNOWN 0x0
227#define I40E_FLEX10_MODE_DCC 0x1
228#define I40E_FLEX10_MODE_DCI 0x2
229
230 u32 flex10_status;
231#define I40E_FLEX10_STATUS_DCC_ERROR 0x1
232#define I40E_FLEX10_STATUS_VC_MODE 0x2
233
234 bool mgmt_cem;
235 bool ieee_1588;
236 bool iwarp;
237 bool fd;
238 u32 fd_filters_guaranteed;
239 u32 fd_filters_best_effort;
240 bool rss;
241 u32 rss_table_size;
242 u32 rss_table_entry_width;
243 bool led[I40E_HW_CAP_MAX_GPIO];
244 bool sdp[I40E_HW_CAP_MAX_GPIO];
245 u32 nvm_image_type;
246 u32 num_flow_director_filters;
247 u32 num_vfs;
248 u32 vf_base_id;
249 u32 num_vsis;
250 u32 num_rx_qp;
251 u32 num_tx_qp;
252 u32 base_queue;
253 u32 num_msix_vectors;
254 u32 num_msix_vectors_vf;
255 u32 led_pin_num;
256 u32 sdp_pin_num;
257 u32 mdio_port_num;
258 u32 mdio_port_mode;
259 u8 rx_buf_chain_len;
260 u32 enabled_tcmap;
261 u32 maxtc;
262 u64 wr_csr_prot;
263};
264
265struct i40e_mac_info {
266 enum i40e_mac_type type;
267 u8 addr[ETH_ALEN];
268 u8 perm_addr[ETH_ALEN];
269 u8 san_addr[ETH_ALEN];
270 u8 port_addr[ETH_ALEN];
271 u16 max_fcoeq;
272};
273
274enum i40e_aq_resources_ids {
275 I40E_NVM_RESOURCE_ID = 1
276};
277
278enum i40e_aq_resource_access_type {
279 I40E_RESOURCE_READ = 1,
280 I40E_RESOURCE_WRITE
281};
282
283struct i40e_nvm_info {
284 u64 hw_semaphore_timeout;
285 u32 timeout;
286 u16 sr_size;
287 bool blank_nvm_mode;
288 u16 version;
289 u32 eetrack;
290};
291
292
293
294enum i40e_nvmupd_cmd {
295 I40E_NVMUPD_INVALID,
296 I40E_NVMUPD_READ_CON,
297 I40E_NVMUPD_READ_SNT,
298 I40E_NVMUPD_READ_LCB,
299 I40E_NVMUPD_READ_SA,
300 I40E_NVMUPD_WRITE_ERA,
301 I40E_NVMUPD_WRITE_CON,
302 I40E_NVMUPD_WRITE_SNT,
303 I40E_NVMUPD_WRITE_LCB,
304 I40E_NVMUPD_WRITE_SA,
305 I40E_NVMUPD_CSUM_CON,
306 I40E_NVMUPD_CSUM_SA,
307 I40E_NVMUPD_CSUM_LCB,
308};
309
310enum i40e_nvmupd_state {
311 I40E_NVMUPD_STATE_INIT,
312 I40E_NVMUPD_STATE_READING,
313 I40E_NVMUPD_STATE_WRITING
314};
315
316
317
318
319#define I40E_NVM_READ 0xB
320#define I40E_NVM_WRITE 0xC
321
322#define I40E_NVM_MOD_PNT_MASK 0xFF
323
324#define I40E_NVM_TRANS_SHIFT 8
325#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
326#define I40E_NVM_CON 0x0
327#define I40E_NVM_SNT 0x1
328#define I40E_NVM_LCB 0x2
329#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
330#define I40E_NVM_ERA 0x4
331#define I40E_NVM_CSUM 0x8
332
333#define I40E_NVM_ADAPT_SHIFT 16
334#define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
335
336#define I40E_NVMUPD_MAX_DATA 4096
337#define I40E_NVMUPD_IFACE_TIMEOUT 2
338
339struct i40e_nvm_access {
340 u32 command;
341 u32 config;
342 u32 offset;
343 u32 data_size;
344 u8 data[1];
345};
346
347
348enum i40e_bus_type {
349 i40e_bus_type_unknown = 0,
350 i40e_bus_type_pci,
351 i40e_bus_type_pcix,
352 i40e_bus_type_pci_express,
353 i40e_bus_type_reserved
354};
355
356
357enum i40e_bus_speed {
358 i40e_bus_speed_unknown = 0,
359 i40e_bus_speed_33 = 33,
360 i40e_bus_speed_66 = 66,
361 i40e_bus_speed_100 = 100,
362 i40e_bus_speed_120 = 120,
363 i40e_bus_speed_133 = 133,
364 i40e_bus_speed_2500 = 2500,
365 i40e_bus_speed_5000 = 5000,
366 i40e_bus_speed_8000 = 8000,
367 i40e_bus_speed_reserved
368};
369
370
371enum i40e_bus_width {
372 i40e_bus_width_unknown = 0,
373 i40e_bus_width_pcie_x1 = 1,
374 i40e_bus_width_pcie_x2 = 2,
375 i40e_bus_width_pcie_x4 = 4,
376 i40e_bus_width_pcie_x8 = 8,
377 i40e_bus_width_32 = 32,
378 i40e_bus_width_64 = 64,
379 i40e_bus_width_reserved
380};
381
382
383struct i40e_bus_info {
384 enum i40e_bus_speed speed;
385 enum i40e_bus_width width;
386 enum i40e_bus_type type;
387
388 u16 func;
389 u16 device;
390 u16 lan_id;
391};
392
393
394struct i40e_fc_info {
395 enum i40e_fc_mode current_mode;
396 enum i40e_fc_mode requested_mode;
397};
398
399#define I40E_MAX_TRAFFIC_CLASS 8
400#define I40E_MAX_USER_PRIORITY 8
401#define I40E_DCBX_MAX_APPS 32
402#define I40E_LLDPDU_SIZE 1500
403#define I40E_TLV_STATUS_OPER 0x1
404#define I40E_TLV_STATUS_SYNC 0x2
405#define I40E_TLV_STATUS_ERR 0x4
406#define I40E_CEE_OPER_MAX_APPS 3
407#define I40E_APP_PROTOID_FCOE 0x8906
408#define I40E_APP_PROTOID_ISCSI 0x0cbc
409#define I40E_APP_PROTOID_FIP 0x8914
410#define I40E_APP_SEL_ETHTYPE 0x1
411#define I40E_APP_SEL_TCPIP 0x2
412
413
414struct i40e_dcb_ets_config {
415 u8 willing;
416 u8 cbs;
417 u8 maxtcs;
418 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
419 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
420 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
421};
422
423
424struct i40e_dcb_pfc_config {
425 u8 willing;
426 u8 mbc;
427 u8 pfccap;
428 u8 pfcenable;
429};
430
431
432struct i40e_dcb_app_priority_table {
433 u8 priority;
434 u8 selector;
435 u16 protocolid;
436};
437
438struct i40e_dcbx_config {
439 u8 dcbx_mode;
440#define I40E_DCBX_MODE_CEE 0x1
441#define I40E_DCBX_MODE_IEEE 0x2
442 u32 numapps;
443 u32 tlv_status;
444 struct i40e_dcb_ets_config etscfg;
445 struct i40e_dcb_ets_config etsrec;
446 struct i40e_dcb_pfc_config pfc;
447 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
448};
449
450
451struct i40e_hw {
452 u8 __iomem *hw_addr;
453 void *back;
454
455
456 struct i40e_phy_info phy;
457 struct i40e_mac_info mac;
458 struct i40e_bus_info bus;
459 struct i40e_nvm_info nvm;
460 struct i40e_fc_info fc;
461
462
463 u16 device_id;
464 u16 vendor_id;
465 u16 subsystem_device_id;
466 u16 subsystem_vendor_id;
467 u8 revision_id;
468 u8 port;
469 bool adapter_stopped;
470
471
472 struct i40e_hw_capabilities dev_caps;
473 struct i40e_hw_capabilities func_caps;
474
475
476 u16 fdir_shared_filter_count;
477
478
479 u8 pf_id;
480 u16 main_vsi_seid;
481
482
483 u16 partition_id;
484 u16 num_partitions;
485 u16 num_ports;
486
487
488 u16 numa_node;
489
490
491 struct i40e_adminq_info aq;
492
493
494 enum i40e_nvmupd_state nvmupd_state;
495
496
497 struct i40e_hmc_info hmc;
498
499
500 u16 dcbx_status;
501
502
503 struct i40e_dcbx_config local_dcbx_config;
504 struct i40e_dcbx_config remote_dcbx_config;
505
506
507 u32 debug_mask;
508 char err_str[16];
509};
510
511static inline bool i40e_is_vf(struct i40e_hw *hw)
512{
513 return (hw->mac.type == I40E_MAC_VF ||
514 hw->mac.type == I40E_MAC_X722_VF);
515}
516
517struct i40e_driver_version {
518 u8 major_version;
519 u8 minor_version;
520 u8 build_version;
521 u8 subbuild_version;
522 u8 driver_string[32];
523};
524
525
526union i40e_16byte_rx_desc {
527 struct {
528 __le64 pkt_addr;
529 __le64 hdr_addr;
530 } read;
531 struct {
532 struct {
533 struct {
534 union {
535 __le16 mirroring_status;
536 __le16 fcoe_ctx_id;
537 } mirr_fcoe;
538 __le16 l2tag1;
539 } lo_dword;
540 union {
541 __le32 rss;
542 __le32 fd_id;
543 __le32 fcoe_param;
544 } hi_dword;
545 } qword0;
546 struct {
547
548 __le64 status_error_len;
549 } qword1;
550 } wb;
551};
552
553union i40e_32byte_rx_desc {
554 struct {
555 __le64 pkt_addr;
556 __le64 hdr_addr;
557
558 __le64 rsvd1;
559 __le64 rsvd2;
560 } read;
561 struct {
562 struct {
563 struct {
564 union {
565 __le16 mirroring_status;
566 __le16 fcoe_ctx_id;
567 } mirr_fcoe;
568 __le16 l2tag1;
569 } lo_dword;
570 union {
571 __le32 rss;
572 __le32 fcoe_param;
573
574
575
576 __le32 fd_id;
577 } hi_dword;
578 } qword0;
579 struct {
580
581 __le64 status_error_len;
582 } qword1;
583 struct {
584 __le16 ext_status;
585 __le16 rsvd;
586 __le16 l2tag2_1;
587 __le16 l2tag2_2;
588 } qword2;
589 struct {
590 union {
591 __le32 flex_bytes_lo;
592 __le32 pe_status;
593 } lo_dword;
594 union {
595 __le32 flex_bytes_hi;
596 __le32 fd_id;
597 } hi_dword;
598 } qword3;
599 } wb;
600};
601
602enum i40e_rx_desc_status_bits {
603
604 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
605 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
606 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
607 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
608 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
609 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5,
610 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
611
612 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
613 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9,
614 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
615 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12,
616 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
617 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
618 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16,
619
620
621
622 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
623 I40E_RX_DESC_STATUS_LAST
624};
625
626#define I40E_RXD_QW1_STATUS_SHIFT 0
627#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
628 << I40E_RXD_QW1_STATUS_SHIFT)
629
630#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
631#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
632 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
633
634#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
635#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
636 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
637
638enum i40e_rx_desc_fltstat_values {
639 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
640 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1,
641 I40E_RX_DESC_FLTSTAT_RSV = 2,
642 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
643};
644
645#define I40E_RXD_QW1_ERROR_SHIFT 19
646#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
647
648enum i40e_rx_desc_error_bits {
649
650 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
651 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
652 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
653 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3,
654 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
655 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
656 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
657 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
658 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
659};
660
661enum i40e_rx_desc_error_l3l4e_fcoe_masks {
662 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
663 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
664 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
665 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
666 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
667};
668
669#define I40E_RXD_QW1_PTYPE_SHIFT 30
670#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
671
672
673enum i40e_rx_l2_ptype {
674 I40E_RX_PTYPE_L2_RESERVED = 0,
675 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
676 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
677 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
678 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
679 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
680 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
681 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
682 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
683 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
684 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
685 I40E_RX_PTYPE_L2_ARP = 11,
686 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
687 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
688 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
689 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
690 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
691 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
692 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
693 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
694 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
695 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
696 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
697 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
698 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
699 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
700};
701
702struct i40e_rx_ptype_decoded {
703 u32 ptype:8;
704 u32 known:1;
705 u32 outer_ip:1;
706 u32 outer_ip_ver:1;
707 u32 outer_frag:1;
708 u32 tunnel_type:3;
709 u32 tunnel_end_prot:2;
710 u32 tunnel_end_frag:1;
711 u32 inner_prot:4;
712 u32 payload_layer:3;
713};
714
715enum i40e_rx_ptype_outer_ip {
716 I40E_RX_PTYPE_OUTER_L2 = 0,
717 I40E_RX_PTYPE_OUTER_IP = 1
718};
719
720enum i40e_rx_ptype_outer_ip_ver {
721 I40E_RX_PTYPE_OUTER_NONE = 0,
722 I40E_RX_PTYPE_OUTER_IPV4 = 0,
723 I40E_RX_PTYPE_OUTER_IPV6 = 1
724};
725
726enum i40e_rx_ptype_outer_fragmented {
727 I40E_RX_PTYPE_NOT_FRAG = 0,
728 I40E_RX_PTYPE_FRAG = 1
729};
730
731enum i40e_rx_ptype_tunnel_type {
732 I40E_RX_PTYPE_TUNNEL_NONE = 0,
733 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
734 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
735 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
736 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
737};
738
739enum i40e_rx_ptype_tunnel_end_prot {
740 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
741 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
742 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
743};
744
745enum i40e_rx_ptype_inner_prot {
746 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
747 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
748 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
749 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
750 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
751 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
752};
753
754enum i40e_rx_ptype_payload_layer {
755 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
756 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
757 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
758 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
759};
760
761#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
762#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
763 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
764
765#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
766#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
767 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
768
769#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
770#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
771
772enum i40e_rx_desc_ext_status_bits {
773
774 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
775 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
776 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2,
777 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4,
778 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
779 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
780 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
781};
782
783enum i40e_rx_desc_pe_status_bits {
784
785 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0,
786 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0,
787 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16,
788 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
789 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
790 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
791 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
792 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
793 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
794};
795
796#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
797#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
798
799#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
800#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
801 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
802
803#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
804#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
805 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
806
807enum i40e_rx_prog_status_desc_status_bits {
808
809 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
810 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2
811};
812
813enum i40e_rx_prog_status_desc_prog_id_masks {
814 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
815 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
816 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
817};
818
819enum i40e_rx_prog_status_desc_error_bits {
820
821 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
822 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
823 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
824 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
825};
826
827
828struct i40e_tx_desc {
829 __le64 buffer_addr;
830 __le64 cmd_type_offset_bsz;
831};
832
833#define I40E_TXD_QW1_DTYPE_SHIFT 0
834#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
835
836enum i40e_tx_desc_dtype_value {
837 I40E_TX_DESC_DTYPE_DATA = 0x0,
838 I40E_TX_DESC_DTYPE_NOP = 0x1,
839 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
840 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
841 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
842 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
843 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
844 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
845 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
846 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
847};
848
849#define I40E_TXD_QW1_CMD_SHIFT 4
850#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
851
852enum i40e_tx_desc_cmd_bits {
853 I40E_TX_DESC_CMD_EOP = 0x0001,
854 I40E_TX_DESC_CMD_RS = 0x0002,
855 I40E_TX_DESC_CMD_ICRC = 0x0004,
856 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
857 I40E_TX_DESC_CMD_DUMMY = 0x0010,
858 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000,
859 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020,
860 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040,
861 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060,
862 I40E_TX_DESC_CMD_FCOET = 0x0080,
863 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000,
864 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100,
865 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200,
866 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300,
867 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000,
868 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100,
869 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200,
870 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300,
871};
872
873#define I40E_TXD_QW1_OFFSET_SHIFT 16
874#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
875 I40E_TXD_QW1_OFFSET_SHIFT)
876
877enum i40e_tx_desc_length_fields {
878
879 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0,
880 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7,
881 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14
882};
883
884#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
885#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
886 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
887
888#define I40E_TXD_QW1_L2TAG1_SHIFT 48
889#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
890
891
892struct i40e_tx_context_desc {
893 __le32 tunneling_params;
894 __le16 l2tag2;
895 __le16 rsvd;
896 __le64 type_cmd_tso_mss;
897};
898
899#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
900#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
901
902#define I40E_TXD_CTX_QW1_CMD_SHIFT 4
903#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
904
905enum i40e_tx_ctx_desc_cmd_bits {
906 I40E_TX_CTX_DESC_TSO = 0x01,
907 I40E_TX_CTX_DESC_TSYN = 0x02,
908 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
909 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
910 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
911 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
912 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
913 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
914 I40E_TX_CTX_DESC_SWPE = 0x40
915};
916
917#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
918#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
919 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
920
921#define I40E_TXD_CTX_QW1_MSS_SHIFT 50
922#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
923 I40E_TXD_CTX_QW1_MSS_SHIFT)
924
925#define I40E_TXD_CTX_QW1_VSI_SHIFT 50
926#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
927
928#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
929#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
930 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
931
932enum i40e_tx_ctx_desc_eipt_offload {
933 I40E_TX_CTX_EXT_IP_NONE = 0x0,
934 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
935 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
936 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
937};
938
939#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
940#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
941 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
942
943#define I40E_TXD_CTX_QW0_NATT_SHIFT 9
944#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
945
946#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
947#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
948
949#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
950#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
951 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
952
953#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
954
955#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
956#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
957 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
958
959#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
960#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
961 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
962
963#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
964#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
965struct i40e_filter_program_desc {
966 __le32 qindex_flex_ptype_vsi;
967 __le32 rsvd;
968 __le32 dtype_cmd_cntindex;
969 __le32 fd_id;
970};
971#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
972#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
973 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
974#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
975#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
976 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
977#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
978#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
979 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
980
981
982enum i40e_filter_pctype {
983
984
985
986 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
987 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
988 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
989 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
990 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
991 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
992 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
993 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
994
995
996
997 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
998 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
999 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1000 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1001 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1002 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1003 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1004 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1005
1006 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1007 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1008 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1009
1010 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1011};
1012
1013enum i40e_filter_program_desc_dest {
1014 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1015 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1016 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1017};
1018
1019enum i40e_filter_program_desc_fd_status {
1020 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1021 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1022 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1023 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1024};
1025
1026#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1027#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1028 BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1029
1030#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1031#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1032 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1033
1034#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1035#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1036
1037enum i40e_filter_program_desc_pcmd {
1038 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1039 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1040};
1041
1042#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1043#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1044
1045#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1046#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1047
1048#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1049 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1050#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1051 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1052
1053#define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1054 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1055#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1056
1057#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1058#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1059 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1060
1061enum i40e_filter_type {
1062 I40E_FLOW_DIRECTOR_FLTR = 0,
1063 I40E_PE_QUAD_HASH_FLTR = 1,
1064 I40E_ETHERTYPE_FLTR,
1065 I40E_FCOE_CTX_FLTR,
1066 I40E_MAC_VLAN_FLTR,
1067 I40E_HASH_FLTR
1068};
1069
1070struct i40e_vsi_context {
1071 u16 seid;
1072 u16 uplink_seid;
1073 u16 vsi_number;
1074 u16 vsis_allocated;
1075 u16 vsis_unallocated;
1076 u16 flags;
1077 u8 pf_num;
1078 u8 vf_num;
1079 u8 connection_type;
1080 struct i40e_aqc_vsi_properties_data info;
1081};
1082
1083struct i40e_veb_context {
1084 u16 seid;
1085 u16 uplink_seid;
1086 u16 veb_number;
1087 u16 vebs_allocated;
1088 u16 vebs_unallocated;
1089 u16 flags;
1090 struct i40e_aqc_get_veb_parameters_completion info;
1091};
1092
1093
1094struct i40e_eth_stats {
1095 u64 rx_bytes;
1096 u64 rx_unicast;
1097 u64 rx_multicast;
1098 u64 rx_broadcast;
1099 u64 rx_discards;
1100 u64 rx_unknown_protocol;
1101 u64 tx_bytes;
1102 u64 tx_unicast;
1103 u64 tx_multicast;
1104 u64 tx_broadcast;
1105 u64 tx_discards;
1106 u64 tx_errors;
1107};
1108
1109
1110struct i40e_veb_tc_stats {
1111 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1112 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1113 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1114 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1115};
1116
1117#ifdef I40E_FCOE
1118
1119struct i40e_fcoe_stats {
1120 u64 rx_fcoe_packets;
1121 u64 rx_fcoe_dwords;
1122 u64 rx_fcoe_dropped;
1123 u64 tx_fcoe_packets;
1124 u64 tx_fcoe_dwords;
1125 u64 fcoe_bad_fccrc;
1126 u64 fcoe_last_error;
1127 u64 fcoe_ddp_count;
1128};
1129
1130
1131#define I40E_FCOE_VF_STAT_OFFSET 0
1132#define I40E_FCOE_PF_STAT_OFFSET 128
1133#define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1134
1135#endif
1136
1137struct i40e_hw_port_stats {
1138
1139 struct i40e_eth_stats eth;
1140
1141
1142 u64 tx_dropped_link_down;
1143 u64 crc_errors;
1144 u64 illegal_bytes;
1145 u64 error_bytes;
1146 u64 mac_local_faults;
1147 u64 mac_remote_faults;
1148 u64 rx_length_errors;
1149 u64 link_xon_rx;
1150 u64 link_xoff_rx;
1151 u64 priority_xon_rx[8];
1152 u64 priority_xoff_rx[8];
1153 u64 link_xon_tx;
1154 u64 link_xoff_tx;
1155 u64 priority_xon_tx[8];
1156 u64 priority_xoff_tx[8];
1157 u64 priority_xon_2_xoff[8];
1158 u64 rx_size_64;
1159 u64 rx_size_127;
1160 u64 rx_size_255;
1161 u64 rx_size_511;
1162 u64 rx_size_1023;
1163 u64 rx_size_1522;
1164 u64 rx_size_big;
1165 u64 rx_undersize;
1166 u64 rx_fragments;
1167 u64 rx_oversize;
1168 u64 rx_jabber;
1169 u64 tx_size_64;
1170 u64 tx_size_127;
1171 u64 tx_size_255;
1172 u64 tx_size_511;
1173 u64 tx_size_1023;
1174 u64 tx_size_1522;
1175 u64 tx_size_big;
1176 u64 mac_short_packet_dropped;
1177 u64 checksum_error;
1178
1179 u64 fd_atr_match;
1180 u64 fd_sb_match;
1181 u64 fd_atr_tunnel_match;
1182 u32 fd_atr_status;
1183 u32 fd_sb_status;
1184
1185 u32 tx_lpi_status;
1186 u32 rx_lpi_status;
1187 u64 tx_lpi_count;
1188 u64 rx_lpi_count;
1189};
1190
1191
1192#define I40E_SR_NVM_CONTROL_WORD 0x00
1193#define I40E_SR_EMP_MODULE_PTR 0x0F
1194#define I40E_SR_PBA_FLAGS 0x15
1195#define I40E_SR_PBA_BLOCK_PTR 0x16
1196#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1197#define I40E_SR_NVM_WAKE_ON_LAN 0x19
1198#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1199#define I40E_SR_NVM_EETRACK_LO 0x2D
1200#define I40E_SR_NVM_EETRACK_HI 0x2E
1201#define I40E_SR_VPD_PTR 0x2F
1202#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1203#define I40E_SR_SW_CHECKSUM_WORD 0x3F
1204
1205
1206#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1207#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1208#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1209#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1210
1211
1212#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1213#define I40E_SR_WORDS_IN_1KB 512
1214
1215
1216
1217#define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1218
1219#define I40E_SRRD_SRCTL_ATTEMPTS 100000
1220
1221#ifdef I40E_FCOE
1222
1223
1224enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1225 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00,
1226 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01,
1227 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05,
1228 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02,
1229 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06,
1230 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03,
1231 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07,
1232 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08,
1233 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09,
1234 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1235 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1236 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1237 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1238};
1239
1240
1241struct i40e_fcoe_ddp_context_desc {
1242 __le64 rsvd;
1243 __le64 type_cmd_foff_lsize;
1244};
1245
1246#define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1247#define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1248 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1249
1250#define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1251#define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1252 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1253
1254enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1255 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00,
1256 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01,
1257 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02,
1258 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03,
1259 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04,
1260 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08,
1261};
1262
1263#define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1264#define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1265 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1266
1267#define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1268#define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1269 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1270
1271
1272struct i40e_fcoe_queue_context_desc {
1273 __le64 dmaindx_fbase;
1274 __le64 flen_tph;
1275};
1276
1277#define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1278#define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1279 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1280
1281#define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1282#define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1283 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1284
1285#define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1286#define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1287 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1288
1289#define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1290#define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1291 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1292
1293enum i40e_fcoe_queue_ctx_desc_tph_bits {
1294 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1295 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1296};
1297
1298#define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1299#define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1300 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1301
1302
1303struct i40e_fcoe_filter_context_desc {
1304 __le32 param;
1305 __le16 seqn;
1306
1307
1308 __le16 rsvd_dmaindx;
1309
1310
1311 __le64 flags_rsvd_lanq;
1312};
1313
1314#define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1315#define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1316 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1317
1318enum i40e_fcoe_filter_ctx_desc_flags_bits {
1319 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1320 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1321 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1322 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1323 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1324 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1325};
1326
1327#define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1328#define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1329 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1330
1331#define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1332#define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1333 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1334
1335#define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1336#define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1337 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1338
1339#endif
1340enum i40e_switch_element_types {
1341 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1342 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1343 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1344 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1345 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1346 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1347 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1348 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1349 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1350};
1351
1352
1353enum i40e_ether_type_index {
1354 I40E_ETHER_TYPE_1588 = 0,
1355 I40E_ETHER_TYPE_FIP = 1,
1356 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1357 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1358 I40E_ETHER_TYPE_LLDP = 4,
1359 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1360 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1361 I40E_ETHER_TYPE_QCN_CNM = 7,
1362 I40E_ETHER_TYPE_8021X = 8,
1363 I40E_ETHER_TYPE_ARP = 9,
1364 I40E_ETHER_TYPE_RSV1 = 10,
1365 I40E_ETHER_TYPE_RSV2 = 11,
1366};
1367
1368
1369#define I40E_HASH_FILTER_BASE_SIZE 1024
1370
1371enum i40e_hash_filter_size {
1372 I40E_HASH_FILTER_SIZE_1K = 0,
1373 I40E_HASH_FILTER_SIZE_2K = 1,
1374 I40E_HASH_FILTER_SIZE_4K = 2,
1375 I40E_HASH_FILTER_SIZE_8K = 3,
1376 I40E_HASH_FILTER_SIZE_16K = 4,
1377 I40E_HASH_FILTER_SIZE_32K = 5,
1378 I40E_HASH_FILTER_SIZE_64K = 6,
1379 I40E_HASH_FILTER_SIZE_128K = 7,
1380 I40E_HASH_FILTER_SIZE_256K = 8,
1381 I40E_HASH_FILTER_SIZE_512K = 9,
1382 I40E_HASH_FILTER_SIZE_1M = 10,
1383};
1384
1385
1386#define I40E_DMA_CNTX_BASE_SIZE 512
1387
1388enum i40e_dma_cntx_size {
1389 I40E_DMA_CNTX_SIZE_512 = 0,
1390 I40E_DMA_CNTX_SIZE_1K = 1,
1391 I40E_DMA_CNTX_SIZE_2K = 2,
1392 I40E_DMA_CNTX_SIZE_4K = 3,
1393 I40E_DMA_CNTX_SIZE_8K = 4,
1394 I40E_DMA_CNTX_SIZE_16K = 5,
1395 I40E_DMA_CNTX_SIZE_32K = 6,
1396 I40E_DMA_CNTX_SIZE_64K = 7,
1397 I40E_DMA_CNTX_SIZE_128K = 8,
1398 I40E_DMA_CNTX_SIZE_256K = 9,
1399};
1400
1401
1402enum i40e_hash_lut_size {
1403 I40E_HASH_LUT_SIZE_128 = 0,
1404 I40E_HASH_LUT_SIZE_512 = 1,
1405};
1406
1407
1408struct i40e_filter_control_settings {
1409
1410 enum i40e_hash_filter_size pe_filt_num;
1411
1412 enum i40e_dma_cntx_size pe_cntx_num;
1413
1414 enum i40e_hash_filter_size fcoe_filt_num;
1415
1416 enum i40e_dma_cntx_size fcoe_cntx_num;
1417
1418 enum i40e_hash_lut_size hash_lut_size;
1419
1420 bool enable_fdir;
1421
1422 bool enable_ethtype;
1423
1424 bool enable_macvlan;
1425};
1426
1427
1428struct i40e_control_filter_stats {
1429 u16 mac_etype_used;
1430 u16 etype_used;
1431 u16 mac_etype_free;
1432 u16 etype_free;
1433};
1434
1435enum i40e_reset_type {
1436 I40E_RESET_POR = 0,
1437 I40E_RESET_CORER = 1,
1438 I40E_RESET_GLOBR = 2,
1439 I40E_RESET_EMPR = 3,
1440};
1441
1442
1443#define I40E_NVM_LLDP_CFG_PTR 0xD
1444struct i40e_lldp_variables {
1445 u16 length;
1446 u16 adminstatus;
1447 u16 msgfasttx;
1448 u16 msgtxinterval;
1449 u16 txparams;
1450 u16 timers;
1451 u16 crc8;
1452};
1453
1454
1455#define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0
1456#define I40E_ALT_STRUCT_DWORDS_PER_PF 64
1457#define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD
1458#define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC
1459#define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE
1460#define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF
1461
1462
1463#define I40E_ALT_BW_VALUE_MASK 0xFF
1464#define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1465#define I40E_ALT_BW_VALID_MASK 0x80000000
1466
1467
1468#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1469#endif
1470
