1/* 2 * Linux MegaRAID driver for SAS based RAID controllers 3 * 4 * Copyright (c) 2009-2013 LSI Corporation 5 * Copyright (c) 2013-2014 Avago Technologies 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 * 20 * FILE: megaraid_sas_fusion.h 21 * 22 * Authors: Avago Technologies 23 * Manoj Jose 24 * Sumant Patro 25 * Kashyap Desai <kashyap.desai@avagotech.com> 26 * Sumit Saxena <sumit.saxena@avagotech.com> 27 * 28 * Send feedback to: megaraidlinux.pdl@avagotech.com 29 * 30 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, 31 * San Jose, California 95131 32 */ 33 34#ifndef _MEGARAID_SAS_FUSION_H_ 35#define _MEGARAID_SAS_FUSION_H_ 36 37/* Fusion defines */ 38#define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 39#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 40#define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 41#define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 42#define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 43#define MEGASAS_LOAD_BALANCE_FLAG 0x1 44#define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1 45#define HOST_DIAG_WRITE_ENABLE 0x80 46#define HOST_DIAG_RESET_ADAPTER 0x4 47#define MEGASAS_FUSION_MAX_RESET_TRIES 3 48#define MAX_MSIX_QUEUES_FUSION 128 49 50/* Invader defines */ 51#define MPI2_TYPE_CUDA 0x2 52#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 53#define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 54#define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 55#define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 56#define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 57 58/* T10 PI defines */ 59#define MR_PROT_INFO_TYPE_CONTROLLER 0x8 60#define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 61#define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9 62#define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB 63#define MEGASAS_SCSI_ADDL_CDB_LEN 0x18 64#define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20 65#define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60 66 67#define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) 68#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 69 70/* 71 * Raid context flags 72 */ 73 74#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 75#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 76enum MR_RAID_FLAGS_IO_SUB_TYPE { 77 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 78 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 79}; 80 81/* 82 * Request descriptor types 83 */ 84#define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 85#define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1 86#define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 87#define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 88 89#define MEGASAS_FP_CMD_LEN 16 90#define MEGASAS_FUSION_IN_RESET 0 91#define THRESHOLD_REPLY_COUNT 50 92 93/* 94 * Raid Context structure which describes MegaRAID specific IO Parameters 95 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 96 */ 97 98struct RAID_CONTEXT { 99#if defined(__BIG_ENDIAN_BITFIELD) 100 u8 nseg:4; 101 u8 Type:4; 102#else 103 u8 Type:4; 104 u8 nseg:4; 105#endif 106 u8 resvd0; 107 __le16 timeoutValue; 108 u8 regLockFlags; 109 u8 resvd1; 110 __le16 VirtualDiskTgtId; 111 __le64 regLockRowLBA; 112 __le32 regLockLength; 113 __le16 nextLMId; 114 u8 exStatus; 115 u8 status; 116 u8 RAIDFlags; 117 u8 numSGE; 118 __le16 configSeqNum; 119 u8 spanArm; 120 u8 resvd2[3]; 121}; 122 123#define RAID_CTX_SPANARM_ARM_SHIFT (0) 124#define RAID_CTX_SPANARM_ARM_MASK (0x1f) 125 126#define RAID_CTX_SPANARM_SPAN_SHIFT (5) 127#define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 128 129/* 130 * define region lock types 131 */ 132enum REGION_TYPE { 133 REGION_TYPE_UNUSED = 0, 134 REGION_TYPE_SHARED_READ = 1, 135 REGION_TYPE_SHARED_WRITE = 2, 136 REGION_TYPE_EXCLUSIVE = 3, 137}; 138 139/* MPI2 defines */ 140#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 141#define MPI2_WHOINIT_HOST_DRIVER (0x04) 142#define MPI2_VERSION_MAJOR (0x02) 143#define MPI2_VERSION_MINOR (0x00) 144#define MPI2_VERSION_MAJOR_MASK (0xFF00) 145#define MPI2_VERSION_MAJOR_SHIFT (8) 146#define MPI2_VERSION_MINOR_MASK (0x00FF) 147#define MPI2_VERSION_MINOR_SHIFT (0) 148#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 149 MPI2_VERSION_MINOR) 150#define MPI2_HEADER_VERSION_UNIT (0x10) 151#define MPI2_HEADER_VERSION_DEV (0x00) 152#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 153#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 154#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 155#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 156#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 157 MPI2_HEADER_VERSION_DEV) 158#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 159#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 160#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 161#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 162#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 163#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 164#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 165#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 166#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 167#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 168#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 169#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 170#define MPI2_SCSIIO_CONTROL_READ (0x02000000) 171#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 172#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 173#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 174#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 175#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 176#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 177#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 178#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 179#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 180#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 181#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 182#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 183 184struct MPI25_IEEE_SGE_CHAIN64 { 185 __le64 Address; 186 __le32 Length; 187 __le16 Reserved1; 188 u8 NextChainOffset; 189 u8 Flags; 190}; 191 192struct MPI2_SGE_SIMPLE_UNION { 193 __le32 FlagsLength; 194 union { 195 __le32 Address32; 196 __le64 Address64; 197 } u; 198}; 199 200struct MPI2_SCSI_IO_CDB_EEDP32 { 201 u8 CDB[20]; /* 0x00 */ 202 __be32 PrimaryReferenceTag; /* 0x14 */ 203 __be16 PrimaryApplicationTag; /* 0x18 */ 204 __be16 PrimaryApplicationTagMask; /* 0x1A */ 205 __le32 TransferLength; /* 0x1C */ 206}; 207 208struct MPI2_SGE_CHAIN_UNION { 209 __le16 Length; 210 u8 NextChainOffset; 211 u8 Flags; 212 union { 213 __le32 Address32; 214 __le64 Address64; 215 } u; 216}; 217 218struct MPI2_IEEE_SGE_SIMPLE32 { 219 __le32 Address; 220 __le32 FlagsLength; 221}; 222 223struct MPI2_IEEE_SGE_CHAIN32 { 224 __le32 Address; 225 __le32 FlagsLength; 226}; 227 228struct MPI2_IEEE_SGE_SIMPLE64 { 229 __le64 Address; 230 __le32 Length; 231 __le16 Reserved1; 232 u8 Reserved2; 233 u8 Flags; 234}; 235 236struct MPI2_IEEE_SGE_CHAIN64 { 237 __le64 Address; 238 __le32 Length; 239 __le16 Reserved1; 240 u8 Reserved2; 241 u8 Flags; 242}; 243 244union MPI2_IEEE_SGE_SIMPLE_UNION { 245 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 246 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 247}; 248 249union MPI2_IEEE_SGE_CHAIN_UNION { 250 struct MPI2_IEEE_SGE_CHAIN32 Chain32; 251 struct MPI2_IEEE_SGE_CHAIN64 Chain64; 252}; 253 254union MPI2_SGE_IO_UNION { 255 struct MPI2_SGE_SIMPLE_UNION MpiSimple; 256 struct MPI2_SGE_CHAIN_UNION MpiChain; 257 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 258 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 259}; 260 261union MPI2_SCSI_IO_CDB_UNION { 262 u8 CDB32[32]; 263 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 264 struct MPI2_SGE_SIMPLE_UNION SGE; 265}; 266 267/* 268 * RAID SCSI IO Request Message 269 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 270 */ 271struct MPI2_RAID_SCSI_IO_REQUEST { 272 __le16 DevHandle; /* 0x00 */ 273 u8 ChainOffset; /* 0x02 */ 274 u8 Function; /* 0x03 */ 275 __le16 Reserved1; /* 0x04 */ 276 u8 Reserved2; /* 0x06 */ 277 u8 MsgFlags; /* 0x07 */ 278 u8 VP_ID; /* 0x08 */ 279 u8 VF_ID; /* 0x09 */ 280 __le16 Reserved3; /* 0x0A */ 281 __le32 SenseBufferLowAddress; /* 0x0C */ 282 __le16 SGLFlags; /* 0x10 */ 283 u8 SenseBufferLength; /* 0x12 */ 284 u8 Reserved4; /* 0x13 */ 285 u8 SGLOffset0; /* 0x14 */ 286 u8 SGLOffset1; /* 0x15 */ 287 u8 SGLOffset2; /* 0x16 */ 288 u8 SGLOffset3; /* 0x17 */ 289 __le32 SkipCount; /* 0x18 */ 290 __le32 DataLength; /* 0x1C */ 291 __le32 BidirectionalDataLength; /* 0x20 */ 292 __le16 IoFlags; /* 0x24 */ 293 __le16 EEDPFlags; /* 0x26 */ 294 __le32 EEDPBlockSize; /* 0x28 */ 295 __le32 SecondaryReferenceTag; /* 0x2C */ 296 __le16 SecondaryApplicationTag; /* 0x30 */ 297 __le16 ApplicationTagTranslationMask; /* 0x32 */ 298 u8 LUN[8]; /* 0x34 */ 299 __le32 Control; /* 0x3C */ 300 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 301 struct RAID_CONTEXT RaidContext; /* 0x60 */ 302 union MPI2_SGE_IO_UNION SGL; /* 0x80 */ 303}; 304 305/* 306 * MPT RAID MFA IO Descriptor. 307 */ 308struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR { 309 u32 RequestFlags:8; 310 u32 MessageAddress1:24; 311 u32 MessageAddress2; 312}; 313 314/* Default Request Descriptor */ 315struct MPI2_DEFAULT_REQUEST_DESCRIPTOR { 316 u8 RequestFlags; /* 0x00 */ 317 u8 MSIxIndex; /* 0x01 */ 318 __le16 SMID; /* 0x02 */ 319 __le16 LMID; /* 0x04 */ 320 __le16 DescriptorTypeDependent; /* 0x06 */ 321}; 322 323/* High Priority Request Descriptor */ 324struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 325 u8 RequestFlags; /* 0x00 */ 326 u8 MSIxIndex; /* 0x01 */ 327 __le16 SMID; /* 0x02 */ 328 __le16 LMID; /* 0x04 */ 329 __le16 Reserved1; /* 0x06 */ 330}; 331 332/* SCSI IO Request Descriptor */ 333struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 334 u8 RequestFlags; /* 0x00 */ 335 u8 MSIxIndex; /* 0x01 */ 336 __le16 SMID; /* 0x02 */ 337 __le16 LMID; /* 0x04 */ 338 __le16 DevHandle; /* 0x06 */ 339}; 340 341/* SCSI Target Request Descriptor */ 342struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 343 u8 RequestFlags; /* 0x00 */ 344 u8 MSIxIndex; /* 0x01 */ 345 __le16 SMID; /* 0x02 */ 346 __le16 LMID; /* 0x04 */ 347 __le16 IoIndex; /* 0x06 */ 348}; 349 350/* RAID Accelerator Request Descriptor */ 351struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 352 u8 RequestFlags; /* 0x00 */ 353 u8 MSIxIndex; /* 0x01 */ 354 __le16 SMID; /* 0x02 */ 355 __le16 LMID; /* 0x04 */ 356 __le16 Reserved; /* 0x06 */ 357}; 358 359/* union of Request Descriptors */ 360union MEGASAS_REQUEST_DESCRIPTOR_UNION { 361 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 362 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 363 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 364 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 365 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 366 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 367 union { 368 struct { 369 __le32 low; 370 __le32 high; 371 } u; 372 __le64 Words; 373 }; 374}; 375 376/* Default Reply Descriptor */ 377struct MPI2_DEFAULT_REPLY_DESCRIPTOR { 378 u8 ReplyFlags; /* 0x00 */ 379 u8 MSIxIndex; /* 0x01 */ 380 __le16 DescriptorTypeDependent1; /* 0x02 */ 381 __le32 DescriptorTypeDependent2; /* 0x04 */ 382}; 383 384/* Address Reply Descriptor */ 385struct MPI2_ADDRESS_REPLY_DESCRIPTOR { 386 u8 ReplyFlags; /* 0x00 */ 387 u8 MSIxIndex; /* 0x01 */ 388 __le16 SMID; /* 0x02 */ 389 __le32 ReplyFrameAddress; /* 0x04 */ 390}; 391 392/* SCSI IO Success Reply Descriptor */ 393struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 394 u8 ReplyFlags; /* 0x00 */ 395 u8 MSIxIndex; /* 0x01 */ 396 __le16 SMID; /* 0x02 */ 397 __le16 TaskTag; /* 0x04 */ 398 __le16 Reserved1; /* 0x06 */ 399}; 400 401/* TargetAssist Success Reply Descriptor */ 402struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 403 u8 ReplyFlags; /* 0x00 */ 404 u8 MSIxIndex; /* 0x01 */ 405 __le16 SMID; /* 0x02 */ 406 u8 SequenceNumber; /* 0x04 */ 407 u8 Reserved1; /* 0x05 */ 408 __le16 IoIndex; /* 0x06 */ 409}; 410 411/* Target Command Buffer Reply Descriptor */ 412struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 413 u8 ReplyFlags; /* 0x00 */ 414 u8 MSIxIndex; /* 0x01 */ 415 u8 VP_ID; /* 0x02 */ 416 u8 Flags; /* 0x03 */ 417 __le16 InitiatorDevHandle; /* 0x04 */ 418 __le16 IoIndex; /* 0x06 */ 419}; 420 421/* RAID Accelerator Success Reply Descriptor */ 422struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 423 u8 ReplyFlags; /* 0x00 */ 424 u8 MSIxIndex; /* 0x01 */ 425 __le16 SMID; /* 0x02 */ 426 __le32 Reserved; /* 0x04 */ 427}; 428 429/* union of Reply Descriptors */ 430union MPI2_REPLY_DESCRIPTORS_UNION { 431 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 432 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 433 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 434 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 435 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 436 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 437 RAIDAcceleratorSuccess; 438 __le64 Words; 439}; 440 441/* IOCInit Request message */ 442struct MPI2_IOC_INIT_REQUEST { 443 u8 WhoInit; /* 0x00 */ 444 u8 Reserved1; /* 0x01 */ 445 u8 ChainOffset; /* 0x02 */ 446 u8 Function; /* 0x03 */ 447 __le16 Reserved2; /* 0x04 */ 448 u8 Reserved3; /* 0x06 */ 449 u8 MsgFlags; /* 0x07 */ 450 u8 VP_ID; /* 0x08 */ 451 u8 VF_ID; /* 0x09 */ 452 __le16 Reserved4; /* 0x0A */ 453 __le16 MsgVersion; /* 0x0C */ 454 __le16 HeaderVersion; /* 0x0E */ 455 u32 Reserved5; /* 0x10 */ 456 __le16 Reserved6; /* 0x14 */ 457 u8 Reserved7; /* 0x16 */ 458 u8 HostMSIxVectors; /* 0x17 */ 459 __le16 Reserved8; /* 0x18 */ 460 __le16 SystemRequestFrameSize; /* 0x1A */ 461 __le16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 462 __le16 ReplyFreeQueueDepth; /* 0x1E */ 463 __le32 SenseBufferAddressHigh; /* 0x20 */ 464 __le32 SystemReplyAddressHigh; /* 0x24 */ 465 __le64 SystemRequestFrameBaseAddress; /* 0x28 */ 466 __le64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 467 __le64 ReplyFreeQueueAddress; /* 0x38 */ 468 __le64 TimeStamp; /* 0x40 */ 469}; 470 471/* mrpriv defines */ 472#define MR_PD_INVALID 0xFFFF 473#define MAX_SPAN_DEPTH 8 474#define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 475#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 476#define MAX_ROW_SIZE 32 477#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 478#define MAX_LOGICAL_DRIVES 64 479#define MAX_LOGICAL_DRIVES_EXT 256 480#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 481#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 482#define MAX_ARRAYS 128 483#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 484#define MAX_ARRAYS_EXT 256 485#define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT) 486#define MAX_PHYSICAL_DEVICES 256 487#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 488#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 489#define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/ 490#define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200 491#define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200 492 493struct MR_DEV_HANDLE_INFO { 494 __le16 curDevHdl; 495 u8 validHandles; 496 u8 reserved; 497 __le16 devHandle[2]; 498}; 499 500struct MR_ARRAY_INFO { 501 __le16 pd[MAX_RAIDMAP_ROW_SIZE]; 502}; 503 504struct MR_QUAD_ELEMENT { 505 __le64 logStart; 506 __le64 logEnd; 507 __le64 offsetInSpan; 508 __le32 diff; 509 __le32 reserved1; 510}; 511 512struct MR_SPAN_INFO { 513 __le32 noElements; 514 __le32 reserved1; 515 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 516}; 517 518struct MR_LD_SPAN { 519 __le64 startBlk; 520 __le64 numBlks; 521 __le16 arrayRef; 522 u8 spanRowSize; 523 u8 spanRowDataSize; 524 u8 reserved[4]; 525}; 526 527struct MR_SPAN_BLOCK_INFO { 528 __le64 num_rows; 529 struct MR_LD_SPAN span; 530 struct MR_SPAN_INFO block_span_info; 531}; 532 533struct MR_LD_RAID { 534 struct { 535#if defined(__BIG_ENDIAN_BITFIELD) 536 u32 reserved4:7; 537 u32 fpNonRWCapable:1; 538 u32 fpReadAcrossStripe:1; 539 u32 fpWriteAcrossStripe:1; 540 u32 fpReadCapable:1; 541 u32 fpWriteCapable:1; 542 u32 encryptionType:8; 543 u32 pdPiMode:4; 544 u32 ldPiMode:4; 545 u32 reserved5:3; 546 u32 fpCapable:1; 547#else 548 u32 fpCapable:1; 549 u32 reserved5:3; 550 u32 ldPiMode:4; 551 u32 pdPiMode:4; 552 u32 encryptionType:8; 553 u32 fpWriteCapable:1; 554 u32 fpReadCapable:1; 555 u32 fpWriteAcrossStripe:1; 556 u32 fpReadAcrossStripe:1; 557 u32 fpNonRWCapable:1; 558 u32 reserved4:7; 559#endif 560 } capability; 561 __le32 reserved6; 562 __le64 size; 563 u8 spanDepth; 564 u8 level; 565 u8 stripeShift; 566 u8 rowSize; 567 u8 rowDataSize; 568 u8 writeMode; 569 u8 PRL; 570 u8 SRL; 571 __le16 targetId; 572 u8 ldState; 573 u8 regTypeReqOnWrite; 574 u8 modFactor; 575 u8 regTypeReqOnRead; 576 __le16 seqNum; 577 578 struct { 579 u32 ldSyncRequired:1; 580 u32 reserved:31; 581 } flags; 582 583 u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */ 584 u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/ 585 u8 reserved3[0x80-0x2D]; /* 0x2D */ 586}; 587 588struct MR_LD_SPAN_MAP { 589 struct MR_LD_RAID ldRaid; 590 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 591 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 592}; 593 594struct MR_FW_RAID_MAP { 595 __le32 totalSize; 596 union { 597 struct { 598 __le32 maxLd; 599 __le32 maxSpanDepth; 600 __le32 maxRowSize; 601 __le32 maxPdCount; 602 __le32 maxArrays; 603 } validationInfo; 604 __le32 version[5]; 605 }; 606 607 __le32 ldCount; 608 __le32 Reserved1; 609 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+ 610 MAX_RAIDMAP_VIEWS]; 611 u8 fpPdIoTimeoutSec; 612 u8 reserved2[7]; 613 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 614 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 615 struct MR_LD_SPAN_MAP ldSpanMap[1]; 616}; 617 618struct IO_REQUEST_INFO { 619 u64 ldStartBlock; 620 u32 numBlocks; 621 u16 ldTgtId; 622 u8 isRead; 623 __le16 devHandle; 624 u64 pdBlock; 625 u8 fpOkForIo; 626 u8 IoforUnevenSpan; 627 u8 start_span; 628 u8 reserved; 629 u64 start_row; 630 u8 span_arm; /* span[7:5], arm[4:0] */ 631 u8 pd_after_lb; 632}; 633 634struct MR_LD_TARGET_SYNC { 635 u8 targetId; 636 u8 reserved; 637 __le16 seqNum; 638}; 639 640#define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 641#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 642#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 643#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 644#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 645#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 646#define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 647 648struct megasas_register_set; 649struct megasas_instance; 650 651union desc_word { 652 u64 word; 653 struct { 654 u32 low; 655 u32 high; 656 } u; 657}; 658 659struct megasas_cmd_fusion { 660 struct MPI2_RAID_SCSI_IO_REQUEST *io_request; 661 dma_addr_t io_request_phys_addr; 662 663 union MPI2_SGE_IO_UNION *sg_frame; 664 dma_addr_t sg_frame_phys_addr; 665 666 u8 *sense; 667 dma_addr_t sense_phys_addr; 668 669 struct list_head list; 670 struct scsi_cmnd *scmd; 671 struct megasas_instance *instance; 672 673 u8 retry_for_fw_reset; 674 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc; 675 676 /* 677 * Context for a MFI frame. 678 * Used to get the mfi cmd from list when a MFI cmd is completed 679 */ 680 u32 sync_cmd_idx; 681 u32 index; 682 u8 pd_r1_lb; 683}; 684 685struct LD_LOAD_BALANCE_INFO { 686 u8 loadBalanceFlag; 687 u8 reserved1; 688 atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES]; 689 u64 last_accessed_block[MAX_PHYSICAL_DEVICES]; 690}; 691 692/* SPAN_SET is info caclulated from span info from Raid map per LD */ 693typedef struct _LD_SPAN_SET { 694 u64 log_start_lba; 695 u64 log_end_lba; 696 u64 span_row_start; 697 u64 span_row_end; 698 u64 data_strip_start; 699 u64 data_strip_end; 700 u64 data_row_start; 701 u64 data_row_end; 702 u8 strip_offset[MAX_SPAN_DEPTH]; 703 u32 span_row_data_width; 704 u32 diff; 705 u32 reserved[2]; 706} LD_SPAN_SET, *PLD_SPAN_SET; 707 708typedef struct LOG_BLOCK_SPAN_INFO { 709 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 710} LD_SPAN_INFO, *PLD_SPAN_INFO; 711 712struct MR_FW_RAID_MAP_ALL { 713 struct MR_FW_RAID_MAP raidMap; 714 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 715} __attribute__ ((packed)); 716 717struct MR_DRV_RAID_MAP { 718 /* total size of this structure, including this field. 719 * This feild will be manupulated by driver for ext raid map, 720 * else pick the value from firmware raid map. 721 */ 722 __le32 totalSize; 723 724 union { 725 struct { 726 __le32 maxLd; 727 __le32 maxSpanDepth; 728 __le32 maxRowSize; 729 __le32 maxPdCount; 730 __le32 maxArrays; 731 } validationInfo; 732 __le32 version[5]; 733 }; 734 735 /* timeout value used by driver in FP IOs*/ 736 u8 fpPdIoTimeoutSec; 737 u8 reserved2[7]; 738 739 __le16 ldCount; 740 __le16 arCount; 741 __le16 spanCount; 742 __le16 reserve3; 743 744 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 745 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 746 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 747 struct MR_LD_SPAN_MAP ldSpanMap[1]; 748 749}; 750 751/* Driver raid map size is same as raid map ext 752 * MR_DRV_RAID_MAP_ALL is created to sync with old raid. 753 * And it is mainly for code re-use purpose. 754 */ 755struct MR_DRV_RAID_MAP_ALL { 756 757 struct MR_DRV_RAID_MAP raidMap; 758 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1]; 759} __packed; 760 761 762 763struct MR_FW_RAID_MAP_EXT { 764 /* Not usred in new map */ 765 u32 reserved; 766 767 union { 768 struct { 769 u32 maxLd; 770 u32 maxSpanDepth; 771 u32 maxRowSize; 772 u32 maxPdCount; 773 u32 maxArrays; 774 } validationInfo; 775 u32 version[5]; 776 }; 777 778 u8 fpPdIoTimeoutSec; 779 u8 reserved2[7]; 780 781 __le16 ldCount; 782 __le16 arCount; 783 __le16 spanCount; 784 __le16 reserve3; 785 786 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 787 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 788 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 789 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 790}; 791 792struct fusion_context { 793 struct megasas_cmd_fusion **cmd_list; 794 dma_addr_t req_frames_desc_phys; 795 u8 *req_frames_desc; 796 797 struct dma_pool *io_request_frames_pool; 798 dma_addr_t io_request_frames_phys; 799 u8 *io_request_frames; 800 801 struct dma_pool *sg_dma_pool; 802 struct dma_pool *sense_dma_pool; 803 804 dma_addr_t reply_frames_desc_phys; 805 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc; 806 struct dma_pool *reply_frames_desc_pool; 807 808 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION]; 809 810 u32 reply_q_depth; 811 u32 request_alloc_sz; 812 u32 reply_alloc_sz; 813 u32 io_frames_alloc_sz; 814 815 u16 max_sge_in_main_msg; 816 u16 max_sge_in_chain; 817 818 u8 chain_offset_io_request; 819 u8 chain_offset_mfi_pthru; 820 821 struct MR_FW_RAID_MAP_ALL *ld_map[2]; 822 dma_addr_t ld_map_phys[2]; 823 824 /*Non dma-able memory. Driver local copy.*/ 825 struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; 826 827 u32 max_map_sz; 828 u32 current_map_sz; 829 u32 drv_map_sz; 830 u32 drv_map_pages; 831 u8 fast_path_io; 832 struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT]; 833 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT]; 834}; 835 836union desc_value { 837 __le64 word; 838 struct { 839 __le32 low; 840 __le32 high; 841 } u; 842}; 843 844 845#endif /* _MEGARAID_SAS_FUSION_H_ */ 846