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18#ifndef SUN3_SCSI_H
19#define SUN3_SCSI_H
20
21
22
23struct sun3_dma_regs {
24 unsigned short dma_addr_hi;
25 unsigned short dma_addr_lo;
26 unsigned short dma_count_hi;
27 unsigned short dma_count_lo;
28 unsigned short udc_data;
29 unsigned short udc_addr;
30 unsigned short fifo_data;
31
32 unsigned short fifo_count;
33 unsigned short csr;
34 unsigned short bpack_hi;
35 unsigned short bpack_lo;
36 unsigned short ivect;
37 unsigned short fifo_count_hi;
38};
39
40
41struct sun3_udc_regs {
42 unsigned short rsel;
43 unsigned short addr_hi;
44 unsigned short addr_lo;
45 unsigned short count;
46 unsigned short mode_hi;
47 unsigned short mode_lo;
48};
49
50
51#define UDC_MODE 0x38
52#define UDC_CSR 0x2e
53#define UDC_CHN_HI 0x26
54#define UDC_CHN_LO 0x22
55#define UDC_CURA_HI 0x1a
56#define UDC_CURA_LO 0x0a
57#define UDC_CURB_HI 0x12
58#define UDC_CURB_LO 0x02
59#define UDC_MODE_HI 0x56
60#define UDC_MODE_LO 0x52
61#define UDC_COUNT 0x32
62
63
64#define UDC_RESET 0
65#define UDC_CHN_START 0xa0
66#define UDC_INT_ENABLE 0x32
67
68
69#define UDC_MODE_HIWORD 0x40
70#define UDC_MODE_LSEND 0xc2
71#define UDC_MODE_LRECV 0xd2
72
73
74#define UDC_RSEL_SEND 0x282
75#define UDC_RSEL_RECV 0x182
76
77
78#define CSR_DMA_ACTIVE 0x8000
79#define CSR_DMA_CONFLICT 0x4000
80#define CSR_DMA_BUSERR 0x2000
81
82#define CSR_FIFO_EMPTY 0x400
83#define CSR_SDB_INT 0x200
84#define CSR_DMA_INT 0x100
85
86#define CSR_LEFT 0xc0
87#define CSR_LEFT_3 0xc0
88#define CSR_LEFT_2 0x80
89#define CSR_LEFT_1 0x40
90#define CSR_PACK_ENABLE 0x20
91
92#define CSR_DMA_ENABLE 0x10
93
94#define CSR_SEND 0x8
95#define CSR_FIFO 0x2
96#define CSR_INTR 0x4
97#define CSR_SCSI 0x1
98
99#define VME_DATA24 0x3d00
100
101#endif
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