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9#include <linux/interrupt.h>
10#include <linux/irq.h>
11#include <linux/delay.h>
12#include <linux/mutex.h>
13#include <linux/device.h>
14#include <linux/kernel.h>
15#include <linux/spi/spi.h>
16#include <linux/slab.h>
17#include <linux/sysfs.h>
18#include <linux/list.h>
19#include <linux/module.h>
20
21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23#include <linux/iio/buffer.h>
24#include "meter.h"
25#include "ade7758.h"
26
27int ade7758_spi_write_reg_8(struct device *dev,
28 u8 reg_address,
29 u8 val)
30{
31 int ret;
32 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
33 struct ade7758_state *st = iio_priv(indio_dev);
34
35 mutex_lock(&st->buf_lock);
36 st->tx[0] = ADE7758_WRITE_REG(reg_address);
37 st->tx[1] = val;
38
39 ret = spi_write(st->us, st->tx, 2);
40 mutex_unlock(&st->buf_lock);
41
42 return ret;
43}
44
45static int ade7758_spi_write_reg_16(struct device *dev,
46 u8 reg_address,
47 u16 value)
48{
49 int ret;
50 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
51 struct ade7758_state *st = iio_priv(indio_dev);
52 struct spi_transfer xfers[] = {
53 {
54 .tx_buf = st->tx,
55 .bits_per_word = 8,
56 .len = 3,
57 }
58 };
59
60 mutex_lock(&st->buf_lock);
61 st->tx[0] = ADE7758_WRITE_REG(reg_address);
62 st->tx[1] = (value >> 8) & 0xFF;
63 st->tx[2] = value & 0xFF;
64
65 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
66 mutex_unlock(&st->buf_lock);
67
68 return ret;
69}
70
71static int ade7758_spi_write_reg_24(struct device *dev,
72 u8 reg_address,
73 u32 value)
74{
75 int ret;
76 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
77 struct ade7758_state *st = iio_priv(indio_dev);
78 struct spi_transfer xfers[] = {
79 {
80 .tx_buf = st->tx,
81 .bits_per_word = 8,
82 .len = 4,
83 }
84 };
85
86 mutex_lock(&st->buf_lock);
87 st->tx[0] = ADE7758_WRITE_REG(reg_address);
88 st->tx[1] = (value >> 16) & 0xFF;
89 st->tx[2] = (value >> 8) & 0xFF;
90 st->tx[3] = value & 0xFF;
91
92 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
93 mutex_unlock(&st->buf_lock);
94
95 return ret;
96}
97
98int ade7758_spi_read_reg_8(struct device *dev,
99 u8 reg_address,
100 u8 *val)
101{
102 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
103 struct ade7758_state *st = iio_priv(indio_dev);
104 int ret;
105 struct spi_transfer xfers[] = {
106 {
107 .tx_buf = st->tx,
108 .bits_per_word = 8,
109 .len = 1,
110 .delay_usecs = 4,
111 },
112 {
113 .tx_buf = &st->tx[1],
114 .rx_buf = st->rx,
115 .bits_per_word = 8,
116 .len = 1,
117 },
118 };
119
120 mutex_lock(&st->buf_lock);
121 st->tx[0] = ADE7758_READ_REG(reg_address);
122 st->tx[1] = 0;
123
124 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
125 if (ret) {
126 dev_err(&st->us->dev, "problem when reading 8 bit register 0x%02X",
127 reg_address);
128 goto error_ret;
129 }
130 *val = st->rx[0];
131
132error_ret:
133 mutex_unlock(&st->buf_lock);
134 return ret;
135}
136
137static int ade7758_spi_read_reg_16(struct device *dev,
138 u8 reg_address,
139 u16 *val)
140{
141 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
142 struct ade7758_state *st = iio_priv(indio_dev);
143 int ret;
144 struct spi_transfer xfers[] = {
145 {
146 .tx_buf = st->tx,
147 .bits_per_word = 8,
148 .len = 1,
149 .delay_usecs = 4,
150 },
151 {
152 .tx_buf = &st->tx[1],
153 .rx_buf = st->rx,
154 .bits_per_word = 8,
155 .len = 2,
156 },
157 };
158
159
160 mutex_lock(&st->buf_lock);
161 st->tx[0] = ADE7758_READ_REG(reg_address);
162 st->tx[1] = 0;
163 st->tx[2] = 0;
164
165 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
166 if (ret) {
167 dev_err(&st->us->dev, "problem when reading 16 bit register 0x%02X",
168 reg_address);
169 goto error_ret;
170 }
171
172 *val = (st->rx[0] << 8) | st->rx[1];
173
174error_ret:
175 mutex_unlock(&st->buf_lock);
176 return ret;
177}
178
179static int ade7758_spi_read_reg_24(struct device *dev,
180 u8 reg_address,
181 u32 *val)
182{
183 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
184 struct ade7758_state *st = iio_priv(indio_dev);
185 int ret;
186 struct spi_transfer xfers[] = {
187 {
188 .tx_buf = st->tx,
189 .bits_per_word = 8,
190 .len = 1,
191 .delay_usecs = 4,
192 },
193 {
194 .tx_buf = &st->tx[1],
195 .rx_buf = st->rx,
196 .bits_per_word = 8,
197 .len = 3,
198 },
199 };
200
201 mutex_lock(&st->buf_lock);
202 st->tx[0] = ADE7758_READ_REG(reg_address);
203 st->tx[1] = 0;
204 st->tx[2] = 0;
205 st->tx[3] = 0;
206
207 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
208 if (ret) {
209 dev_err(&st->us->dev, "problem when reading 24 bit register 0x%02X",
210 reg_address);
211 goto error_ret;
212 }
213 *val = (st->rx[0] << 16) | (st->rx[1] << 8) | st->rx[2];
214
215error_ret:
216 mutex_unlock(&st->buf_lock);
217 return ret;
218}
219
220static ssize_t ade7758_read_8bit(struct device *dev,
221 struct device_attribute *attr,
222 char *buf)
223{
224 int ret;
225 u8 val = 0;
226 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
227
228 ret = ade7758_spi_read_reg_8(dev, this_attr->address, &val);
229 if (ret)
230 return ret;
231
232 return sprintf(buf, "%u\n", val);
233}
234
235static ssize_t ade7758_read_16bit(struct device *dev,
236 struct device_attribute *attr,
237 char *buf)
238{
239 int ret;
240 u16 val = 0;
241 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
242
243 ret = ade7758_spi_read_reg_16(dev, this_attr->address, &val);
244 if (ret)
245 return ret;
246
247 return sprintf(buf, "%u\n", val);
248}
249
250static ssize_t ade7758_read_24bit(struct device *dev,
251 struct device_attribute *attr,
252 char *buf)
253{
254 int ret;
255 u32 val = 0;
256 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
257
258 ret = ade7758_spi_read_reg_24(dev, this_attr->address, &val);
259 if (ret)
260 return ret;
261
262 return sprintf(buf, "%u\n", val & 0xFFFFFF);
263}
264
265static ssize_t ade7758_write_8bit(struct device *dev,
266 struct device_attribute *attr,
267 const char *buf,
268 size_t len)
269{
270 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
271 int ret;
272 u8 val;
273
274 ret = kstrtou8(buf, 10, &val);
275 if (ret)
276 goto error_ret;
277 ret = ade7758_spi_write_reg_8(dev, this_attr->address, val);
278
279error_ret:
280 return ret ? ret : len;
281}
282
283static ssize_t ade7758_write_16bit(struct device *dev,
284 struct device_attribute *attr,
285 const char *buf,
286 size_t len)
287{
288 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
289 int ret;
290 u16 val;
291
292 ret = kstrtou16(buf, 10, &val);
293 if (ret)
294 goto error_ret;
295 ret = ade7758_spi_write_reg_16(dev, this_attr->address, val);
296
297error_ret:
298 return ret ? ret : len;
299}
300
301static int ade7758_reset(struct device *dev)
302{
303 int ret;
304 u8 val;
305
306 ret = ade7758_spi_read_reg_8(dev, ADE7758_OPMODE, &val);
307 if (ret < 0) {
308 dev_err(dev, "Failed to read opmode reg\n");
309 return ret;
310 }
311 val |= 1 << 6;
312 ret = ade7758_spi_write_reg_8(dev, ADE7758_OPMODE, val);
313 if (ret < 0)
314 dev_err(dev, "Failed to write opmode reg\n");
315 return ret;
316}
317
318static IIO_DEV_ATTR_VPEAK(S_IWUSR | S_IRUGO,
319 ade7758_read_8bit,
320 ade7758_write_8bit,
321 ADE7758_VPEAK);
322static IIO_DEV_ATTR_IPEAK(S_IWUSR | S_IRUGO,
323 ade7758_read_8bit,
324 ade7758_write_8bit,
325 ADE7758_VPEAK);
326static IIO_DEV_ATTR_APHCAL(S_IWUSR | S_IRUGO,
327 ade7758_read_8bit,
328 ade7758_write_8bit,
329 ADE7758_APHCAL);
330static IIO_DEV_ATTR_BPHCAL(S_IWUSR | S_IRUGO,
331 ade7758_read_8bit,
332 ade7758_write_8bit,
333 ADE7758_BPHCAL);
334static IIO_DEV_ATTR_CPHCAL(S_IWUSR | S_IRUGO,
335 ade7758_read_8bit,
336 ade7758_write_8bit,
337 ADE7758_CPHCAL);
338static IIO_DEV_ATTR_WDIV(S_IWUSR | S_IRUGO,
339 ade7758_read_8bit,
340 ade7758_write_8bit,
341 ADE7758_WDIV);
342static IIO_DEV_ATTR_VADIV(S_IWUSR | S_IRUGO,
343 ade7758_read_8bit,
344 ade7758_write_8bit,
345 ADE7758_VADIV);
346static IIO_DEV_ATTR_AIRMS(S_IRUGO,
347 ade7758_read_24bit,
348 NULL,
349 ADE7758_AIRMS);
350static IIO_DEV_ATTR_BIRMS(S_IRUGO,
351 ade7758_read_24bit,
352 NULL,
353 ADE7758_BIRMS);
354static IIO_DEV_ATTR_CIRMS(S_IRUGO,
355 ade7758_read_24bit,
356 NULL,
357 ADE7758_CIRMS);
358static IIO_DEV_ATTR_AVRMS(S_IRUGO,
359 ade7758_read_24bit,
360 NULL,
361 ADE7758_AVRMS);
362static IIO_DEV_ATTR_BVRMS(S_IRUGO,
363 ade7758_read_24bit,
364 NULL,
365 ADE7758_BVRMS);
366static IIO_DEV_ATTR_CVRMS(S_IRUGO,
367 ade7758_read_24bit,
368 NULL,
369 ADE7758_CVRMS);
370static IIO_DEV_ATTR_AIRMSOS(S_IWUSR | S_IRUGO,
371 ade7758_read_16bit,
372 ade7758_write_16bit,
373 ADE7758_AIRMSOS);
374static IIO_DEV_ATTR_BIRMSOS(S_IWUSR | S_IRUGO,
375 ade7758_read_16bit,
376 ade7758_write_16bit,
377 ADE7758_BIRMSOS);
378static IIO_DEV_ATTR_CIRMSOS(S_IWUSR | S_IRUGO,
379 ade7758_read_16bit,
380 ade7758_write_16bit,
381 ADE7758_CIRMSOS);
382static IIO_DEV_ATTR_AVRMSOS(S_IWUSR | S_IRUGO,
383 ade7758_read_16bit,
384 ade7758_write_16bit,
385 ADE7758_AVRMSOS);
386static IIO_DEV_ATTR_BVRMSOS(S_IWUSR | S_IRUGO,
387 ade7758_read_16bit,
388 ade7758_write_16bit,
389 ADE7758_BVRMSOS);
390static IIO_DEV_ATTR_CVRMSOS(S_IWUSR | S_IRUGO,
391 ade7758_read_16bit,
392 ade7758_write_16bit,
393 ADE7758_CVRMSOS);
394static IIO_DEV_ATTR_AIGAIN(S_IWUSR | S_IRUGO,
395 ade7758_read_16bit,
396 ade7758_write_16bit,
397 ADE7758_AIGAIN);
398static IIO_DEV_ATTR_BIGAIN(S_IWUSR | S_IRUGO,
399 ade7758_read_16bit,
400 ade7758_write_16bit,
401 ADE7758_BIGAIN);
402static IIO_DEV_ATTR_CIGAIN(S_IWUSR | S_IRUGO,
403 ade7758_read_16bit,
404 ade7758_write_16bit,
405 ADE7758_CIGAIN);
406static IIO_DEV_ATTR_AVRMSGAIN(S_IWUSR | S_IRUGO,
407 ade7758_read_16bit,
408 ade7758_write_16bit,
409 ADE7758_AVRMSGAIN);
410static IIO_DEV_ATTR_BVRMSGAIN(S_IWUSR | S_IRUGO,
411 ade7758_read_16bit,
412 ade7758_write_16bit,
413 ADE7758_BVRMSGAIN);
414static IIO_DEV_ATTR_CVRMSGAIN(S_IWUSR | S_IRUGO,
415 ade7758_read_16bit,
416 ade7758_write_16bit,
417 ADE7758_CVRMSGAIN);
418
419int ade7758_set_irq(struct device *dev, bool enable)
420{
421 int ret;
422 u32 irqen;
423
424 ret = ade7758_spi_read_reg_24(dev, ADE7758_MASK, &irqen);
425 if (ret)
426 goto error_ret;
427
428 if (enable)
429 irqen |= 1 << 16;
430
431 else
432 irqen &= ~(1 << 16);
433
434 ret = ade7758_spi_write_reg_24(dev, ADE7758_MASK, irqen);
435 if (ret)
436 goto error_ret;
437
438error_ret:
439 return ret;
440}
441
442
443static int ade7758_stop_device(struct device *dev)
444{
445 int ret;
446 u8 val;
447
448 ret = ade7758_spi_read_reg_8(dev, ADE7758_OPMODE, &val);
449 if (ret < 0) {
450 dev_err(dev, "Failed to read opmode reg\n");
451 return ret;
452 }
453 val |= 7 << 3;
454 ret = ade7758_spi_write_reg_8(dev, ADE7758_OPMODE, val);
455 if (ret < 0)
456 dev_err(dev, "Failed to write opmode reg\n");
457 return ret;
458}
459
460static int ade7758_initial_setup(struct iio_dev *indio_dev)
461{
462 struct ade7758_state *st = iio_priv(indio_dev);
463 struct device *dev = &indio_dev->dev;
464 int ret;
465
466
467 st->us->mode = SPI_MODE_1;
468 spi_setup(st->us);
469
470
471 ret = ade7758_set_irq(dev, false);
472 if (ret) {
473 dev_err(dev, "disable irq failed");
474 goto err_ret;
475 }
476
477 ade7758_reset(dev);
478 msleep(ADE7758_STARTUP_DELAY);
479
480err_ret:
481 return ret;
482}
483
484static ssize_t ade7758_read_frequency(struct device *dev,
485 struct device_attribute *attr,
486 char *buf)
487{
488 int ret;
489 u8 t;
490 int sps;
491
492 ret = ade7758_spi_read_reg_8(dev,
493 ADE7758_WAVMODE,
494 &t);
495 if (ret)
496 return ret;
497
498 t = (t >> 5) & 0x3;
499 sps = 26040 / (1 << t);
500
501 return sprintf(buf, "%d SPS\n", sps);
502}
503
504static ssize_t ade7758_write_frequency(struct device *dev,
505 struct device_attribute *attr,
506 const char *buf,
507 size_t len)
508{
509 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
510 u16 val;
511 int ret;
512 u8 reg, t;
513
514 ret = kstrtou16(buf, 10, &val);
515 if (ret)
516 return ret;
517
518 mutex_lock(&indio_dev->mlock);
519
520 switch (val) {
521 case 26040:
522 t = 0;
523 break;
524 case 13020:
525 t = 1;
526 break;
527 case 6510:
528 t = 2;
529 break;
530 case 3255:
531 t = 3;
532 break;
533 default:
534 ret = -EINVAL;
535 goto out;
536 }
537
538 ret = ade7758_spi_read_reg_8(dev,
539 ADE7758_WAVMODE,
540 ®);
541 if (ret)
542 goto out;
543
544 reg &= ~(5 << 3);
545 reg |= t << 5;
546
547 ret = ade7758_spi_write_reg_8(dev,
548 ADE7758_WAVMODE,
549 reg);
550
551out:
552 mutex_unlock(&indio_dev->mlock);
553
554 return ret ? ret : len;
555}
556
557static IIO_DEV_ATTR_TEMP_RAW(ade7758_read_8bit);
558static IIO_CONST_ATTR(in_temp_offset, "129 C");
559static IIO_CONST_ATTR(in_temp_scale, "4 C");
560
561static IIO_DEV_ATTR_AWATTHR(ade7758_read_16bit,
562 ADE7758_AWATTHR);
563static IIO_DEV_ATTR_BWATTHR(ade7758_read_16bit,
564 ADE7758_BWATTHR);
565static IIO_DEV_ATTR_CWATTHR(ade7758_read_16bit,
566 ADE7758_CWATTHR);
567static IIO_DEV_ATTR_AVARHR(ade7758_read_16bit,
568 ADE7758_AVARHR);
569static IIO_DEV_ATTR_BVARHR(ade7758_read_16bit,
570 ADE7758_BVARHR);
571static IIO_DEV_ATTR_CVARHR(ade7758_read_16bit,
572 ADE7758_CVARHR);
573static IIO_DEV_ATTR_AVAHR(ade7758_read_16bit,
574 ADE7758_AVAHR);
575static IIO_DEV_ATTR_BVAHR(ade7758_read_16bit,
576 ADE7758_BVAHR);
577static IIO_DEV_ATTR_CVAHR(ade7758_read_16bit,
578 ADE7758_CVAHR);
579
580static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
581 ade7758_read_frequency,
582 ade7758_write_frequency);
583
584static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("26040 13020 6510 3255");
585
586static struct attribute *ade7758_attributes[] = {
587 &iio_dev_attr_in_temp_raw.dev_attr.attr,
588 &iio_const_attr_in_temp_offset.dev_attr.attr,
589 &iio_const_attr_in_temp_scale.dev_attr.attr,
590 &iio_dev_attr_sampling_frequency.dev_attr.attr,
591 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
592 &iio_dev_attr_awatthr.dev_attr.attr,
593 &iio_dev_attr_bwatthr.dev_attr.attr,
594 &iio_dev_attr_cwatthr.dev_attr.attr,
595 &iio_dev_attr_avarhr.dev_attr.attr,
596 &iio_dev_attr_bvarhr.dev_attr.attr,
597 &iio_dev_attr_cvarhr.dev_attr.attr,
598 &iio_dev_attr_avahr.dev_attr.attr,
599 &iio_dev_attr_bvahr.dev_attr.attr,
600 &iio_dev_attr_cvahr.dev_attr.attr,
601 &iio_dev_attr_vpeak.dev_attr.attr,
602 &iio_dev_attr_ipeak.dev_attr.attr,
603 &iio_dev_attr_aphcal.dev_attr.attr,
604 &iio_dev_attr_bphcal.dev_attr.attr,
605 &iio_dev_attr_cphcal.dev_attr.attr,
606 &iio_dev_attr_wdiv.dev_attr.attr,
607 &iio_dev_attr_vadiv.dev_attr.attr,
608 &iio_dev_attr_airms.dev_attr.attr,
609 &iio_dev_attr_birms.dev_attr.attr,
610 &iio_dev_attr_cirms.dev_attr.attr,
611 &iio_dev_attr_avrms.dev_attr.attr,
612 &iio_dev_attr_bvrms.dev_attr.attr,
613 &iio_dev_attr_cvrms.dev_attr.attr,
614 &iio_dev_attr_aigain.dev_attr.attr,
615 &iio_dev_attr_bigain.dev_attr.attr,
616 &iio_dev_attr_cigain.dev_attr.attr,
617 &iio_dev_attr_avrmsgain.dev_attr.attr,
618 &iio_dev_attr_bvrmsgain.dev_attr.attr,
619 &iio_dev_attr_cvrmsgain.dev_attr.attr,
620 &iio_dev_attr_airmsos.dev_attr.attr,
621 &iio_dev_attr_birmsos.dev_attr.attr,
622 &iio_dev_attr_cirmsos.dev_attr.attr,
623 &iio_dev_attr_avrmsos.dev_attr.attr,
624 &iio_dev_attr_bvrmsos.dev_attr.attr,
625 &iio_dev_attr_cvrmsos.dev_attr.attr,
626 NULL,
627};
628
629static const struct attribute_group ade7758_attribute_group = {
630 .attrs = ade7758_attributes,
631};
632
633static const struct iio_chan_spec ade7758_channels[] = {
634 {
635 .type = IIO_VOLTAGE,
636 .indexed = 1,
637 .channel = 0,
638 .address = AD7758_WT(AD7758_PHASE_A, AD7758_VOLTAGE),
639 .scan_index = 0,
640 .scan_type = {
641 .sign = 's',
642 .realbits = 24,
643 .storagebits = 32,
644 },
645 }, {
646 .type = IIO_CURRENT,
647 .indexed = 1,
648 .channel = 0,
649 .address = AD7758_WT(AD7758_PHASE_A, AD7758_CURRENT),
650 .scan_index = 1,
651 .scan_type = {
652 .sign = 's',
653 .realbits = 24,
654 .storagebits = 32,
655 },
656 }, {
657 .type = IIO_POWER,
658 .indexed = 1,
659 .channel = 0,
660 .extend_name = "apparent",
661 .address = AD7758_WT(AD7758_PHASE_A, AD7758_APP_PWR),
662 .scan_index = 2,
663 .scan_type = {
664 .sign = 's',
665 .realbits = 24,
666 .storagebits = 32,
667 },
668 }, {
669 .type = IIO_POWER,
670 .indexed = 1,
671 .channel = 0,
672 .extend_name = "active",
673 .address = AD7758_WT(AD7758_PHASE_A, AD7758_ACT_PWR),
674 .scan_index = 3,
675 .scan_type = {
676 .sign = 's',
677 .realbits = 24,
678 .storagebits = 32,
679 },
680 }, {
681 .type = IIO_POWER,
682 .indexed = 1,
683 .channel = 0,
684 .extend_name = "reactive",
685 .address = AD7758_WT(AD7758_PHASE_A, AD7758_REACT_PWR),
686 .scan_index = 4,
687 .scan_type = {
688 .sign = 's',
689 .realbits = 24,
690 .storagebits = 32,
691 },
692 }, {
693 .type = IIO_VOLTAGE,
694 .indexed = 1,
695 .channel = 1,
696 .address = AD7758_WT(AD7758_PHASE_B, AD7758_VOLTAGE),
697 .scan_index = 5,
698 .scan_type = {
699 .sign = 's',
700 .realbits = 24,
701 .storagebits = 32,
702 },
703 }, {
704 .type = IIO_CURRENT,
705 .indexed = 1,
706 .channel = 1,
707 .address = AD7758_WT(AD7758_PHASE_B, AD7758_CURRENT),
708 .scan_index = 6,
709 .scan_type = {
710 .sign = 's',
711 .realbits = 24,
712 .storagebits = 32,
713 },
714 }, {
715 .type = IIO_POWER,
716 .indexed = 1,
717 .channel = 1,
718 .extend_name = "apparent",
719 .address = AD7758_WT(AD7758_PHASE_B, AD7758_APP_PWR),
720 .scan_index = 7,
721 .scan_type = {
722 .sign = 's',
723 .realbits = 24,
724 .storagebits = 32,
725 },
726 }, {
727 .type = IIO_POWER,
728 .indexed = 1,
729 .channel = 1,
730 .extend_name = "active",
731 .address = AD7758_WT(AD7758_PHASE_B, AD7758_ACT_PWR),
732 .scan_index = 8,
733 .scan_type = {
734 .sign = 's',
735 .realbits = 24,
736 .storagebits = 32,
737 },
738 }, {
739 .type = IIO_POWER,
740 .indexed = 1,
741 .channel = 1,
742 .extend_name = "reactive",
743 .address = AD7758_WT(AD7758_PHASE_B, AD7758_REACT_PWR),
744 .scan_index = 9,
745 .scan_type = {
746 .sign = 's',
747 .realbits = 24,
748 .storagebits = 32,
749 },
750 }, {
751 .type = IIO_VOLTAGE,
752 .indexed = 1,
753 .channel = 2,
754 .address = AD7758_WT(AD7758_PHASE_C, AD7758_VOLTAGE),
755 .scan_index = 10,
756 .scan_type = {
757 .sign = 's',
758 .realbits = 24,
759 .storagebits = 32,
760 },
761 }, {
762 .type = IIO_CURRENT,
763 .indexed = 1,
764 .channel = 2,
765 .address = AD7758_WT(AD7758_PHASE_C, AD7758_CURRENT),
766 .scan_index = 11,
767 .scan_type = {
768 .sign = 's',
769 .realbits = 24,
770 .storagebits = 32,
771 },
772 }, {
773 .type = IIO_POWER,
774 .indexed = 1,
775 .channel = 2,
776 .extend_name = "apparent",
777 .address = AD7758_WT(AD7758_PHASE_C, AD7758_APP_PWR),
778 .scan_index = 12,
779 .scan_type = {
780 .sign = 's',
781 .realbits = 24,
782 .storagebits = 32,
783 },
784 }, {
785 .type = IIO_POWER,
786 .indexed = 1,
787 .channel = 2,
788 .extend_name = "active",
789 .address = AD7758_WT(AD7758_PHASE_C, AD7758_ACT_PWR),
790 .scan_index = 13,
791 .scan_type = {
792 .sign = 's',
793 .realbits = 24,
794 .storagebits = 32,
795 },
796 }, {
797 .type = IIO_POWER,
798 .indexed = 1,
799 .channel = 2,
800 .extend_name = "reactive",
801 .address = AD7758_WT(AD7758_PHASE_C, AD7758_REACT_PWR),
802 .scan_index = 14,
803 .scan_type = {
804 .sign = 's',
805 .realbits = 24,
806 .storagebits = 32,
807 },
808 },
809 IIO_CHAN_SOFT_TIMESTAMP(15),
810};
811
812static const struct iio_info ade7758_info = {
813 .attrs = &ade7758_attribute_group,
814 .driver_module = THIS_MODULE,
815};
816
817static int ade7758_probe(struct spi_device *spi)
818{
819 int ret;
820 struct ade7758_state *st;
821 struct iio_dev *indio_dev;
822
823 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
824 if (!indio_dev)
825 return -ENOMEM;
826
827 st = iio_priv(indio_dev);
828
829 spi_set_drvdata(spi, indio_dev);
830
831
832 st->rx = kcalloc(ADE7758_MAX_RX, sizeof(*st->rx), GFP_KERNEL);
833 if (!st->rx)
834 return -ENOMEM;
835 st->tx = kcalloc(ADE7758_MAX_TX, sizeof(*st->tx), GFP_KERNEL);
836 if (!st->tx) {
837 ret = -ENOMEM;
838 goto error_free_rx;
839 }
840 st->us = spi;
841 mutex_init(&st->buf_lock);
842
843 indio_dev->name = spi->dev.driver->name;
844 indio_dev->dev.parent = &spi->dev;
845 indio_dev->info = &ade7758_info;
846 indio_dev->modes = INDIO_DIRECT_MODE;
847 indio_dev->channels = ade7758_channels;
848 indio_dev->num_channels = ARRAY_SIZE(ade7758_channels);
849
850 ret = ade7758_configure_ring(indio_dev);
851 if (ret)
852 goto error_free_tx;
853
854
855 ret = ade7758_initial_setup(indio_dev);
856 if (ret)
857 goto error_unreg_ring_funcs;
858
859 if (spi->irq) {
860 ret = ade7758_probe_trigger(indio_dev);
861 if (ret)
862 goto error_unreg_ring_funcs;
863 }
864
865 ret = iio_device_register(indio_dev);
866 if (ret)
867 goto error_remove_trigger;
868
869 return 0;
870
871error_remove_trigger:
872 if (spi->irq)
873 ade7758_remove_trigger(indio_dev);
874error_unreg_ring_funcs:
875 ade7758_unconfigure_ring(indio_dev);
876error_free_tx:
877 kfree(st->tx);
878error_free_rx:
879 kfree(st->rx);
880 return ret;
881}
882
883static int ade7758_remove(struct spi_device *spi)
884{
885 struct iio_dev *indio_dev = spi_get_drvdata(spi);
886 struct ade7758_state *st = iio_priv(indio_dev);
887
888 iio_device_unregister(indio_dev);
889 ade7758_stop_device(&indio_dev->dev);
890 ade7758_remove_trigger(indio_dev);
891 ade7758_unconfigure_ring(indio_dev);
892 kfree(st->tx);
893 kfree(st->rx);
894
895 return 0;
896}
897
898static const struct spi_device_id ade7758_id[] = {
899 {"ade7758", 0},
900 {}
901};
902MODULE_DEVICE_TABLE(spi, ade7758_id);
903
904static struct spi_driver ade7758_driver = {
905 .driver = {
906 .name = "ade7758",
907 .owner = THIS_MODULE,
908 },
909 .probe = ade7758_probe,
910 .remove = ade7758_remove,
911 .id_table = ade7758_id,
912};
913module_spi_driver(ade7758_driver);
914
915MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
916MODULE_DESCRIPTION("Analog Devices ADE7758 Polyphase Multifunction Energy Metering IC Driver");
917MODULE_LICENSE("GPL v2");
918
