1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/slab.h>
34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/io.h>
37#include <linux/platform_device.h>
38#include <linux/init.h>
39#include <linux/sysrq.h>
40#include <linux/console.h>
41#include <linux/tty.h>
42#include <linux/tty_flip.h>
43#include <linux/serial_core.h>
44#include <linux/serial.h>
45#include <linux/serial_s3c.h>
46#include <linux/delay.h>
47#include <linux/clk.h>
48#include <linux/cpufreq.h>
49#include <linux/of.h>
50
51#include <asm/irq.h>
52
53#include "samsung.h"
54
55#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
56 !defined(MODULE)
57
58extern void printascii(const char *);
59
60__printf(1, 2)
61static void dbg(const char *fmt, ...)
62{
63 va_list va;
64 char buff[256];
65
66 va_start(va, fmt);
67 vscnprintf(buff, sizeof(buff), fmt, va);
68 va_end(va);
69
70 printascii(buff);
71}
72
73#else
74#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
75#endif
76
77
78
79#define S3C24XX_SERIAL_NAME "ttySAC"
80#define S3C24XX_SERIAL_MAJOR 204
81#define S3C24XX_SERIAL_MINOR 64
82
83#define S3C24XX_TX_PIO 1
84#define S3C24XX_TX_DMA 2
85#define S3C24XX_RX_PIO 1
86#define S3C24XX_RX_DMA 2
87
88
89#define tx_enabled(port) ((port)->unused[0])
90#define rx_enabled(port) ((port)->unused[1])
91
92
93#define RXSTAT_DUMMY_READ (0x10000000)
94
95static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
96{
97 return container_of(port, struct s3c24xx_uart_port, port);
98}
99
100
101
102static inline const char *s3c24xx_serial_portname(struct uart_port *port)
103{
104 return to_platform_device(port->dev)->name;
105}
106
107static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
108{
109 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
110}
111
112
113
114
115
116
117static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
118{
119 return to_ourport(port)->info->type == PORT_S3C6400;
120}
121
122static void s3c24xx_serial_rx_enable(struct uart_port *port)
123{
124 unsigned long flags;
125 unsigned int ucon, ufcon;
126 int count = 10000;
127
128 spin_lock_irqsave(&port->lock, flags);
129
130 while (--count && !s3c24xx_serial_txempty_nofifo(port))
131 udelay(100);
132
133 ufcon = rd_regl(port, S3C2410_UFCON);
134 ufcon |= S3C2410_UFCON_RESETRX;
135 wr_regl(port, S3C2410_UFCON, ufcon);
136
137 ucon = rd_regl(port, S3C2410_UCON);
138 ucon |= S3C2410_UCON_RXIRQMODE;
139 wr_regl(port, S3C2410_UCON, ucon);
140
141 rx_enabled(port) = 1;
142 spin_unlock_irqrestore(&port->lock, flags);
143}
144
145static void s3c24xx_serial_rx_disable(struct uart_port *port)
146{
147 unsigned long flags;
148 unsigned int ucon;
149
150 spin_lock_irqsave(&port->lock, flags);
151
152 ucon = rd_regl(port, S3C2410_UCON);
153 ucon &= ~S3C2410_UCON_RXIRQMODE;
154 wr_regl(port, S3C2410_UCON, ucon);
155
156 rx_enabled(port) = 0;
157 spin_unlock_irqrestore(&port->lock, flags);
158}
159
160static void s3c24xx_serial_stop_tx(struct uart_port *port)
161{
162 struct s3c24xx_uart_port *ourport = to_ourport(port);
163 struct s3c24xx_uart_dma *dma = ourport->dma;
164 struct circ_buf *xmit = &port->state->xmit;
165 struct dma_tx_state state;
166 int count;
167
168 if (!tx_enabled(port))
169 return;
170
171 if (s3c24xx_serial_has_interrupt_mask(port))
172 __set_bit(S3C64XX_UINTM_TXD,
173 portaddrl(port, S3C64XX_UINTM));
174 else
175 disable_irq_nosync(ourport->tx_irq);
176
177 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
178 dmaengine_pause(dma->tx_chan);
179 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
180 dmaengine_terminate_all(dma->tx_chan);
181 dma_sync_single_for_cpu(ourport->port.dev,
182 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
183 async_tx_ack(dma->tx_desc);
184 count = dma->tx_bytes_requested - state.residue;
185 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
186 port->icount.tx += count;
187 }
188
189 tx_enabled(port) = 0;
190 ourport->tx_in_progress = 0;
191
192 if (port->flags & UPF_CONS_FLOW)
193 s3c24xx_serial_rx_enable(port);
194
195 ourport->tx_mode = 0;
196}
197
198static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
199
200static void s3c24xx_serial_tx_dma_complete(void *args)
201{
202 struct s3c24xx_uart_port *ourport = args;
203 struct uart_port *port = &ourport->port;
204 struct circ_buf *xmit = &port->state->xmit;
205 struct s3c24xx_uart_dma *dma = ourport->dma;
206 struct dma_tx_state state;
207 unsigned long flags;
208 int count;
209
210
211 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
212 count = dma->tx_bytes_requested - state.residue;
213 async_tx_ack(dma->tx_desc);
214
215 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
216 dma->tx_size, DMA_TO_DEVICE);
217
218 spin_lock_irqsave(&port->lock, flags);
219
220 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
221 port->icount.tx += count;
222 ourport->tx_in_progress = 0;
223
224 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
225 uart_write_wakeup(port);
226
227 s3c24xx_serial_start_next_tx(ourport);
228 spin_unlock_irqrestore(&port->lock, flags);
229}
230
231static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
232{
233 struct uart_port *port = &ourport->port;
234 u32 ucon;
235
236
237 if (s3c24xx_serial_has_interrupt_mask(port))
238 __set_bit(S3C64XX_UINTM_TXD,
239 portaddrl(port, S3C64XX_UINTM));
240 else
241 disable_irq_nosync(ourport->tx_irq);
242
243
244 ucon = rd_regl(port, S3C2410_UCON);
245 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
246 ucon |= (dma_get_cache_alignment() >= 16) ?
247 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
248 ucon |= S3C64XX_UCON_TXMODE_DMA;
249 wr_regl(port, S3C2410_UCON, ucon);
250
251 ourport->tx_mode = S3C24XX_TX_DMA;
252}
253
254static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
255{
256 struct uart_port *port = &ourport->port;
257 u32 ucon, ufcon;
258
259
260 ourport->tx_in_progress = S3C24XX_TX_PIO;
261 ufcon = rd_regl(port, S3C2410_UFCON);
262 wr_regl(port, S3C2410_UFCON, ufcon);
263
264
265 ucon = rd_regl(port, S3C2410_UCON);
266 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
267 ucon |= S3C64XX_UCON_TXMODE_CPU;
268 wr_regl(port, S3C2410_UCON, ucon);
269
270
271 if (s3c24xx_serial_has_interrupt_mask(port))
272 __clear_bit(S3C64XX_UINTM_TXD,
273 portaddrl(port, S3C64XX_UINTM));
274 else
275 enable_irq(ourport->tx_irq);
276
277 ourport->tx_mode = S3C24XX_TX_PIO;
278}
279
280static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
281{
282 if (ourport->tx_mode != S3C24XX_TX_PIO)
283 enable_tx_pio(ourport);
284}
285
286static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
287 unsigned int count)
288{
289 struct uart_port *port = &ourport->port;
290 struct circ_buf *xmit = &port->state->xmit;
291 struct s3c24xx_uart_dma *dma = ourport->dma;
292
293
294 if (ourport->tx_mode != S3C24XX_TX_DMA)
295 enable_tx_dma(ourport);
296
297 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
298 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
299
300 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
301 dma->tx_size, DMA_TO_DEVICE);
302
303 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
304 dma->tx_transfer_addr, dma->tx_size,
305 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
306 if (!dma->tx_desc) {
307 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
308 return -EIO;
309 }
310
311 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
312 dma->tx_desc->callback_param = ourport;
313 dma->tx_bytes_requested = dma->tx_size;
314
315 ourport->tx_in_progress = S3C24XX_TX_DMA;
316 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
317 dma_async_issue_pending(dma->tx_chan);
318 return 0;
319}
320
321static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
322{
323 struct uart_port *port = &ourport->port;
324 struct circ_buf *xmit = &port->state->xmit;
325 unsigned long count;
326
327
328 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
329
330 if (!count) {
331 s3c24xx_serial_stop_tx(port);
332 return;
333 }
334
335 if (!ourport->dma || !ourport->dma->tx_chan ||
336 count < ourport->min_dma_size ||
337 xmit->tail & (dma_get_cache_alignment() - 1))
338 s3c24xx_serial_start_tx_pio(ourport);
339 else
340 s3c24xx_serial_start_tx_dma(ourport, count);
341}
342
343static void s3c24xx_serial_start_tx(struct uart_port *port)
344{
345 struct s3c24xx_uart_port *ourport = to_ourport(port);
346 struct circ_buf *xmit = &port->state->xmit;
347
348 if (!tx_enabled(port)) {
349 if (port->flags & UPF_CONS_FLOW)
350 s3c24xx_serial_rx_disable(port);
351
352 tx_enabled(port) = 1;
353 if (!ourport->dma || !ourport->dma->tx_chan)
354 s3c24xx_serial_start_tx_pio(ourport);
355 }
356
357 if (ourport->dma && ourport->dma->tx_chan) {
358 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
359 s3c24xx_serial_start_next_tx(ourport);
360 }
361}
362
363static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
364 struct tty_port *tty, int count)
365{
366 struct s3c24xx_uart_dma *dma = ourport->dma;
367 int copied;
368
369 if (!count)
370 return;
371
372 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
373 dma->rx_size, DMA_FROM_DEVICE);
374
375 ourport->port.icount.rx += count;
376 if (!tty) {
377 dev_err(ourport->port.dev, "No tty port\n");
378 return;
379 }
380 copied = tty_insert_flip_string(tty,
381 ((unsigned char *)(ourport->dma->rx_buf)), count);
382 if (copied != count) {
383 WARN_ON(1);
384 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
385 }
386}
387
388static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
389 unsigned long ufstat);
390
391static void uart_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
392{
393 struct uart_port *port = &ourport->port;
394 struct tty_port *tty = &port->state->port;
395 unsigned int ch, ufstat;
396 unsigned int count;
397
398 ufstat = rd_regl(port, S3C2410_UFSTAT);
399 count = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
400
401 if (!count)
402 return;
403
404 while (count-- > 0) {
405 ch = rd_regb(port, S3C2410_URXH);
406
407 ourport->port.icount.rx++;
408 tty_insert_flip_char(tty, ch, TTY_NORMAL);
409 }
410
411 tty_flip_buffer_push(tty);
412}
413
414static void s3c24xx_serial_stop_rx(struct uart_port *port)
415{
416 struct s3c24xx_uart_port *ourport = to_ourport(port);
417 struct s3c24xx_uart_dma *dma = ourport->dma;
418 struct tty_port *t = &port->state->port;
419 struct dma_tx_state state;
420 enum dma_status dma_status;
421 unsigned int received;
422
423 if (rx_enabled(port)) {
424 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
425 if (s3c24xx_serial_has_interrupt_mask(port))
426 __set_bit(S3C64XX_UINTM_RXD,
427 portaddrl(port, S3C64XX_UINTM));
428 else
429 disable_irq_nosync(ourport->rx_irq);
430 rx_enabled(port) = 0;
431 }
432 if (dma && dma->rx_chan) {
433 dmaengine_pause(dma->tx_chan);
434 dma_status = dmaengine_tx_status(dma->rx_chan,
435 dma->rx_cookie, &state);
436 if (dma_status == DMA_IN_PROGRESS ||
437 dma_status == DMA_PAUSED) {
438 received = dma->rx_bytes_requested - state.residue;
439 dmaengine_terminate_all(dma->rx_chan);
440 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
441 }
442 }
443}
444
445static inline struct s3c24xx_uart_info
446 *s3c24xx_port_to_info(struct uart_port *port)
447{
448 return to_ourport(port)->info;
449}
450
451static inline struct s3c2410_uartcfg
452 *s3c24xx_port_to_cfg(struct uart_port *port)
453{
454 struct s3c24xx_uart_port *ourport;
455
456 if (port->dev == NULL)
457 return NULL;
458
459 ourport = container_of(port, struct s3c24xx_uart_port, port);
460 return ourport->cfg;
461}
462
463static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
464 unsigned long ufstat)
465{
466 struct s3c24xx_uart_info *info = ourport->info;
467
468 if (ufstat & info->rx_fifofull)
469 return ourport->port.fifosize;
470
471 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
472}
473
474static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
475static void s3c24xx_serial_rx_dma_complete(void *args)
476{
477 struct s3c24xx_uart_port *ourport = args;
478 struct uart_port *port = &ourport->port;
479
480 struct s3c24xx_uart_dma *dma = ourport->dma;
481 struct tty_port *t = &port->state->port;
482 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
483
484 struct dma_tx_state state;
485 unsigned long flags;
486 int received;
487
488 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
489 received = dma->rx_bytes_requested - state.residue;
490 async_tx_ack(dma->rx_desc);
491
492 spin_lock_irqsave(&port->lock, flags);
493
494 if (received)
495 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
496
497 if (tty) {
498 tty_flip_buffer_push(t);
499 tty_kref_put(tty);
500 }
501
502 s3c64xx_start_rx_dma(ourport);
503
504 spin_unlock_irqrestore(&port->lock, flags);
505}
506
507static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
508{
509 struct s3c24xx_uart_dma *dma = ourport->dma;
510
511 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
512 dma->rx_size, DMA_FROM_DEVICE);
513
514 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
515 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
516 DMA_PREP_INTERRUPT);
517 if (!dma->rx_desc) {
518 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
519 return;
520 }
521
522 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
523 dma->rx_desc->callback_param = ourport;
524 dma->rx_bytes_requested = dma->rx_size;
525
526 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
527 dma_async_issue_pending(dma->rx_chan);
528}
529
530
531#define S3C2410_UERSTAT_PARITY (0x1000)
532
533static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
534{
535 struct uart_port *port = &ourport->port;
536 unsigned int ucon;
537
538
539 ucon = rd_regl(port, S3C2410_UCON);
540 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
541 S3C64XX_UCON_TIMEOUT_MASK |
542 S3C64XX_UCON_EMPTYINT_EN |
543 S3C64XX_UCON_DMASUS_EN |
544 S3C64XX_UCON_TIMEOUT_EN |
545 S3C64XX_UCON_RXMODE_MASK);
546 ucon |= S3C64XX_UCON_RXBURST_16 |
547 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
548 S3C64XX_UCON_EMPTYINT_EN |
549 S3C64XX_UCON_TIMEOUT_EN |
550 S3C64XX_UCON_RXMODE_DMA;
551 wr_regl(port, S3C2410_UCON, ucon);
552
553 ourport->rx_mode = S3C24XX_RX_DMA;
554}
555
556static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
557{
558 struct uart_port *port = &ourport->port;
559 unsigned int ucon;
560
561
562 ucon = rd_regl(port, S3C2410_UCON);
563 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
564 S3C64XX_UCON_EMPTYINT_EN |
565 S3C64XX_UCON_DMASUS_EN |
566 S3C64XX_UCON_TIMEOUT_EN |
567 S3C64XX_UCON_RXMODE_MASK);
568 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
569 S3C64XX_UCON_TIMEOUT_EN |
570 S3C64XX_UCON_RXMODE_CPU;
571 wr_regl(port, S3C2410_UCON, ucon);
572
573 ourport->rx_mode = S3C24XX_RX_PIO;
574}
575
576static irqreturn_t s3c24xx_serial_rx_chars_dma(int irq, void *dev_id)
577{
578 unsigned int utrstat, ufstat, received;
579 struct s3c24xx_uart_port *ourport = dev_id;
580 struct uart_port *port = &ourport->port;
581 struct s3c24xx_uart_dma *dma = ourport->dma;
582 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
583 struct tty_port *t = &port->state->port;
584 unsigned long flags;
585 struct dma_tx_state state;
586
587 utrstat = rd_regl(port, S3C2410_UTRSTAT);
588 ufstat = rd_regl(port, S3C2410_UFSTAT);
589
590 spin_lock_irqsave(&port->lock, flags);
591
592 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
593 s3c64xx_start_rx_dma(ourport);
594 if (ourport->rx_mode == S3C24XX_RX_PIO)
595 enable_rx_dma(ourport);
596 goto finish;
597 }
598
599 if (ourport->rx_mode == S3C24XX_RX_DMA) {
600 dmaengine_pause(dma->rx_chan);
601 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
602 dmaengine_terminate_all(dma->rx_chan);
603 received = dma->rx_bytes_requested - state.residue;
604 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
605
606 enable_rx_pio(ourport);
607 }
608
609 uart_rx_drain_fifo(ourport);
610
611 if (tty) {
612 tty_flip_buffer_push(t);
613 tty_kref_put(tty);
614 }
615
616 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
617
618finish:
619 spin_unlock_irqrestore(&port->lock, flags);
620
621 return IRQ_HANDLED;
622}
623
624static irqreturn_t s3c24xx_serial_rx_chars_pio(int irq, void *dev_id)
625{
626 struct s3c24xx_uart_port *ourport = dev_id;
627 struct uart_port *port = &ourport->port;
628 unsigned int ufcon, ch, flag, ufstat, uerstat;
629 unsigned long flags;
630 int max_count = port->fifosize;
631
632 spin_lock_irqsave(&port->lock, flags);
633
634 while (max_count-- > 0) {
635 ufcon = rd_regl(port, S3C2410_UFCON);
636 ufstat = rd_regl(port, S3C2410_UFSTAT);
637
638 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
639 break;
640
641 uerstat = rd_regl(port, S3C2410_UERSTAT);
642 ch = rd_regb(port, S3C2410_URXH);
643
644 if (port->flags & UPF_CONS_FLOW) {
645 int txe = s3c24xx_serial_txempty_nofifo(port);
646
647 if (rx_enabled(port)) {
648 if (!txe) {
649 rx_enabled(port) = 0;
650 continue;
651 }
652 } else {
653 if (txe) {
654 ufcon |= S3C2410_UFCON_RESETRX;
655 wr_regl(port, S3C2410_UFCON, ufcon);
656 rx_enabled(port) = 1;
657 spin_unlock_irqrestore(&port->lock,
658 flags);
659 goto out;
660 }
661 continue;
662 }
663 }
664
665
666
667 flag = TTY_NORMAL;
668 port->icount.rx++;
669
670 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
671 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
672 ch, uerstat);
673
674
675 if (uerstat & S3C2410_UERSTAT_BREAK) {
676 dbg("break!\n");
677 port->icount.brk++;
678 if (uart_handle_break(port))
679 goto ignore_char;
680 }
681
682 if (uerstat & S3C2410_UERSTAT_FRAME)
683 port->icount.frame++;
684 if (uerstat & S3C2410_UERSTAT_OVERRUN)
685 port->icount.overrun++;
686
687 uerstat &= port->read_status_mask;
688
689 if (uerstat & S3C2410_UERSTAT_BREAK)
690 flag = TTY_BREAK;
691 else if (uerstat & S3C2410_UERSTAT_PARITY)
692 flag = TTY_PARITY;
693 else if (uerstat & (S3C2410_UERSTAT_FRAME |
694 S3C2410_UERSTAT_OVERRUN))
695 flag = TTY_FRAME;
696 }
697
698 if (uart_handle_sysrq_char(port, ch))
699 goto ignore_char;
700
701 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
702 ch, flag);
703
704ignore_char:
705 continue;
706 }
707
708 spin_unlock_irqrestore(&port->lock, flags);
709 tty_flip_buffer_push(&port->state->port);
710
711out:
712 return IRQ_HANDLED;
713}
714
715
716static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
717{
718 struct s3c24xx_uart_port *ourport = dev_id;
719
720 if (ourport->dma && ourport->dma->rx_chan)
721 return s3c24xx_serial_rx_chars_dma(irq, dev_id);
722 return s3c24xx_serial_rx_chars_pio(irq, dev_id);
723}
724
725static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
726{
727 struct s3c24xx_uart_port *ourport = id;
728 struct uart_port *port = &ourport->port;
729 struct circ_buf *xmit = &port->state->xmit;
730 unsigned long flags;
731 int count, dma_count = 0;
732
733 spin_lock_irqsave(&port->lock, flags);
734
735 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
736
737 if (ourport->dma && ourport->dma->tx_chan &&
738 count >= ourport->min_dma_size) {
739 int align = dma_get_cache_alignment() -
740 (xmit->tail & (dma_get_cache_alignment() - 1));
741 if (count-align >= ourport->min_dma_size) {
742 dma_count = count-align;
743 count = align;
744 }
745 }
746
747 if (port->x_char) {
748 wr_regb(port, S3C2410_UTXH, port->x_char);
749 port->icount.tx++;
750 port->x_char = 0;
751 goto out;
752 }
753
754
755
756
757
758 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
759 s3c24xx_serial_stop_tx(port);
760 goto out;
761 }
762
763
764
765 if (count > port->fifosize) {
766 count = port->fifosize;
767 dma_count = 0;
768 }
769
770 while (!uart_circ_empty(xmit) && count > 0) {
771 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
772 break;
773
774 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
775 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
776 port->icount.tx++;
777 count--;
778 }
779
780 if (!count && dma_count) {
781 s3c24xx_serial_start_tx_dma(ourport, dma_count);
782 goto out;
783 }
784
785 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
786 spin_unlock(&port->lock);
787 uart_write_wakeup(port);
788 spin_lock(&port->lock);
789 }
790
791 if (uart_circ_empty(xmit))
792 s3c24xx_serial_stop_tx(port);
793
794out:
795 spin_unlock_irqrestore(&port->lock, flags);
796 return IRQ_HANDLED;
797}
798
799
800static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
801{
802 struct s3c24xx_uart_port *ourport = id;
803 struct uart_port *port = &ourport->port;
804 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
805 irqreturn_t ret = IRQ_HANDLED;
806
807 if (pend & S3C64XX_UINTM_RXD_MSK) {
808 ret = s3c24xx_serial_rx_chars(irq, id);
809 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
810 }
811 if (pend & S3C64XX_UINTM_TXD_MSK) {
812 ret = s3c24xx_serial_tx_chars(irq, id);
813 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
814 }
815 return ret;
816}
817
818static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
819{
820 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
821 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
822 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
823
824 if (ufcon & S3C2410_UFCON_FIFOMODE) {
825 if ((ufstat & info->tx_fifomask) != 0 ||
826 (ufstat & info->tx_fifofull))
827 return 0;
828
829 return 1;
830 }
831
832 return s3c24xx_serial_txempty_nofifo(port);
833}
834
835
836static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
837{
838 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
839
840 if (umstat & S3C2410_UMSTAT_CTS)
841 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
842 else
843 return TIOCM_CAR | TIOCM_DSR;
844}
845
846static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
847{
848 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
849
850 if (mctrl & TIOCM_RTS)
851 umcon |= S3C2410_UMCOM_RTS_LOW;
852 else
853 umcon &= ~S3C2410_UMCOM_RTS_LOW;
854
855 wr_regl(port, S3C2410_UMCON, umcon);
856}
857
858static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
859{
860 unsigned long flags;
861 unsigned int ucon;
862
863 spin_lock_irqsave(&port->lock, flags);
864
865 ucon = rd_regl(port, S3C2410_UCON);
866
867 if (break_state)
868 ucon |= S3C2410_UCON_SBREAK;
869 else
870 ucon &= ~S3C2410_UCON_SBREAK;
871
872 wr_regl(port, S3C2410_UCON, ucon);
873
874 spin_unlock_irqrestore(&port->lock, flags);
875}
876
877static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
878{
879 struct s3c24xx_uart_dma *dma = p->dma;
880 dma_cap_mask_t mask;
881 unsigned long flags;
882
883
884 dma->rx_conf.direction = DMA_DEV_TO_MEM;
885 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
886 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
887 dma->rx_conf.src_maxburst = 16;
888
889 dma->tx_conf.direction = DMA_MEM_TO_DEV;
890 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
891 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
892 if (dma_get_cache_alignment() >= 16)
893 dma->tx_conf.dst_maxburst = 16;
894 else
895 dma->tx_conf.dst_maxburst = 1;
896
897 dma_cap_zero(mask);
898 dma_cap_set(DMA_SLAVE, mask);
899
900 dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
901 dma->rx_param, p->port.dev, "rx");
902 if (!dma->rx_chan)
903 return -ENODEV;
904
905 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
906
907 dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
908 dma->tx_param, p->port.dev, "tx");
909 if (!dma->tx_chan) {
910 dma_release_channel(dma->rx_chan);
911 return -ENODEV;
912 }
913
914 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
915
916
917 dma->rx_size = PAGE_SIZE;
918
919 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
920
921 if (!dma->rx_buf) {
922 dma_release_channel(dma->rx_chan);
923 dma_release_channel(dma->tx_chan);
924 return -ENOMEM;
925 }
926
927 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
928 dma->rx_size, DMA_FROM_DEVICE);
929
930 spin_lock_irqsave(&p->port.lock, flags);
931
932
933 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
934 p->port.state->xmit.buf,
935 UART_XMIT_SIZE, DMA_TO_DEVICE);
936
937 spin_unlock_irqrestore(&p->port.lock, flags);
938
939 return 0;
940}
941
942static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
943{
944 struct s3c24xx_uart_dma *dma = p->dma;
945
946 if (dma->rx_chan) {
947 dmaengine_terminate_all(dma->rx_chan);
948 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
949 dma->rx_size, DMA_FROM_DEVICE);
950 kfree(dma->rx_buf);
951 dma_release_channel(dma->rx_chan);
952 dma->rx_chan = NULL;
953 }
954
955 if (dma->tx_chan) {
956 dmaengine_terminate_all(dma->tx_chan);
957 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
958 UART_XMIT_SIZE, DMA_TO_DEVICE);
959 dma_release_channel(dma->tx_chan);
960 dma->tx_chan = NULL;
961 }
962}
963
964static void s3c24xx_serial_shutdown(struct uart_port *port)
965{
966 struct s3c24xx_uart_port *ourport = to_ourport(port);
967
968 if (ourport->tx_claimed) {
969 if (!s3c24xx_serial_has_interrupt_mask(port))
970 free_irq(ourport->tx_irq, ourport);
971 tx_enabled(port) = 0;
972 ourport->tx_claimed = 0;
973 ourport->tx_mode = 0;
974 }
975
976 if (ourport->rx_claimed) {
977 if (!s3c24xx_serial_has_interrupt_mask(port))
978 free_irq(ourport->rx_irq, ourport);
979 ourport->rx_claimed = 0;
980 rx_enabled(port) = 0;
981 }
982
983
984 if (s3c24xx_serial_has_interrupt_mask(port)) {
985 free_irq(port->irq, ourport);
986
987 wr_regl(port, S3C64XX_UINTP, 0xf);
988 wr_regl(port, S3C64XX_UINTM, 0xf);
989 }
990
991 if (ourport->dma)
992 s3c24xx_serial_release_dma(ourport);
993
994 ourport->tx_in_progress = 0;
995}
996
997static int s3c24xx_serial_startup(struct uart_port *port)
998{
999 struct s3c24xx_uart_port *ourport = to_ourport(port);
1000 int ret;
1001
1002 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
1003 port, (unsigned long long)port->mapbase, port->membase);
1004
1005 rx_enabled(port) = 1;
1006
1007 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1008 s3c24xx_serial_portname(port), ourport);
1009
1010 if (ret != 0) {
1011 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1012 return ret;
1013 }
1014
1015 ourport->rx_claimed = 1;
1016
1017 dbg("requesting tx irq...\n");
1018
1019 tx_enabled(port) = 1;
1020
1021 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1022 s3c24xx_serial_portname(port), ourport);
1023
1024 if (ret) {
1025 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1026 goto err;
1027 }
1028
1029 ourport->tx_claimed = 1;
1030
1031 dbg("s3c24xx_serial_startup ok\n");
1032
1033
1034
1035
1036 return ret;
1037
1038err:
1039 s3c24xx_serial_shutdown(port);
1040 return ret;
1041}
1042
1043static int s3c64xx_serial_startup(struct uart_port *port)
1044{
1045 struct s3c24xx_uart_port *ourport = to_ourport(port);
1046 unsigned long flags;
1047 unsigned int ufcon;
1048 int ret;
1049
1050 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1051 port, (unsigned long long)port->mapbase, port->membase);
1052
1053 wr_regl(port, S3C64XX_UINTM, 0xf);
1054 if (ourport->dma) {
1055 ret = s3c24xx_serial_request_dma(ourport);
1056 if (ret < 0) {
1057 dev_warn(port->dev, "DMA request failed\n");
1058 return ret;
1059 }
1060 }
1061
1062 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1063 s3c24xx_serial_portname(port), ourport);
1064 if (ret) {
1065 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1066 return ret;
1067 }
1068
1069
1070 rx_enabled(port) = 1;
1071 ourport->rx_claimed = 1;
1072 tx_enabled(port) = 0;
1073 ourport->tx_claimed = 1;
1074
1075 spin_lock_irqsave(&port->lock, flags);
1076
1077 ufcon = rd_regl(port, S3C2410_UFCON);
1078 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1079 if (!uart_console(port))
1080 ufcon |= S3C2410_UFCON_RESETTX;
1081 wr_regl(port, S3C2410_UFCON, ufcon);
1082
1083 enable_rx_pio(ourport);
1084
1085 spin_unlock_irqrestore(&port->lock, flags);
1086
1087
1088 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
1089
1090 dbg("s3c64xx_serial_startup ok\n");
1091 return ret;
1092}
1093
1094
1095
1096static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1097 unsigned int old)
1098{
1099 struct s3c24xx_uart_port *ourport = to_ourport(port);
1100 int timeout = 10000;
1101
1102 ourport->pm_level = level;
1103
1104 switch (level) {
1105 case 3:
1106 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1107 udelay(100);
1108
1109 if (!IS_ERR(ourport->baudclk))
1110 clk_disable_unprepare(ourport->baudclk);
1111
1112 clk_disable_unprepare(ourport->clk);
1113 break;
1114
1115 case 0:
1116 clk_prepare_enable(ourport->clk);
1117
1118 if (!IS_ERR(ourport->baudclk))
1119 clk_prepare_enable(ourport->baudclk);
1120
1121 break;
1122 default:
1123 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1124 }
1125}
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140#define MAX_CLK_NAME_LENGTH 15
1141
1142static inline int s3c24xx_serial_getsource(struct uart_port *port)
1143{
1144 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1145 unsigned int ucon;
1146
1147 if (info->num_clks == 1)
1148 return 0;
1149
1150 ucon = rd_regl(port, S3C2410_UCON);
1151 ucon &= info->clksel_mask;
1152 return ucon >> info->clksel_shift;
1153}
1154
1155static void s3c24xx_serial_setsource(struct uart_port *port,
1156 unsigned int clk_sel)
1157{
1158 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1159 unsigned int ucon;
1160
1161 if (info->num_clks == 1)
1162 return;
1163
1164 ucon = rd_regl(port, S3C2410_UCON);
1165 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1166 return;
1167
1168 ucon &= ~info->clksel_mask;
1169 ucon |= clk_sel << info->clksel_shift;
1170 wr_regl(port, S3C2410_UCON, ucon);
1171}
1172
1173static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1174 unsigned int req_baud, struct clk **best_clk,
1175 unsigned int *clk_num)
1176{
1177 struct s3c24xx_uart_info *info = ourport->info;
1178 struct clk *clk;
1179 unsigned long rate;
1180 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1181 char clkname[MAX_CLK_NAME_LENGTH];
1182 int calc_deviation, deviation = (1 << 30) - 1;
1183
1184 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1185 ourport->info->def_clk_sel;
1186 for (cnt = 0; cnt < info->num_clks; cnt++) {
1187 if (!(clk_sel & (1 << cnt)))
1188 continue;
1189
1190 sprintf(clkname, "clk_uart_baud%d", cnt);
1191 clk = clk_get(ourport->port.dev, clkname);
1192 if (IS_ERR(clk))
1193 continue;
1194
1195 rate = clk_get_rate(clk);
1196 if (!rate)
1197 continue;
1198
1199 if (ourport->info->has_divslot) {
1200 unsigned long div = rate / req_baud;
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210 quot = div / 16;
1211 baud = rate / div;
1212 } else {
1213 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1214 baud = rate / (quot * 16);
1215 }
1216 quot--;
1217
1218 calc_deviation = req_baud - baud;
1219 if (calc_deviation < 0)
1220 calc_deviation = -calc_deviation;
1221
1222 if (calc_deviation < deviation) {
1223 *best_clk = clk;
1224 best_quot = quot;
1225 *clk_num = cnt;
1226 deviation = calc_deviation;
1227 }
1228 }
1229
1230 return best_quot;
1231}
1232
1233
1234
1235
1236
1237
1238static u16 udivslot_table[16] = {
1239 [0] = 0x0000,
1240 [1] = 0x0080,
1241 [2] = 0x0808,
1242 [3] = 0x0888,
1243 [4] = 0x2222,
1244 [5] = 0x4924,
1245 [6] = 0x4A52,
1246 [7] = 0x54AA,
1247 [8] = 0x5555,
1248 [9] = 0xD555,
1249 [10] = 0xD5D5,
1250 [11] = 0xDDD5,
1251 [12] = 0xDDDD,
1252 [13] = 0xDFDD,
1253 [14] = 0xDFDF,
1254 [15] = 0xFFDF,
1255};
1256
1257static void s3c24xx_serial_set_termios(struct uart_port *port,
1258 struct ktermios *termios,
1259 struct ktermios *old)
1260{
1261 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1262 struct s3c24xx_uart_port *ourport = to_ourport(port);
1263 struct clk *clk = ERR_PTR(-EINVAL);
1264 unsigned long flags;
1265 unsigned int baud, quot, clk_sel = 0;
1266 unsigned int ulcon;
1267 unsigned int umcon;
1268 unsigned int udivslot = 0;
1269
1270
1271
1272
1273 termios->c_cflag &= ~(HUPCL | CMSPAR);
1274 termios->c_cflag |= CLOCAL;
1275
1276
1277
1278
1279
1280 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1281 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1282 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1283 quot = port->custom_divisor;
1284 if (IS_ERR(clk))
1285 return;
1286
1287
1288
1289 if (ourport->baudclk != clk) {
1290 s3c24xx_serial_setsource(port, clk_sel);
1291
1292 if (!IS_ERR(ourport->baudclk)) {
1293 clk_disable_unprepare(ourport->baudclk);
1294 ourport->baudclk = ERR_PTR(-EINVAL);
1295 }
1296
1297 clk_prepare_enable(clk);
1298
1299 ourport->baudclk = clk;
1300 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1301 }
1302
1303 if (ourport->info->has_divslot) {
1304 unsigned int div = ourport->baudclk_rate / baud;
1305
1306 if (cfg->has_fracval) {
1307 udivslot = (div & 15);
1308 dbg("fracval = %04x\n", udivslot);
1309 } else {
1310 udivslot = udivslot_table[div & 15];
1311 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1312 }
1313 }
1314
1315 switch (termios->c_cflag & CSIZE) {
1316 case CS5:
1317 dbg("config: 5bits/char\n");
1318 ulcon = S3C2410_LCON_CS5;
1319 break;
1320 case CS6:
1321 dbg("config: 6bits/char\n");
1322 ulcon = S3C2410_LCON_CS6;
1323 break;
1324 case CS7:
1325 dbg("config: 7bits/char\n");
1326 ulcon = S3C2410_LCON_CS7;
1327 break;
1328 case CS8:
1329 default:
1330 dbg("config: 8bits/char\n");
1331 ulcon = S3C2410_LCON_CS8;
1332 break;
1333 }
1334
1335
1336 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1337
1338 if (termios->c_cflag & CSTOPB)
1339 ulcon |= S3C2410_LCON_STOPB;
1340
1341 if (termios->c_cflag & PARENB) {
1342 if (termios->c_cflag & PARODD)
1343 ulcon |= S3C2410_LCON_PODD;
1344 else
1345 ulcon |= S3C2410_LCON_PEVEN;
1346 } else {
1347 ulcon |= S3C2410_LCON_PNONE;
1348 }
1349
1350 spin_lock_irqsave(&port->lock, flags);
1351
1352 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1353 ulcon, quot, udivslot);
1354
1355 wr_regl(port, S3C2410_ULCON, ulcon);
1356 wr_regl(port, S3C2410_UBRDIV, quot);
1357
1358 umcon = rd_regl(port, S3C2410_UMCON);
1359 if (termios->c_cflag & CRTSCTS) {
1360 umcon |= S3C2410_UMCOM_AFC;
1361
1362 umcon &= ~S3C2412_UMCON_AFC_8;
1363 } else {
1364 umcon &= ~S3C2410_UMCOM_AFC;
1365 }
1366 wr_regl(port, S3C2410_UMCON, umcon);
1367
1368 if (ourport->info->has_divslot)
1369 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1370
1371 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1372 rd_regl(port, S3C2410_ULCON),
1373 rd_regl(port, S3C2410_UCON),
1374 rd_regl(port, S3C2410_UFCON));
1375
1376
1377
1378
1379 uart_update_timeout(port, termios->c_cflag, baud);
1380
1381
1382
1383
1384 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1385 if (termios->c_iflag & INPCK)
1386 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1387 S3C2410_UERSTAT_PARITY;
1388
1389
1390
1391 port->ignore_status_mask = 0;
1392 if (termios->c_iflag & IGNPAR)
1393 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1394 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1395 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1396
1397
1398
1399
1400 if ((termios->c_cflag & CREAD) == 0)
1401 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1402
1403 spin_unlock_irqrestore(&port->lock, flags);
1404}
1405
1406static const char *s3c24xx_serial_type(struct uart_port *port)
1407{
1408 switch (port->type) {
1409 case PORT_S3C2410:
1410 return "S3C2410";
1411 case PORT_S3C2440:
1412 return "S3C2440";
1413 case PORT_S3C2412:
1414 return "S3C2412";
1415 case PORT_S3C6400:
1416 return "S3C6400/10";
1417 default:
1418 return NULL;
1419 }
1420}
1421
1422#define MAP_SIZE (0x100)
1423
1424static void s3c24xx_serial_release_port(struct uart_port *port)
1425{
1426 release_mem_region(port->mapbase, MAP_SIZE);
1427}
1428
1429static int s3c24xx_serial_request_port(struct uart_port *port)
1430{
1431 const char *name = s3c24xx_serial_portname(port);
1432 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1433}
1434
1435static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1436{
1437 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1438
1439 if (flags & UART_CONFIG_TYPE &&
1440 s3c24xx_serial_request_port(port) == 0)
1441 port->type = info->type;
1442}
1443
1444
1445
1446
1447static int
1448s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1449{
1450 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1451
1452 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1453 return -EINVAL;
1454
1455 return 0;
1456}
1457
1458
1459#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1460
1461static struct console s3c24xx_serial_console;
1462
1463static int __init s3c24xx_serial_console_init(void)
1464{
1465 register_console(&s3c24xx_serial_console);
1466 return 0;
1467}
1468console_initcall(s3c24xx_serial_console_init);
1469
1470#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1471#else
1472#define S3C24XX_SERIAL_CONSOLE NULL
1473#endif
1474
1475#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1476static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1477static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1478 unsigned char c);
1479#endif
1480
1481static struct uart_ops s3c24xx_serial_ops = {
1482 .pm = s3c24xx_serial_pm,
1483 .tx_empty = s3c24xx_serial_tx_empty,
1484 .get_mctrl = s3c24xx_serial_get_mctrl,
1485 .set_mctrl = s3c24xx_serial_set_mctrl,
1486 .stop_tx = s3c24xx_serial_stop_tx,
1487 .start_tx = s3c24xx_serial_start_tx,
1488 .stop_rx = s3c24xx_serial_stop_rx,
1489 .break_ctl = s3c24xx_serial_break_ctl,
1490 .startup = s3c24xx_serial_startup,
1491 .shutdown = s3c24xx_serial_shutdown,
1492 .set_termios = s3c24xx_serial_set_termios,
1493 .type = s3c24xx_serial_type,
1494 .release_port = s3c24xx_serial_release_port,
1495 .request_port = s3c24xx_serial_request_port,
1496 .config_port = s3c24xx_serial_config_port,
1497 .verify_port = s3c24xx_serial_verify_port,
1498#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1499 .poll_get_char = s3c24xx_serial_get_poll_char,
1500 .poll_put_char = s3c24xx_serial_put_poll_char,
1501#endif
1502};
1503
1504static struct uart_driver s3c24xx_uart_drv = {
1505 .owner = THIS_MODULE,
1506 .driver_name = "s3c2410_serial",
1507 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1508 .cons = S3C24XX_SERIAL_CONSOLE,
1509 .dev_name = S3C24XX_SERIAL_NAME,
1510 .major = S3C24XX_SERIAL_MAJOR,
1511 .minor = S3C24XX_SERIAL_MINOR,
1512};
1513
1514#define __PORT_LOCK_UNLOCKED(i) \
1515 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1516static struct s3c24xx_uart_port
1517s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1518 [0] = {
1519 .port = {
1520 .lock = __PORT_LOCK_UNLOCKED(0),
1521 .iotype = UPIO_MEM,
1522 .uartclk = 0,
1523 .fifosize = 16,
1524 .ops = &s3c24xx_serial_ops,
1525 .flags = UPF_BOOT_AUTOCONF,
1526 .line = 0,
1527 }
1528 },
1529 [1] = {
1530 .port = {
1531 .lock = __PORT_LOCK_UNLOCKED(1),
1532 .iotype = UPIO_MEM,
1533 .uartclk = 0,
1534 .fifosize = 16,
1535 .ops = &s3c24xx_serial_ops,
1536 .flags = UPF_BOOT_AUTOCONF,
1537 .line = 1,
1538 }
1539 },
1540#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1541
1542 [2] = {
1543 .port = {
1544 .lock = __PORT_LOCK_UNLOCKED(2),
1545 .iotype = UPIO_MEM,
1546 .uartclk = 0,
1547 .fifosize = 16,
1548 .ops = &s3c24xx_serial_ops,
1549 .flags = UPF_BOOT_AUTOCONF,
1550 .line = 2,
1551 }
1552 },
1553#endif
1554#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1555 [3] = {
1556 .port = {
1557 .lock = __PORT_LOCK_UNLOCKED(3),
1558 .iotype = UPIO_MEM,
1559 .uartclk = 0,
1560 .fifosize = 16,
1561 .ops = &s3c24xx_serial_ops,
1562 .flags = UPF_BOOT_AUTOCONF,
1563 .line = 3,
1564 }
1565 }
1566#endif
1567};
1568#undef __PORT_LOCK_UNLOCKED
1569
1570
1571
1572
1573
1574
1575static void s3c24xx_serial_resetport(struct uart_port *port,
1576 struct s3c2410_uartcfg *cfg)
1577{
1578 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1579 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1580 unsigned int ucon_mask;
1581
1582 ucon_mask = info->clksel_mask;
1583 if (info->type == PORT_S3C2440)
1584 ucon_mask |= S3C2440_UCON0_DIVMASK;
1585
1586 ucon &= ucon_mask;
1587 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1588
1589
1590 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1591 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1592
1593
1594 udelay(1);
1595}
1596
1597
1598#ifdef CONFIG_CPU_FREQ
1599
1600static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1601 unsigned long val, void *data)
1602{
1603 struct s3c24xx_uart_port *port;
1604 struct uart_port *uport;
1605
1606 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1607 uport = &port->port;
1608
1609
1610
1611 if (port->pm_level != 0)
1612 return 0;
1613
1614
1615
1616
1617
1618
1619 if (IS_ERR(port->baudclk))
1620 goto exit;
1621
1622 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1623 goto exit;
1624
1625 if (val == CPUFREQ_PRECHANGE) {
1626
1627
1628
1629 } else if (val == CPUFREQ_POSTCHANGE) {
1630 struct ktermios *termios;
1631 struct tty_struct *tty;
1632
1633 if (uport->state == NULL)
1634 goto exit;
1635
1636 tty = uport->state->port.tty;
1637
1638 if (tty == NULL)
1639 goto exit;
1640
1641 termios = &tty->termios;
1642
1643 if (termios == NULL) {
1644 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1645 goto exit;
1646 }
1647
1648 s3c24xx_serial_set_termios(uport, termios, NULL);
1649 }
1650
1651exit:
1652 return 0;
1653}
1654
1655static inline int
1656s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1657{
1658 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1659
1660 return cpufreq_register_notifier(&port->freq_transition,
1661 CPUFREQ_TRANSITION_NOTIFIER);
1662}
1663
1664static inline void
1665s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1666{
1667 cpufreq_unregister_notifier(&port->freq_transition,
1668 CPUFREQ_TRANSITION_NOTIFIER);
1669}
1670
1671#else
1672static inline int
1673s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1674{
1675 return 0;
1676}
1677
1678static inline void
1679s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1680{
1681}
1682#endif
1683
1684
1685
1686
1687
1688
1689static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1690 struct platform_device *platdev)
1691{
1692 struct uart_port *port = &ourport->port;
1693 struct s3c2410_uartcfg *cfg = ourport->cfg;
1694 struct resource *res;
1695 int ret;
1696
1697 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1698
1699 if (platdev == NULL)
1700 return -ENODEV;
1701
1702 if (port->mapbase != 0)
1703 return 0;
1704
1705
1706 port->dev = &platdev->dev;
1707
1708
1709 if (s3c24xx_serial_has_interrupt_mask(port))
1710 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1711
1712 port->uartclk = 1;
1713
1714 if (cfg->uart_flags & UPF_CONS_FLOW) {
1715 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1716 port->flags |= UPF_CONS_FLOW;
1717 }
1718
1719
1720
1721 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1722 if (res == NULL) {
1723 dev_err(port->dev, "failed to find memory resource for uart\n");
1724 return -EINVAL;
1725 }
1726
1727 dbg("resource %pR)\n", res);
1728
1729 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1730 if (!port->membase) {
1731 dev_err(port->dev, "failed to remap controller address\n");
1732 return -EBUSY;
1733 }
1734
1735 port->mapbase = res->start;
1736 ret = platform_get_irq(platdev, 0);
1737 if (ret < 0)
1738 port->irq = 0;
1739 else {
1740 port->irq = ret;
1741 ourport->rx_irq = ret;
1742 ourport->tx_irq = ret + 1;
1743 }
1744
1745 ret = platform_get_irq(platdev, 1);
1746 if (ret > 0)
1747 ourport->tx_irq = ret;
1748
1749
1750
1751
1752 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1753 "dmas", NULL)) {
1754 ourport->dma = devm_kzalloc(port->dev,
1755 sizeof(*ourport->dma),
1756 GFP_KERNEL);
1757 if (!ourport->dma)
1758 return -ENOMEM;
1759 }
1760
1761 ourport->clk = clk_get(&platdev->dev, "uart");
1762 if (IS_ERR(ourport->clk)) {
1763 pr_err("%s: Controller clock not found\n",
1764 dev_name(&platdev->dev));
1765 return PTR_ERR(ourport->clk);
1766 }
1767
1768 ret = clk_prepare_enable(ourport->clk);
1769 if (ret) {
1770 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1771 clk_put(ourport->clk);
1772 return ret;
1773 }
1774
1775
1776 if (s3c24xx_serial_has_interrupt_mask(port)) {
1777 wr_regl(port, S3C64XX_UINTM, 0xf);
1778 wr_regl(port, S3C64XX_UINTP, 0xf);
1779 wr_regl(port, S3C64XX_UINTSP, 0xf);
1780 }
1781
1782 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1783 &port->mapbase, port->membase, port->irq,
1784 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1785
1786
1787 s3c24xx_serial_resetport(port, cfg);
1788 return 0;
1789}
1790
1791
1792
1793static const struct of_device_id s3c24xx_uart_dt_match[];
1794static int probe_index;
1795
1796static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1797 struct platform_device *pdev)
1798{
1799#ifdef CONFIG_OF
1800 if (pdev->dev.of_node) {
1801 const struct of_device_id *match;
1802 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1803 return (struct s3c24xx_serial_drv_data *)match->data;
1804 }
1805#endif
1806 return (struct s3c24xx_serial_drv_data *)
1807 platform_get_device_id(pdev)->driver_data;
1808}
1809
1810static int s3c24xx_serial_probe(struct platform_device *pdev)
1811{
1812 struct device_node *np = pdev->dev.of_node;
1813 struct s3c24xx_uart_port *ourport;
1814 int index = probe_index;
1815 int ret;
1816
1817 if (np) {
1818 ret = of_alias_get_id(np, "serial");
1819 if (ret >= 0)
1820 index = ret;
1821 }
1822
1823 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1824
1825 ourport = &s3c24xx_serial_ports[index];
1826
1827 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1828 if (!ourport->drv_data) {
1829 dev_err(&pdev->dev, "could not find driver data\n");
1830 return -ENODEV;
1831 }
1832
1833 ourport->baudclk = ERR_PTR(-EINVAL);
1834 ourport->info = ourport->drv_data->info;
1835 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1836 dev_get_platdata(&pdev->dev) :
1837 ourport->drv_data->def_cfg;
1838
1839 if (np)
1840 of_property_read_u32(np,
1841 "samsung,uart-fifosize", &ourport->port.fifosize);
1842
1843 if (ourport->drv_data->fifosize[index])
1844 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1845 else if (ourport->info->fifosize)
1846 ourport->port.fifosize = ourport->info->fifosize;
1847
1848
1849
1850
1851
1852 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1853 dma_get_cache_alignment());
1854
1855 probe_index++;
1856
1857 dbg("%s: initialising port %p...\n", __func__, ourport);
1858
1859 ret = s3c24xx_serial_init_port(ourport, pdev);
1860 if (ret < 0)
1861 return ret;
1862
1863 if (!s3c24xx_uart_drv.state) {
1864 ret = uart_register_driver(&s3c24xx_uart_drv);
1865 if (ret < 0) {
1866 pr_err("Failed to register Samsung UART driver\n");
1867 return ret;
1868 }
1869 }
1870
1871 dbg("%s: adding port\n", __func__);
1872 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1873 platform_set_drvdata(pdev, &ourport->port);
1874
1875
1876
1877
1878
1879
1880 clk_disable_unprepare(ourport->clk);
1881
1882 ret = s3c24xx_serial_cpufreq_register(ourport);
1883 if (ret < 0)
1884 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1885
1886 return 0;
1887}
1888
1889static int s3c24xx_serial_remove(struct platform_device *dev)
1890{
1891 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1892
1893 if (port) {
1894 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1895 uart_remove_one_port(&s3c24xx_uart_drv, port);
1896 }
1897
1898 uart_unregister_driver(&s3c24xx_uart_drv);
1899
1900 return 0;
1901}
1902
1903
1904#ifdef CONFIG_PM_SLEEP
1905static int s3c24xx_serial_suspend(struct device *dev)
1906{
1907 struct uart_port *port = s3c24xx_dev_to_port(dev);
1908
1909 if (port)
1910 uart_suspend_port(&s3c24xx_uart_drv, port);
1911
1912 return 0;
1913}
1914
1915static int s3c24xx_serial_resume(struct device *dev)
1916{
1917 struct uart_port *port = s3c24xx_dev_to_port(dev);
1918 struct s3c24xx_uart_port *ourport = to_ourport(port);
1919
1920 if (port) {
1921 clk_prepare_enable(ourport->clk);
1922 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1923 clk_disable_unprepare(ourport->clk);
1924
1925 uart_resume_port(&s3c24xx_uart_drv, port);
1926 }
1927
1928 return 0;
1929}
1930
1931static int s3c24xx_serial_resume_noirq(struct device *dev)
1932{
1933 struct uart_port *port = s3c24xx_dev_to_port(dev);
1934
1935 if (port) {
1936
1937 if (s3c24xx_serial_has_interrupt_mask(port)) {
1938 unsigned int uintm = 0xf;
1939 if (tx_enabled(port))
1940 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1941 if (rx_enabled(port))
1942 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1943 wr_regl(port, S3C64XX_UINTM, uintm);
1944 }
1945 }
1946
1947 return 0;
1948}
1949
1950static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1951 .suspend = s3c24xx_serial_suspend,
1952 .resume = s3c24xx_serial_resume,
1953 .resume_noirq = s3c24xx_serial_resume_noirq,
1954};
1955#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1956
1957#else
1958
1959#define SERIAL_SAMSUNG_PM_OPS NULL
1960#endif
1961
1962
1963
1964#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1965
1966static struct uart_port *cons_uart;
1967
1968static int
1969s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1970{
1971 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1972 unsigned long ufstat, utrstat;
1973
1974 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1975
1976
1977 ufstat = rd_regl(port, S3C2410_UFSTAT);
1978 return (ufstat & info->tx_fifofull) ? 0 : 1;
1979 }
1980
1981
1982
1983 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1984 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1985}
1986
1987static bool
1988s3c24xx_port_configured(unsigned int ucon)
1989{
1990
1991 return (ucon & 0xf) != 0;
1992}
1993
1994#ifdef CONFIG_CONSOLE_POLL
1995
1996
1997
1998
1999
2000static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2001{
2002 struct s3c24xx_uart_port *ourport = to_ourport(port);
2003 unsigned int ufstat;
2004
2005 ufstat = rd_regl(port, S3C2410_UFSTAT);
2006 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2007 return NO_POLL_CHAR;
2008
2009 return rd_regb(port, S3C2410_URXH);
2010}
2011
2012static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2013 unsigned char c)
2014{
2015 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2016 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2017
2018
2019 if (!s3c24xx_port_configured(ucon))
2020 return;
2021
2022 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2023 cpu_relax();
2024 wr_regb(port, S3C2410_UTXH, c);
2025}
2026
2027#endif
2028
2029static void
2030s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2031{
2032 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2033
2034 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2035 cpu_relax();
2036 wr_regb(port, S3C2410_UTXH, ch);
2037}
2038
2039static void
2040s3c24xx_serial_console_write(struct console *co, const char *s,
2041 unsigned int count)
2042{
2043 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2044
2045
2046 if (!s3c24xx_port_configured(ucon))
2047 return;
2048
2049 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2050}
2051
2052static void __init
2053s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2054 int *parity, int *bits)
2055{
2056 struct clk *clk;
2057 unsigned int ulcon;
2058 unsigned int ucon;
2059 unsigned int ubrdiv;
2060 unsigned long rate;
2061 unsigned int clk_sel;
2062 char clk_name[MAX_CLK_NAME_LENGTH];
2063
2064 ulcon = rd_regl(port, S3C2410_ULCON);
2065 ucon = rd_regl(port, S3C2410_UCON);
2066 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2067
2068 dbg("s3c24xx_serial_get_options: port=%p\n"
2069 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2070 port, ulcon, ucon, ubrdiv);
2071
2072 if (s3c24xx_port_configured(ucon)) {
2073 switch (ulcon & S3C2410_LCON_CSMASK) {
2074 case S3C2410_LCON_CS5:
2075 *bits = 5;
2076 break;
2077 case S3C2410_LCON_CS6:
2078 *bits = 6;
2079 break;
2080 case S3C2410_LCON_CS7:
2081 *bits = 7;
2082 break;
2083 case S3C2410_LCON_CS8:
2084 default:
2085 *bits = 8;
2086 break;
2087 }
2088
2089 switch (ulcon & S3C2410_LCON_PMASK) {
2090 case S3C2410_LCON_PEVEN:
2091 *parity = 'e';
2092 break;
2093
2094 case S3C2410_LCON_PODD:
2095 *parity = 'o';
2096 break;
2097
2098 case S3C2410_LCON_PNONE:
2099 default:
2100 *parity = 'n';
2101 }
2102
2103
2104
2105 clk_sel = s3c24xx_serial_getsource(port);
2106 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2107
2108 clk = clk_get(port->dev, clk_name);
2109 if (!IS_ERR(clk))
2110 rate = clk_get_rate(clk);
2111 else
2112 rate = 1;
2113
2114 *baud = rate / (16 * (ubrdiv + 1));
2115 dbg("calculated baud %d\n", *baud);
2116 }
2117
2118}
2119
2120static int __init
2121s3c24xx_serial_console_setup(struct console *co, char *options)
2122{
2123 struct uart_port *port;
2124 int baud = 9600;
2125 int bits = 8;
2126 int parity = 'n';
2127 int flow = 'n';
2128
2129 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2130 co, co->index, options);
2131
2132
2133
2134 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2135 co->index = 0;
2136
2137 port = &s3c24xx_serial_ports[co->index].port;
2138
2139
2140
2141 if (port->mapbase == 0x0)
2142 return -ENODEV;
2143
2144 cons_uart = port;
2145
2146 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2147
2148
2149
2150
2151
2152
2153 if (options)
2154 uart_parse_options(options, &baud, &parity, &bits, &flow);
2155 else
2156 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2157
2158 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2159
2160 return uart_set_options(port, co, baud, parity, bits, flow);
2161}
2162
2163static struct console s3c24xx_serial_console = {
2164 .name = S3C24XX_SERIAL_NAME,
2165 .device = uart_console_device,
2166 .flags = CON_PRINTBUFFER,
2167 .index = -1,
2168 .write = s3c24xx_serial_console_write,
2169 .setup = s3c24xx_serial_console_setup,
2170 .data = &s3c24xx_uart_drv,
2171};
2172#endif
2173
2174#ifdef CONFIG_CPU_S3C2410
2175static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2176 .info = &(struct s3c24xx_uart_info) {
2177 .name = "Samsung S3C2410 UART",
2178 .type = PORT_S3C2410,
2179 .fifosize = 16,
2180 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2181 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2182 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2183 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2184 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2185 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2186 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2187 .num_clks = 2,
2188 .clksel_mask = S3C2410_UCON_CLKMASK,
2189 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2190 },
2191 .def_cfg = &(struct s3c2410_uartcfg) {
2192 .ucon = S3C2410_UCON_DEFAULT,
2193 .ufcon = S3C2410_UFCON_DEFAULT,
2194 },
2195};
2196#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2197#else
2198#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2199#endif
2200
2201#ifdef CONFIG_CPU_S3C2412
2202static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2203 .info = &(struct s3c24xx_uart_info) {
2204 .name = "Samsung S3C2412 UART",
2205 .type = PORT_S3C2412,
2206 .fifosize = 64,
2207 .has_divslot = 1,
2208 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2209 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2210 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2211 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2212 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2213 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2214 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2215 .num_clks = 4,
2216 .clksel_mask = S3C2412_UCON_CLKMASK,
2217 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2218 },
2219 .def_cfg = &(struct s3c2410_uartcfg) {
2220 .ucon = S3C2410_UCON_DEFAULT,
2221 .ufcon = S3C2410_UFCON_DEFAULT,
2222 },
2223};
2224#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2225#else
2226#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2227#endif
2228
2229#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2230 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2231static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2232 .info = &(struct s3c24xx_uart_info) {
2233 .name = "Samsung S3C2440 UART",
2234 .type = PORT_S3C2440,
2235 .fifosize = 64,
2236 .has_divslot = 1,
2237 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2238 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2239 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2240 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2241 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2242 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2243 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2244 .num_clks = 4,
2245 .clksel_mask = S3C2412_UCON_CLKMASK,
2246 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2247 },
2248 .def_cfg = &(struct s3c2410_uartcfg) {
2249 .ucon = S3C2410_UCON_DEFAULT,
2250 .ufcon = S3C2410_UFCON_DEFAULT,
2251 },
2252};
2253#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2254#else
2255#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2256#endif
2257
2258#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2259static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2260 .info = &(struct s3c24xx_uart_info) {
2261 .name = "Samsung S3C6400 UART",
2262 .type = PORT_S3C6400,
2263 .fifosize = 64,
2264 .has_divslot = 1,
2265 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2266 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2267 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2268 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2269 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2270 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2271 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2272 .num_clks = 4,
2273 .clksel_mask = S3C6400_UCON_CLKMASK,
2274 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2275 },
2276 .def_cfg = &(struct s3c2410_uartcfg) {
2277 .ucon = S3C2410_UCON_DEFAULT,
2278 .ufcon = S3C2410_UFCON_DEFAULT,
2279 },
2280};
2281#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2282#else
2283#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2284#endif
2285
2286#ifdef CONFIG_CPU_S5PV210
2287static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2288 .info = &(struct s3c24xx_uart_info) {
2289 .name = "Samsung S5PV210 UART",
2290 .type = PORT_S3C6400,
2291 .has_divslot = 1,
2292 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2293 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2294 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2295 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2296 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2297 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2298 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2299 .num_clks = 2,
2300 .clksel_mask = S5PV210_UCON_CLKMASK,
2301 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2302 },
2303 .def_cfg = &(struct s3c2410_uartcfg) {
2304 .ucon = S5PV210_UCON_DEFAULT,
2305 .ufcon = S5PV210_UFCON_DEFAULT,
2306 },
2307 .fifosize = { 256, 64, 16, 16 },
2308};
2309#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2310#else
2311#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2312#endif
2313
2314#if defined(CONFIG_ARCH_EXYNOS)
2315#define EXYNOS_COMMON_SERIAL_DRV_DATA \
2316 .info = &(struct s3c24xx_uart_info) { \
2317 .name = "Samsung Exynos UART", \
2318 .type = PORT_S3C6400, \
2319 .has_divslot = 1, \
2320 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2321 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2322 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2323 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2324 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2325 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2326 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2327 .num_clks = 1, \
2328 .clksel_mask = 0, \
2329 .clksel_shift = 0, \
2330 }, \
2331 .def_cfg = &(struct s3c2410_uartcfg) { \
2332 .ucon = S5PV210_UCON_DEFAULT, \
2333 .ufcon = S5PV210_UFCON_DEFAULT, \
2334 .has_fracval = 1, \
2335 } \
2336
2337static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2338 EXYNOS_COMMON_SERIAL_DRV_DATA,
2339 .fifosize = { 256, 64, 16, 16 },
2340};
2341
2342static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2343 EXYNOS_COMMON_SERIAL_DRV_DATA,
2344 .fifosize = { 64, 256, 16, 256 },
2345};
2346
2347#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2348#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2349#else
2350#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2351#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2352#endif
2353
2354static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2355 {
2356 .name = "s3c2410-uart",
2357 .driver_data = S3C2410_SERIAL_DRV_DATA,
2358 }, {
2359 .name = "s3c2412-uart",
2360 .driver_data = S3C2412_SERIAL_DRV_DATA,
2361 }, {
2362 .name = "s3c2440-uart",
2363 .driver_data = S3C2440_SERIAL_DRV_DATA,
2364 }, {
2365 .name = "s3c6400-uart",
2366 .driver_data = S3C6400_SERIAL_DRV_DATA,
2367 }, {
2368 .name = "s5pv210-uart",
2369 .driver_data = S5PV210_SERIAL_DRV_DATA,
2370 }, {
2371 .name = "exynos4210-uart",
2372 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
2373 }, {
2374 .name = "exynos5433-uart",
2375 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
2376 },
2377 { },
2378};
2379MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2380
2381#ifdef CONFIG_OF
2382static const struct of_device_id s3c24xx_uart_dt_match[] = {
2383 { .compatible = "samsung,s3c2410-uart",
2384 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2385 { .compatible = "samsung,s3c2412-uart",
2386 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2387 { .compatible = "samsung,s3c2440-uart",
2388 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2389 { .compatible = "samsung,s3c6400-uart",
2390 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2391 { .compatible = "samsung,s5pv210-uart",
2392 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2393 { .compatible = "samsung,exynos4210-uart",
2394 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2395 { .compatible = "samsung,exynos5433-uart",
2396 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2397 {},
2398};
2399MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2400#endif
2401
2402static struct platform_driver samsung_serial_driver = {
2403 .probe = s3c24xx_serial_probe,
2404 .remove = s3c24xx_serial_remove,
2405 .id_table = s3c24xx_serial_driver_ids,
2406 .driver = {
2407 .name = "samsung-uart",
2408 .pm = SERIAL_SAMSUNG_PM_OPS,
2409 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2410 },
2411};
2412
2413module_platform_driver(samsung_serial_driver);
2414
2415#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2416
2417
2418
2419
2420struct samsung_early_console_data {
2421 u32 txfull_mask;
2422};
2423
2424static void samsung_early_busyuart(struct uart_port *port)
2425{
2426 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2427 ;
2428}
2429
2430static void samsung_early_busyuart_fifo(struct uart_port *port)
2431{
2432 struct samsung_early_console_data *data = port->private_data;
2433
2434 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2435 ;
2436}
2437
2438static void samsung_early_putc(struct uart_port *port, int c)
2439{
2440 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2441 samsung_early_busyuart_fifo(port);
2442 else
2443 samsung_early_busyuart(port);
2444
2445 writeb(c, port->membase + S3C2410_UTXH);
2446}
2447
2448static void samsung_early_write(struct console *con, const char *s, unsigned n)
2449{
2450 struct earlycon_device *dev = con->data;
2451
2452 uart_console_write(&dev->port, s, n, samsung_early_putc);
2453}
2454
2455static int __init samsung_early_console_setup(struct earlycon_device *device,
2456 const char *opt)
2457{
2458 if (!device->port.membase)
2459 return -ENODEV;
2460
2461 device->con->write = samsung_early_write;
2462 return 0;
2463}
2464
2465
2466static struct samsung_early_console_data s3c2410_early_console_data = {
2467 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2468};
2469
2470static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2471 const char *opt)
2472{
2473 device->port.private_data = &s3c2410_early_console_data;
2474 return samsung_early_console_setup(device, opt);
2475}
2476OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2477 s3c2410_early_console_setup);
2478EARLYCON_DECLARE(s3c2410, s3c2410_early_console_setup);
2479
2480
2481static struct samsung_early_console_data s3c2440_early_console_data = {
2482 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2483};
2484
2485static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2486 const char *opt)
2487{
2488 device->port.private_data = &s3c2440_early_console_data;
2489 return samsung_early_console_setup(device, opt);
2490}
2491OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2492 s3c2440_early_console_setup);
2493OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2494 s3c2440_early_console_setup);
2495OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2496 s3c2440_early_console_setup);
2497EARLYCON_DECLARE(s3c2412, s3c2440_early_console_setup);
2498EARLYCON_DECLARE(s3c2440, s3c2440_early_console_setup);
2499EARLYCON_DECLARE(s3c6400, s3c2440_early_console_setup);
2500
2501
2502static struct samsung_early_console_data s5pv210_early_console_data = {
2503 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2504};
2505
2506static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2507 const char *opt)
2508{
2509 device->port.private_data = &s5pv210_early_console_data;
2510 return samsung_early_console_setup(device, opt);
2511}
2512OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2513 s5pv210_early_console_setup);
2514OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2515 s5pv210_early_console_setup);
2516EARLYCON_DECLARE(s5pv210, s5pv210_early_console_setup);
2517EARLYCON_DECLARE(exynos4210, s5pv210_early_console_setup);
2518#endif
2519
2520MODULE_ALIAS("platform:samsung-uart");
2521MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2522MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2523MODULE_LICENSE("GPL v2");
2524
