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19#ifndef __LINUX_EHCI_HCD_H
20#define __LINUX_EHCI_HCD_H
21
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30
31
32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33typedef __u32 __bitwise __hc32;
34typedef __u16 __bitwise __hc16;
35#else
36#define __hc32 __le32
37#define __hc16 __le16
38#endif
39
40
41#ifdef CONFIG_DYNAMIC_DEBUG
42#define EHCI_STATS
43#endif
44
45struct ehci_stats {
46
47 unsigned long normal;
48 unsigned long error;
49 unsigned long iaa;
50 unsigned long lost_iaa;
51
52
53 unsigned long complete;
54 unsigned long unlink;
55};
56
57
58
59
60
61struct ehci_per_sched {
62 struct usb_device *udev;
63 struct usb_host_endpoint *ep;
64 struct list_head ps_list;
65 u16 tt_usecs;
66 u16 cs_mask;
67 u16 period;
68 u16 phase;
69 u8 bw_phase;
70
71 u8 phase_uf;
72 u8 usecs, c_usecs;
73 u8 bw_uperiod;
74
75 u8 bw_period;
76};
77#define NO_FRAME 29999
78
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86
87
88
89#define EHCI_MAX_ROOT_PORTS 15
90
91
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93
94
95enum ehci_rh_state {
96 EHCI_RH_HALTED,
97 EHCI_RH_SUSPENDED,
98 EHCI_RH_RUNNING,
99 EHCI_RH_STOPPING
100};
101
102
103
104
105
106
107enum ehci_hrtimer_event {
108 EHCI_HRTIMER_POLL_ASS,
109 EHCI_HRTIMER_POLL_PSS,
110 EHCI_HRTIMER_POLL_DEAD,
111 EHCI_HRTIMER_UNLINK_INTR,
112 EHCI_HRTIMER_FREE_ITDS,
113 EHCI_HRTIMER_START_UNLINK_INTR,
114 EHCI_HRTIMER_ASYNC_UNLINKS,
115 EHCI_HRTIMER_IAA_WATCHDOG,
116 EHCI_HRTIMER_DISABLE_PERIODIC,
117 EHCI_HRTIMER_DISABLE_ASYNC,
118 EHCI_HRTIMER_IO_WATCHDOG,
119 EHCI_HRTIMER_NUM_EVENTS
120};
121#define EHCI_HRTIMER_NO_EVENT 99
122
123struct ehci_hcd {
124
125 enum ehci_hrtimer_event next_hrtimer_event;
126 unsigned enabled_hrtimer_events;
127 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
128 struct hrtimer hrtimer;
129
130 int PSS_poll_count;
131 int ASS_poll_count;
132 int died_poll_count;
133
134
135 struct ehci_caps __iomem *caps;
136 struct ehci_regs __iomem *regs;
137 struct ehci_dbg_port __iomem *debug;
138
139 __u32 hcs_params;
140 spinlock_t lock;
141 enum ehci_rh_state rh_state;
142
143
144 bool scanning:1;
145 bool need_rescan:1;
146 bool intr_unlinking:1;
147 bool iaa_in_progress:1;
148 bool async_unlinking:1;
149 bool shutdown:1;
150 struct ehci_qh *qh_scan_next;
151
152
153 struct ehci_qh *async;
154 struct ehci_qh *dummy;
155 struct list_head async_unlink;
156 struct list_head async_idle;
157 unsigned async_unlink_cycle;
158 unsigned async_count;
159
160
161#define DEFAULT_I_TDPS 1024
162 unsigned periodic_size;
163 __hc32 *periodic;
164 dma_addr_t periodic_dma;
165 struct list_head intr_qh_list;
166 unsigned i_thresh;
167
168 union ehci_shadow *pshadow;
169 struct list_head intr_unlink_wait;
170 struct list_head intr_unlink;
171 unsigned intr_unlink_wait_cycle;
172 unsigned intr_unlink_cycle;
173 unsigned now_frame;
174 unsigned last_iso_frame;
175 unsigned intr_count;
176 unsigned isoc_count;
177 unsigned periodic_count;
178 unsigned uframe_periodic_max;
179
180
181
182 struct list_head cached_itd_list;
183 struct ehci_itd *last_itd_to_free;
184 struct list_head cached_sitd_list;
185 struct ehci_sitd *last_sitd_to_free;
186
187
188 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
189
190
191 unsigned long bus_suspended;
192
193 unsigned long companion_ports;
194
195 unsigned long owned_ports;
196
197 unsigned long port_c_suspend;
198
199 unsigned long suspended_ports;
200
201 unsigned long resuming_ports;
202
203
204
205 struct dma_pool *qh_pool;
206 struct dma_pool *qtd_pool;
207 struct dma_pool *itd_pool;
208 struct dma_pool *sitd_pool;
209
210 unsigned random_frame;
211 unsigned long next_statechange;
212 ktime_t last_periodic_enable;
213 u32 command;
214
215
216 unsigned no_selective_suspend:1;
217 unsigned has_fsl_port_bug:1;
218 unsigned has_fsl_hs_errata:1;
219 unsigned big_endian_mmio:1;
220 unsigned big_endian_desc:1;
221 unsigned big_endian_capbase:1;
222 unsigned has_amcc_usb23:1;
223 unsigned need_io_watchdog:1;
224 unsigned amd_pll_fix:1;
225 unsigned use_dummy_qh:1;
226 unsigned has_synopsys_hc_bug:1;
227 unsigned frame_index_bug:1;
228 unsigned need_oc_pp_cycle:1;
229 unsigned imx28_write_fix:1;
230
231
232 #define OHCI_CTRL_HCFS (3 << 6)
233 #define OHCI_USB_OPER (2 << 6)
234 #define OHCI_USB_SUSPEND (3 << 6)
235
236 #define OHCI_HCCTRL_OFFSET 0x4
237 #define OHCI_HCCTRL_LEN 0x4
238 __hc32 *ohci_hcctrl_reg;
239 unsigned has_hostpc:1;
240 unsigned has_tdi_phy_lpm:1;
241 unsigned has_ppcd:1;
242 u8 sbrn;
243
244
245#ifdef EHCI_STATS
246 struct ehci_stats stats;
247# define COUNT(x) do { (x)++; } while (0)
248#else
249# define COUNT(x) do {} while (0)
250#endif
251
252
253#ifdef CONFIG_DYNAMIC_DEBUG
254 struct dentry *debug_dir;
255#endif
256
257
258#define EHCI_BANDWIDTH_SIZE 64
259#define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3)
260 u8 bandwidth[EHCI_BANDWIDTH_SIZE];
261
262 u8 tt_budget[EHCI_BANDWIDTH_SIZE];
263
264 struct list_head tt_list;
265
266
267 unsigned long priv[0] __aligned(sizeof(s64));
268};
269
270
271static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
272{
273 return (struct ehci_hcd *) (hcd->hcd_priv);
274}
275static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
276{
277 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
278}
279
280
281
282#include <linux/usb/ehci_def.h>
283
284
285
286#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
287
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295
296struct ehci_qtd {
297
298 __hc32 hw_next;
299 __hc32 hw_alt_next;
300 __hc32 hw_token;
301#define QTD_TOGGLE (1 << 31)
302#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
303#define QTD_IOC (1 << 15)
304#define QTD_CERR(tok) (((tok)>>10) & 0x3)
305#define QTD_PID(tok) (((tok)>>8) & 0x3)
306#define QTD_STS_ACTIVE (1 << 7)
307#define QTD_STS_HALT (1 << 6)
308#define QTD_STS_DBE (1 << 5)
309#define QTD_STS_BABBLE (1 << 4)
310#define QTD_STS_XACT (1 << 3)
311#define QTD_STS_MMF (1 << 2)
312#define QTD_STS_STS (1 << 1)
313#define QTD_STS_PING (1 << 0)
314
315#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
316#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
317#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
318
319 __hc32 hw_buf [5];
320 __hc32 hw_buf_hi [5];
321
322
323 dma_addr_t qtd_dma;
324 struct list_head qtd_list;
325 struct urb *urb;
326 size_t length;
327} __attribute__ ((aligned (32)));
328
329
330#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
331
332#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
333
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335
336
337#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
338
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346
347#define Q_TYPE_ITD (0 << 1)
348#define Q_TYPE_QH (1 << 1)
349#define Q_TYPE_SITD (2 << 1)
350#define Q_TYPE_FSTN (3 << 1)
351
352
353#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
354
355
356#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1)
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365
366union ehci_shadow {
367 struct ehci_qh *qh;
368 struct ehci_itd *itd;
369 struct ehci_sitd *sitd;
370 struct ehci_fstn *fstn;
371 __hc32 *hw_next;
372 void *ptr;
373};
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386struct ehci_qh_hw {
387 __hc32 hw_next;
388 __hc32 hw_info1;
389#define QH_CONTROL_EP (1 << 27)
390#define QH_HEAD (1 << 15)
391#define QH_TOGGLE_CTL (1 << 14)
392#define QH_HIGH_SPEED (2 << 12)
393#define QH_LOW_SPEED (1 << 12)
394#define QH_FULL_SPEED (0 << 12)
395#define QH_INACTIVATE (1 << 7)
396 __hc32 hw_info2;
397#define QH_SMASK 0x000000ff
398#define QH_CMASK 0x0000ff00
399#define QH_HUBADDR 0x007f0000
400#define QH_HUBPORT 0x3f800000
401#define QH_MULT 0xc0000000
402 __hc32 hw_current;
403
404
405 __hc32 hw_qtd_next;
406 __hc32 hw_alt_next;
407 __hc32 hw_token;
408 __hc32 hw_buf [5];
409 __hc32 hw_buf_hi [5];
410} __attribute__ ((aligned(32)));
411
412struct ehci_qh {
413 struct ehci_qh_hw *hw;
414
415 dma_addr_t qh_dma;
416 union ehci_shadow qh_next;
417 struct list_head qtd_list;
418 struct list_head intr_node;
419 struct ehci_qtd *dummy;
420 struct list_head unlink_node;
421 struct ehci_per_sched ps;
422
423 unsigned unlink_cycle;
424
425 u8 qh_state;
426#define QH_STATE_LINKED 1
427#define QH_STATE_UNLINK 2
428#define QH_STATE_IDLE 3
429#define QH_STATE_UNLINK_WAIT 4
430#define QH_STATE_COMPLETING 5
431
432 u8 xacterrs;
433#define QH_XACTERR_MAX 32
434
435 u8 gap_uf;
436
437 unsigned is_out:1;
438 unsigned clearing_tt:1;
439 unsigned dequeue_during_giveback:1;
440 unsigned exception:1;
441
442};
443
444
445
446
447struct ehci_iso_packet {
448
449 u64 bufp;
450 __hc32 transaction;
451 u8 cross;
452
453 u32 buf1;
454};
455
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458
459
460struct ehci_iso_sched {
461 struct list_head td_list;
462 unsigned span;
463 unsigned first_packet;
464 struct ehci_iso_packet packet [0];
465};
466
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470
471struct ehci_iso_stream {
472
473 struct ehci_qh_hw *hw;
474
475 u8 bEndpointAddress;
476 u8 highspeed;
477 struct list_head td_list;
478 struct list_head free_list;
479
480
481 struct ehci_per_sched ps;
482 unsigned next_uframe;
483 __hc32 splits;
484
485
486
487
488 u16 uperiod;
489 u16 maxp;
490 unsigned bandwidth;
491
492
493 __hc32 buf0;
494 __hc32 buf1;
495 __hc32 buf2;
496
497
498 __hc32 address;
499};
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508
509struct ehci_itd {
510
511 __hc32 hw_next;
512 __hc32 hw_transaction [8];
513#define EHCI_ISOC_ACTIVE (1<<31)
514#define EHCI_ISOC_BUF_ERR (1<<30)
515#define EHCI_ISOC_BABBLE (1<<29)
516#define EHCI_ISOC_XACTERR (1<<28)
517#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
518#define EHCI_ITD_IOC (1 << 15)
519
520#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
521
522 __hc32 hw_bufp [7];
523 __hc32 hw_bufp_hi [7];
524
525
526 dma_addr_t itd_dma;
527 union ehci_shadow itd_next;
528
529 struct urb *urb;
530 struct ehci_iso_stream *stream;
531 struct list_head itd_list;
532
533
534 unsigned frame;
535 unsigned pg;
536 unsigned index[8];
537} __attribute__ ((aligned (32)));
538
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546
547struct ehci_sitd {
548
549 __hc32 hw_next;
550
551 __hc32 hw_fullspeed_ep;
552 __hc32 hw_uframe;
553 __hc32 hw_results;
554#define SITD_IOC (1 << 31)
555#define SITD_PAGE (1 << 30)
556#define SITD_LENGTH(x) (0x3ff & ((x)>>16))
557#define SITD_STS_ACTIVE (1 << 7)
558#define SITD_STS_ERR (1 << 6)
559#define SITD_STS_DBE (1 << 5)
560#define SITD_STS_BABBLE (1 << 4)
561#define SITD_STS_XACT (1 << 3)
562#define SITD_STS_MMF (1 << 2)
563#define SITD_STS_STS (1 << 1)
564
565#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
566
567 __hc32 hw_buf [2];
568 __hc32 hw_backpointer;
569 __hc32 hw_buf_hi [2];
570
571
572 dma_addr_t sitd_dma;
573 union ehci_shadow sitd_next;
574
575 struct urb *urb;
576 struct ehci_iso_stream *stream;
577 struct list_head sitd_list;
578 unsigned frame;
579 unsigned index;
580} __attribute__ ((aligned (32)));
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592
593struct ehci_fstn {
594 __hc32 hw_next;
595 __hc32 hw_prev;
596
597
598 dma_addr_t fstn_dma;
599 union ehci_shadow fstn_next;
600} __attribute__ ((aligned (32)));
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621
622struct ehci_tt {
623 u16 bandwidth[EHCI_BANDWIDTH_FRAMES];
624
625 struct list_head tt_list;
626 struct list_head ps_list;
627 struct usb_tt *usb_tt;
628 int tt_port;
629};
630
631
632
633
634
635#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
636 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
637
638#define ehci_prepare_ports_for_controller_resume(ehci) \
639 ehci_adjust_port_wakeup_flags(ehci, false, false);
640
641
642
643#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
644
645
646
647
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649
650
651
652#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
653
654
655static inline unsigned int
656ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
657{
658 if (ehci_is_TDI(ehci)) {
659 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
660 case 0:
661 return 0;
662 case 1:
663 return USB_PORT_STAT_LOW_SPEED;
664 case 2:
665 default:
666 return USB_PORT_STAT_HIGH_SPEED;
667 }
668 }
669 return USB_PORT_STAT_HIGH_SPEED;
670}
671
672#else
673
674#define ehci_is_TDI(e) (0)
675
676#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
677#endif
678
679
680
681#ifdef CONFIG_PPC_83xx
682
683
684
685#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
686#else
687#define ehci_has_fsl_portno_bug(e) (0)
688#endif
689
690#define PORTSC_FSL_PFSC 24
691
692#if defined(CONFIG_PPC_85xx)
693
694
695
696#define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
697#else
698#define ehci_has_fsl_hs_errata(e) (0)
699#endif
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714
715#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
716#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
717#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
718#else
719#define ehci_big_endian_mmio(e) 0
720#define ehci_big_endian_capbase(e) 0
721#endif
722
723
724
725
726
727#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
728#define readl_be(addr) __raw_readl((__force unsigned *)addr)
729#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
730#endif
731
732static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
733 __u32 __iomem * regs)
734{
735#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
736 return ehci_big_endian_mmio(ehci) ?
737 readl_be(regs) :
738 readl(regs);
739#else
740 return readl(regs);
741#endif
742}
743
744#ifdef CONFIG_SOC_IMX28
745static inline void imx28_ehci_writel(const unsigned int val,
746 volatile __u32 __iomem *addr)
747{
748 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
749}
750#else
751static inline void imx28_ehci_writel(const unsigned int val,
752 volatile __u32 __iomem *addr)
753{
754}
755#endif
756static inline void ehci_writel(const struct ehci_hcd *ehci,
757 const unsigned int val, __u32 __iomem *regs)
758{
759#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
760 ehci_big_endian_mmio(ehci) ?
761 writel_be(val, regs) :
762 writel(val, regs);
763#else
764 if (ehci->imx28_write_fix)
765 imx28_ehci_writel(val, regs);
766 else
767 writel(val, regs);
768#endif
769}
770
771
772
773
774
775
776#ifdef CONFIG_44x
777static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
778{
779 u32 hc_control;
780
781 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
782 if (operational)
783 hc_control |= OHCI_USB_OPER;
784 else
785 hc_control |= OHCI_USB_SUSPEND;
786
787 writel_be(hc_control, ehci->ohci_hcctrl_reg);
788 (void) readl_be(ehci->ohci_hcctrl_reg);
789}
790#else
791static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
792{ }
793#endif
794
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802
803
804#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
805#define ehci_big_endian_desc(e) ((e)->big_endian_desc)
806
807
808static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
809{
810 return ehci_big_endian_desc(ehci)
811 ? (__force __hc32)cpu_to_be32(x)
812 : (__force __hc32)cpu_to_le32(x);
813}
814
815
816static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
817{
818 return ehci_big_endian_desc(ehci)
819 ? be32_to_cpu((__force __be32)x)
820 : le32_to_cpu((__force __le32)x);
821}
822
823static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
824{
825 return ehci_big_endian_desc(ehci)
826 ? be32_to_cpup((__force __be32 *)x)
827 : le32_to_cpup((__force __le32 *)x);
828}
829
830#else
831
832
833static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
834{
835 return cpu_to_le32(x);
836}
837
838
839static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
840{
841 return le32_to_cpu(x);
842}
843
844static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
845{
846 return le32_to_cpup(x);
847}
848
849#endif
850
851
852
853#define ehci_dbg(ehci, fmt, args...) \
854 dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
855#define ehci_err(ehci, fmt, args...) \
856 dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
857#define ehci_info(ehci, fmt, args...) \
858 dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
859#define ehci_warn(ehci, fmt, args...) \
860 dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
861
862
863#ifndef CONFIG_DYNAMIC_DEBUG
864#define STUB_DEBUG_FILES
865#endif
866
867
868
869
870
871struct ehci_driver_overrides {
872 size_t extra_priv_size;
873 int (*reset)(struct usb_hcd *hcd);
874 int (*port_power)(struct usb_hcd *hcd,
875 int portnum, bool enable);
876};
877
878extern void ehci_init_driver(struct hc_driver *drv,
879 const struct ehci_driver_overrides *over);
880extern int ehci_setup(struct usb_hcd *hcd);
881extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
882 u32 mask, u32 done, int usec);
883extern int ehci_reset(struct ehci_hcd *ehci);
884
885#ifdef CONFIG_PM
886extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
887extern int ehci_resume(struct usb_hcd *hcd, bool force_reset);
888extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
889 bool suspending, bool do_wakeup);
890#endif
891
892extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
893 u16 wIndex, char *buf, u16 wLength);
894
895#endif
896