linux/drivers/usb/host/ehci.h
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   1/*
   2 * Copyright (c) 2001-2002 by David Brownell
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms of the GNU General Public License as published by the
   6 * Free Software Foundation; either version 2 of the License, or (at your
   7 * option) any later version.
   8 *
   9 * This program is distributed in the hope that it will be useful, but
  10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 * for more details.
  13 *
  14 * You should have received a copy of the GNU General Public License
  15 * along with this program; if not, write to the Free Software Foundation,
  16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17 */
  18
  19#ifndef __LINUX_EHCI_HCD_H
  20#define __LINUX_EHCI_HCD_H
  21
  22/* definitions used for the EHCI driver */
  23
  24/*
  25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  27 * the host controller implementation.
  28 *
  29 * To facilitate the strongest possible byte-order checking from "sparse"
  30 * and so on, we use __leXX unless that's not practical.
  31 */
  32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  33typedef __u32 __bitwise __hc32;
  34typedef __u16 __bitwise __hc16;
  35#else
  36#define __hc32  __le32
  37#define __hc16  __le16
  38#endif
  39
  40/* statistics can be kept for tuning/monitoring */
  41#ifdef CONFIG_DYNAMIC_DEBUG
  42#define EHCI_STATS
  43#endif
  44
  45struct ehci_stats {
  46        /* irq usage */
  47        unsigned long           normal;
  48        unsigned long           error;
  49        unsigned long           iaa;
  50        unsigned long           lost_iaa;
  51
  52        /* termination of urbs from core */
  53        unsigned long           complete;
  54        unsigned long           unlink;
  55};
  56
  57/*
  58 * Scheduling and budgeting information for periodic transfers, for both
  59 * high-speed devices and full/low-speed devices lying behind a TT.
  60 */
  61struct ehci_per_sched {
  62        struct usb_device       *udev;          /* access to the TT */
  63        struct usb_host_endpoint *ep;
  64        struct list_head        ps_list;        /* node on ehci_tt's ps_list */
  65        u16                     tt_usecs;       /* time on the FS/LS bus */
  66        u16                     cs_mask;        /* C-mask and S-mask bytes */
  67        u16                     period;         /* actual period in frames */
  68        u16                     phase;          /* actual phase, frame part */
  69        u8                      bw_phase;       /* same, for bandwidth
  70                                                   reservation */
  71        u8                      phase_uf;       /* uframe part of the phase */
  72        u8                      usecs, c_usecs; /* times on the HS bus */
  73        u8                      bw_uperiod;     /* period in microframes, for
  74                                                   bandwidth reservation */
  75        u8                      bw_period;      /* same, in frames */
  76};
  77#define NO_FRAME        29999                   /* frame not assigned yet */
  78
  79/* ehci_hcd->lock guards shared data against other CPUs:
  80 *   ehci_hcd:  async, unlink, periodic (and shadow), ...
  81 *   usb_host_endpoint: hcpriv
  82 *   ehci_qh:   qh_next, qtd_list
  83 *   ehci_qtd:  qtd_list
  84 *
  85 * Also, hold this lock when talking to HC registers or
  86 * when updating hw_* fields in shared qh/qtd/... structures.
  87 */
  88
  89#define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  90
  91/*
  92 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
  93 * controller may be doing DMA.  Lower values mean there's no DMA.
  94 */
  95enum ehci_rh_state {
  96        EHCI_RH_HALTED,
  97        EHCI_RH_SUSPENDED,
  98        EHCI_RH_RUNNING,
  99        EHCI_RH_STOPPING
 100};
 101
 102/*
 103 * Timer events, ordered by increasing delay length.
 104 * Always update event_delays_ns[] and event_handlers[] (defined in
 105 * ehci-timer.c) in parallel with this list.
 106 */
 107enum ehci_hrtimer_event {
 108        EHCI_HRTIMER_POLL_ASS,          /* Poll for async schedule off */
 109        EHCI_HRTIMER_POLL_PSS,          /* Poll for periodic schedule off */
 110        EHCI_HRTIMER_POLL_DEAD,         /* Wait for dead controller to stop */
 111        EHCI_HRTIMER_UNLINK_INTR,       /* Wait for interrupt QH unlink */
 112        EHCI_HRTIMER_FREE_ITDS,         /* Wait for unused iTDs and siTDs */
 113        EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
 114        EHCI_HRTIMER_ASYNC_UNLINKS,     /* Unlink empty async QHs */
 115        EHCI_HRTIMER_IAA_WATCHDOG,      /* Handle lost IAA interrupts */
 116        EHCI_HRTIMER_DISABLE_PERIODIC,  /* Wait to disable periodic sched */
 117        EHCI_HRTIMER_DISABLE_ASYNC,     /* Wait to disable async sched */
 118        EHCI_HRTIMER_IO_WATCHDOG,       /* Check for missing IRQs */
 119        EHCI_HRTIMER_NUM_EVENTS         /* Must come last */
 120};
 121#define EHCI_HRTIMER_NO_EVENT   99
 122
 123struct ehci_hcd {                       /* one per controller */
 124        /* timing support */
 125        enum ehci_hrtimer_event next_hrtimer_event;
 126        unsigned                enabled_hrtimer_events;
 127        ktime_t                 hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
 128        struct hrtimer          hrtimer;
 129
 130        int                     PSS_poll_count;
 131        int                     ASS_poll_count;
 132        int                     died_poll_count;
 133
 134        /* glue to PCI and HCD framework */
 135        struct ehci_caps __iomem *caps;
 136        struct ehci_regs __iomem *regs;
 137        struct ehci_dbg_port __iomem *debug;
 138
 139        __u32                   hcs_params;     /* cached register copy */
 140        spinlock_t              lock;
 141        enum ehci_rh_state      rh_state;
 142
 143        /* general schedule support */
 144        bool                    scanning:1;
 145        bool                    need_rescan:1;
 146        bool                    intr_unlinking:1;
 147        bool                    iaa_in_progress:1;
 148        bool                    async_unlinking:1;
 149        bool                    shutdown:1;
 150        struct ehci_qh          *qh_scan_next;
 151
 152        /* async schedule support */
 153        struct ehci_qh          *async;
 154        struct ehci_qh          *dummy;         /* For AMD quirk use */
 155        struct list_head        async_unlink;
 156        struct list_head        async_idle;
 157        unsigned                async_unlink_cycle;
 158        unsigned                async_count;    /* async activity count */
 159
 160        /* periodic schedule support */
 161#define DEFAULT_I_TDPS          1024            /* some HCs can do less */
 162        unsigned                periodic_size;
 163        __hc32                  *periodic;      /* hw periodic table */
 164        dma_addr_t              periodic_dma;
 165        struct list_head        intr_qh_list;
 166        unsigned                i_thresh;       /* uframes HC might cache */
 167
 168        union ehci_shadow       *pshadow;       /* mirror hw periodic table */
 169        struct list_head        intr_unlink_wait;
 170        struct list_head        intr_unlink;
 171        unsigned                intr_unlink_wait_cycle;
 172        unsigned                intr_unlink_cycle;
 173        unsigned                now_frame;      /* frame from HC hardware */
 174        unsigned                last_iso_frame; /* last frame scanned for iso */
 175        unsigned                intr_count;     /* intr activity count */
 176        unsigned                isoc_count;     /* isoc activity count */
 177        unsigned                periodic_count; /* periodic activity count */
 178        unsigned                uframe_periodic_max; /* max periodic time per uframe */
 179
 180
 181        /* list of itds & sitds completed while now_frame was still active */
 182        struct list_head        cached_itd_list;
 183        struct ehci_itd         *last_itd_to_free;
 184        struct list_head        cached_sitd_list;
 185        struct ehci_sitd        *last_sitd_to_free;
 186
 187        /* per root hub port */
 188        unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
 189
 190        /* bit vectors (one bit per port) */
 191        unsigned long           bus_suspended;          /* which ports were
 192                        already suspended at the start of a bus suspend */
 193        unsigned long           companion_ports;        /* which ports are
 194                        dedicated to the companion controller */
 195        unsigned long           owned_ports;            /* which ports are
 196                        owned by the companion during a bus suspend */
 197        unsigned long           port_c_suspend;         /* which ports have
 198                        the change-suspend feature turned on */
 199        unsigned long           suspended_ports;        /* which ports are
 200                        suspended */
 201        unsigned long           resuming_ports;         /* which ports have
 202                        started to resume */
 203
 204        /* per-HC memory pools (could be per-bus, but ...) */
 205        struct dma_pool         *qh_pool;       /* qh per active urb */
 206        struct dma_pool         *qtd_pool;      /* one or more per qh */
 207        struct dma_pool         *itd_pool;      /* itd per iso urb */
 208        struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 209
 210        unsigned                random_frame;
 211        unsigned long           next_statechange;
 212        ktime_t                 last_periodic_enable;
 213        u32                     command;
 214
 215        /* SILICON QUIRKS */
 216        unsigned                no_selective_suspend:1;
 217        unsigned                has_fsl_port_bug:1; /* FreeScale */
 218        unsigned                has_fsl_hs_errata:1;    /* Freescale HS quirk */
 219        unsigned                big_endian_mmio:1;
 220        unsigned                big_endian_desc:1;
 221        unsigned                big_endian_capbase:1;
 222        unsigned                has_amcc_usb23:1;
 223        unsigned                need_io_watchdog:1;
 224        unsigned                amd_pll_fix:1;
 225        unsigned                use_dummy_qh:1; /* AMD Frame List table quirk*/
 226        unsigned                has_synopsys_hc_bug:1; /* Synopsys HC */
 227        unsigned                frame_index_bug:1; /* MosChip (AKA NetMos) */
 228        unsigned                need_oc_pp_cycle:1; /* MPC834X port power */
 229        unsigned                imx28_write_fix:1; /* For Freescale i.MX28 */
 230
 231        /* required for usb32 quirk */
 232        #define OHCI_CTRL_HCFS          (3 << 6)
 233        #define OHCI_USB_OPER           (2 << 6)
 234        #define OHCI_USB_SUSPEND        (3 << 6)
 235
 236        #define OHCI_HCCTRL_OFFSET      0x4
 237        #define OHCI_HCCTRL_LEN         0x4
 238        __hc32                  *ohci_hcctrl_reg;
 239        unsigned                has_hostpc:1;
 240        unsigned                has_tdi_phy_lpm:1;
 241        unsigned                has_ppcd:1; /* support per-port change bits */
 242        u8                      sbrn;           /* packed release number */
 243
 244        /* irq statistics */
 245#ifdef EHCI_STATS
 246        struct ehci_stats       stats;
 247#       define COUNT(x) do { (x)++; } while (0)
 248#else
 249#       define COUNT(x) do {} while (0)
 250#endif
 251
 252        /* debug files */
 253#ifdef CONFIG_DYNAMIC_DEBUG
 254        struct dentry           *debug_dir;
 255#endif
 256
 257        /* bandwidth usage */
 258#define EHCI_BANDWIDTH_SIZE     64
 259#define EHCI_BANDWIDTH_FRAMES   (EHCI_BANDWIDTH_SIZE >> 3)
 260        u8                      bandwidth[EHCI_BANDWIDTH_SIZE];
 261                                                /* us allocated per uframe */
 262        u8                      tt_budget[EHCI_BANDWIDTH_SIZE];
 263                                                /* us budgeted per uframe */
 264        struct list_head        tt_list;
 265
 266        /* platform-specific data -- must come last */
 267        unsigned long           priv[0] __aligned(sizeof(s64));
 268};
 269
 270/* convert between an HCD pointer and the corresponding EHCI_HCD */
 271static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 272{
 273        return (struct ehci_hcd *) (hcd->hcd_priv);
 274}
 275static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 276{
 277        return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 278}
 279
 280/*-------------------------------------------------------------------------*/
 281
 282#include <linux/usb/ehci_def.h>
 283
 284/*-------------------------------------------------------------------------*/
 285
 286#define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 287
 288/*
 289 * EHCI Specification 0.95 Section 3.5
 290 * QTD: describe data transfer components (buffer, direction, ...)
 291 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 292 *
 293 * These are associated only with "QH" (Queue Head) structures,
 294 * used with control, bulk, and interrupt transfers.
 295 */
 296struct ehci_qtd {
 297        /* first part defined by EHCI spec */
 298        __hc32                  hw_next;        /* see EHCI 3.5.1 */
 299        __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 300        __hc32                  hw_token;       /* see EHCI 3.5.3 */
 301#define QTD_TOGGLE      (1 << 31)       /* data toggle */
 302#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 303#define QTD_IOC         (1 << 15)       /* interrupt on complete */
 304#define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 305#define QTD_PID(tok)    (((tok)>>8) & 0x3)
 306#define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 307#define QTD_STS_HALT    (1 << 6)        /* halted on error */
 308#define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 309#define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 310#define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 311#define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 312#define QTD_STS_STS     (1 << 1)        /* split transaction state */
 313#define QTD_STS_PING    (1 << 0)        /* issue PING? */
 314
 315#define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 316#define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 317#define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 318
 319        __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 320        __hc32                  hw_buf_hi [5];        /* Appendix B */
 321
 322        /* the rest is HCD-private */
 323        dma_addr_t              qtd_dma;                /* qtd address */
 324        struct list_head        qtd_list;               /* sw qtd list */
 325        struct urb              *urb;                   /* qtd's urb */
 326        size_t                  length;                 /* length of buffer */
 327} __attribute__ ((aligned (32)));
 328
 329/* mask NakCnt+T in qh->hw_alt_next */
 330#define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 331
 332#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 333
 334/*-------------------------------------------------------------------------*/
 335
 336/* type tag from {qh,itd,sitd,fstn}->hw_next */
 337#define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 338
 339/*
 340 * Now the following defines are not converted using the
 341 * cpu_to_le32() macro anymore, since we have to support
 342 * "dynamic" switching between be and le support, so that the driver
 343 * can be used on one system with SoC EHCI controller using big-endian
 344 * descriptors as well as a normal little-endian PCI EHCI controller.
 345 */
 346/* values for that type tag */
 347#define Q_TYPE_ITD      (0 << 1)
 348#define Q_TYPE_QH       (1 << 1)
 349#define Q_TYPE_SITD     (2 << 1)
 350#define Q_TYPE_FSTN     (3 << 1)
 351
 352/* next async queue entry, or pointer to interrupt/periodic QH */
 353#define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 354
 355/* for periodic/async schedules and qtd lists, mark end of list */
 356#define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 357
 358/*
 359 * Entries in periodic shadow table are pointers to one of four kinds
 360 * of data structure.  That's dictated by the hardware; a type tag is
 361 * encoded in the low bits of the hardware's periodic schedule.  Use
 362 * Q_NEXT_TYPE to get the tag.
 363 *
 364 * For entries in the async schedule, the type tag always says "qh".
 365 */
 366union ehci_shadow {
 367        struct ehci_qh          *qh;            /* Q_TYPE_QH */
 368        struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 369        struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 370        struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 371        __hc32                  *hw_next;       /* (all types) */
 372        void                    *ptr;
 373};
 374
 375/*-------------------------------------------------------------------------*/
 376
 377/*
 378 * EHCI Specification 0.95 Section 3.6
 379 * QH: describes control/bulk/interrupt endpoints
 380 * See Fig 3-7 "Queue Head Structure Layout".
 381 *
 382 * These appear in both the async and (for interrupt) periodic schedules.
 383 */
 384
 385/* first part defined by EHCI spec */
 386struct ehci_qh_hw {
 387        __hc32                  hw_next;        /* see EHCI 3.6.1 */
 388        __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 389#define QH_CONTROL_EP   (1 << 27)       /* FS/LS control endpoint */
 390#define QH_HEAD         (1 << 15)       /* Head of async reclamation list */
 391#define QH_TOGGLE_CTL   (1 << 14)       /* Data toggle control */
 392#define QH_HIGH_SPEED   (2 << 12)       /* Endpoint speed */
 393#define QH_LOW_SPEED    (1 << 12)
 394#define QH_FULL_SPEED   (0 << 12)
 395#define QH_INACTIVATE   (1 << 7)        /* Inactivate on next transaction */
 396        __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 397#define QH_SMASK        0x000000ff
 398#define QH_CMASK        0x0000ff00
 399#define QH_HUBADDR      0x007f0000
 400#define QH_HUBPORT      0x3f800000
 401#define QH_MULT         0xc0000000
 402        __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 403
 404        /* qtd overlay (hardware parts of a struct ehci_qtd) */
 405        __hc32                  hw_qtd_next;
 406        __hc32                  hw_alt_next;
 407        __hc32                  hw_token;
 408        __hc32                  hw_buf [5];
 409        __hc32                  hw_buf_hi [5];
 410} __attribute__ ((aligned(32)));
 411
 412struct ehci_qh {
 413        struct ehci_qh_hw       *hw;            /* Must come first */
 414        /* the rest is HCD-private */
 415        dma_addr_t              qh_dma;         /* address of qh */
 416        union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 417        struct list_head        qtd_list;       /* sw qtd list */
 418        struct list_head        intr_node;      /* list of intr QHs */
 419        struct ehci_qtd         *dummy;
 420        struct list_head        unlink_node;
 421        struct ehci_per_sched   ps;             /* scheduling info */
 422
 423        unsigned                unlink_cycle;
 424
 425        u8                      qh_state;
 426#define QH_STATE_LINKED         1               /* HC sees this */
 427#define QH_STATE_UNLINK         2               /* HC may still see this */
 428#define QH_STATE_IDLE           3               /* HC doesn't see this */
 429#define QH_STATE_UNLINK_WAIT    4               /* LINKED and on unlink q */
 430#define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 431
 432        u8                      xacterrs;       /* XactErr retry counter */
 433#define QH_XACTERR_MAX          32              /* XactErr retry limit */
 434
 435        u8                      gap_uf;         /* uframes split/csplit gap */
 436
 437        unsigned                is_out:1;       /* bulk or intr OUT */
 438        unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 439        unsigned                dequeue_during_giveback:1;
 440        unsigned                exception:1;    /* got a fault, or an unlink
 441                                                   was requested */
 442};
 443
 444/*-------------------------------------------------------------------------*/
 445
 446/* description of one iso transaction (up to 3 KB data if highspeed) */
 447struct ehci_iso_packet {
 448        /* These will be copied to iTD when scheduling */
 449        u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 450        __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 451        u8                      cross;          /* buf crosses pages */
 452        /* for full speed OUT splits */
 453        u32                     buf1;
 454};
 455
 456/* temporary schedule data for packets from iso urbs (both speeds)
 457 * each packet is one logical usb transaction to the device (not TT),
 458 * beginning at stream->next_uframe
 459 */
 460struct ehci_iso_sched {
 461        struct list_head        td_list;
 462        unsigned                span;
 463        unsigned                first_packet;
 464        struct ehci_iso_packet  packet [0];
 465};
 466
 467/*
 468 * ehci_iso_stream - groups all (s)itds for this endpoint.
 469 * acts like a qh would, if EHCI had them for ISO.
 470 */
 471struct ehci_iso_stream {
 472        /* first field matches ehci_hq, but is NULL */
 473        struct ehci_qh_hw       *hw;
 474
 475        u8                      bEndpointAddress;
 476        u8                      highspeed;
 477        struct list_head        td_list;        /* queued itds/sitds */
 478        struct list_head        free_list;      /* list of unused itds/sitds */
 479
 480        /* output of (re)scheduling */
 481        struct ehci_per_sched   ps;             /* scheduling info */
 482        unsigned                next_uframe;
 483        __hc32                  splits;
 484
 485        /* the rest is derived from the endpoint descriptor,
 486         * including the extra info for hw_bufp[0..2]
 487         */
 488        u16                     uperiod;        /* period in uframes */
 489        u16                     maxp;
 490        unsigned                bandwidth;
 491
 492        /* This is used to initialize iTD's hw_bufp fields */
 493        __hc32                  buf0;
 494        __hc32                  buf1;
 495        __hc32                  buf2;
 496
 497        /* this is used to initialize sITD's tt info */
 498        __hc32                  address;
 499};
 500
 501/*-------------------------------------------------------------------------*/
 502
 503/*
 504 * EHCI Specification 0.95 Section 3.3
 505 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 506 *
 507 * Schedule records for high speed iso xfers
 508 */
 509struct ehci_itd {
 510        /* first part defined by EHCI spec */
 511        __hc32                  hw_next;           /* see EHCI 3.3.1 */
 512        __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 513#define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 514#define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 515#define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 516#define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 517#define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 518#define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 519
 520#define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 521
 522        __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 523        __hc32                  hw_bufp_hi [7]; /* Appendix B */
 524
 525        /* the rest is HCD-private */
 526        dma_addr_t              itd_dma;        /* for this itd */
 527        union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 528
 529        struct urb              *urb;
 530        struct ehci_iso_stream  *stream;        /* endpoint's queue */
 531        struct list_head        itd_list;       /* list of stream's itds */
 532
 533        /* any/all hw_transactions here may be used by that urb */
 534        unsigned                frame;          /* where scheduled */
 535        unsigned                pg;
 536        unsigned                index[8];       /* in urb->iso_frame_desc */
 537} __attribute__ ((aligned (32)));
 538
 539/*-------------------------------------------------------------------------*/
 540
 541/*
 542 * EHCI Specification 0.95 Section 3.4
 543 * siTD, aka split-transaction isochronous Transfer Descriptor
 544 *       ... describe full speed iso xfers through TT in hubs
 545 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 546 */
 547struct ehci_sitd {
 548        /* first part defined by EHCI spec */
 549        __hc32                  hw_next;
 550/* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 551        __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 552        __hc32                  hw_uframe;              /* EHCI table 3-10 */
 553        __hc32                  hw_results;             /* EHCI table 3-11 */
 554#define SITD_IOC        (1 << 31)       /* interrupt on completion */
 555#define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 556#define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 557#define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 558#define SITD_STS_ERR    (1 << 6)        /* error from TT */
 559#define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 560#define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 561#define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 562#define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 563#define SITD_STS_STS    (1 << 1)        /* split transaction state */
 564
 565#define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 566
 567        __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 568        __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 569        __hc32                  hw_buf_hi [2];          /* Appendix B */
 570
 571        /* the rest is HCD-private */
 572        dma_addr_t              sitd_dma;
 573        union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 574
 575        struct urb              *urb;
 576        struct ehci_iso_stream  *stream;        /* endpoint's queue */
 577        struct list_head        sitd_list;      /* list of stream's sitds */
 578        unsigned                frame;
 579        unsigned                index;
 580} __attribute__ ((aligned (32)));
 581
 582/*-------------------------------------------------------------------------*/
 583
 584/*
 585 * EHCI Specification 0.96 Section 3.7
 586 * Periodic Frame Span Traversal Node (FSTN)
 587 *
 588 * Manages split interrupt transactions (using TT) that span frame boundaries
 589 * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 590 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 591 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 592 */
 593struct ehci_fstn {
 594        __hc32                  hw_next;        /* any periodic q entry */
 595        __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 596
 597        /* the rest is HCD-private */
 598        dma_addr_t              fstn_dma;
 599        union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 600} __attribute__ ((aligned (32)));
 601
 602/*-------------------------------------------------------------------------*/
 603
 604/*
 605 * USB-2.0 Specification Sections 11.14 and 11.18
 606 * Scheduling and budgeting split transactions using TTs
 607 *
 608 * A hub can have a single TT for all its ports, or multiple TTs (one for each
 609 * port).  The bandwidth and budgeting information for the full/low-speed bus
 610 * below each TT is self-contained and independent of the other TTs or the
 611 * high-speed bus.
 612 *
 613 * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated
 614 * to an interrupt or isochronous endpoint for each frame.  "Budget" refers to
 615 * the best-case estimate of the number of full-speed bytes allocated to an
 616 * endpoint for each microframe within an allocated frame.
 617 *
 618 * Removal of an endpoint invalidates a TT's budget.  Instead of trying to
 619 * keep an up-to-date record, we recompute the budget when it is needed.
 620 */
 621
 622struct ehci_tt {
 623        u16                     bandwidth[EHCI_BANDWIDTH_FRAMES];
 624
 625        struct list_head        tt_list;        /* List of all ehci_tt's */
 626        struct list_head        ps_list;        /* Items using this TT */
 627        struct usb_tt           *usb_tt;
 628        int                     tt_port;        /* TT port number */
 629};
 630
 631/*-------------------------------------------------------------------------*/
 632
 633/* Prepare the PORTSC wakeup flags during controller suspend/resume */
 634
 635#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)      \
 636                ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
 637
 638#define ehci_prepare_ports_for_controller_resume(ehci)                  \
 639                ehci_adjust_port_wakeup_flags(ehci, false, false);
 640
 641/*-------------------------------------------------------------------------*/
 642
 643#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 644
 645/*
 646 * Some EHCI controllers have a Transaction Translator built into the
 647 * root hub. This is a non-standard feature.  Each controller will need
 648 * to add code to the following inline functions, and call them as
 649 * needed (mostly in root hub code).
 650 */
 651
 652#define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 653
 654/* Returns the speed of a device attached to a port on the root hub. */
 655static inline unsigned int
 656ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 657{
 658        if (ehci_is_TDI(ehci)) {
 659                switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
 660                case 0:
 661                        return 0;
 662                case 1:
 663                        return USB_PORT_STAT_LOW_SPEED;
 664                case 2:
 665                default:
 666                        return USB_PORT_STAT_HIGH_SPEED;
 667                }
 668        }
 669        return USB_PORT_STAT_HIGH_SPEED;
 670}
 671
 672#else
 673
 674#define ehci_is_TDI(e)                  (0)
 675
 676#define ehci_port_speed(ehci, portsc)   USB_PORT_STAT_HIGH_SPEED
 677#endif
 678
 679/*-------------------------------------------------------------------------*/
 680
 681#ifdef CONFIG_PPC_83xx
 682/* Some Freescale processors have an erratum in which the TT
 683 * port number in the queue head was 0..N-1 instead of 1..N.
 684 */
 685#define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 686#else
 687#define ehci_has_fsl_portno_bug(e)              (0)
 688#endif
 689
 690#define PORTSC_FSL_PFSC 24      /* Port Force Full-Speed Connect */
 691
 692#if defined(CONFIG_PPC_85xx)
 693/* Some Freescale processors have an erratum (USB A-005275) in which
 694 * incoming packets get corrupted in HS mode
 695 */
 696#define ehci_has_fsl_hs_errata(e)       ((e)->has_fsl_hs_errata)
 697#else
 698#define ehci_has_fsl_hs_errata(e)       (0)
 699#endif
 700
 701/*
 702 * While most USB host controllers implement their registers in
 703 * little-endian format, a minority (celleb companion chip) implement
 704 * them in big endian format.
 705 *
 706 * This attempts to support either format at compile time without a
 707 * runtime penalty, or both formats with the additional overhead
 708 * of checking a flag bit.
 709 *
 710 * ehci_big_endian_capbase is a special quirk for controllers that
 711 * implement the HC capability registers as separate registers and not
 712 * as fields of a 32-bit register.
 713 */
 714
 715#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 716#define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 717#define ehci_big_endian_capbase(e)      ((e)->big_endian_capbase)
 718#else
 719#define ehci_big_endian_mmio(e)         0
 720#define ehci_big_endian_capbase(e)      0
 721#endif
 722
 723/*
 724 * Big-endian read/write functions are arch-specific.
 725 * Other arches can be added if/when they're needed.
 726 */
 727#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
 728#define readl_be(addr)          __raw_readl((__force unsigned *)addr)
 729#define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
 730#endif
 731
 732static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 733                __u32 __iomem * regs)
 734{
 735#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 736        return ehci_big_endian_mmio(ehci) ?
 737                readl_be(regs) :
 738                readl(regs);
 739#else
 740        return readl(regs);
 741#endif
 742}
 743
 744#ifdef CONFIG_SOC_IMX28
 745static inline void imx28_ehci_writel(const unsigned int val,
 746                volatile __u32 __iomem *addr)
 747{
 748        __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
 749}
 750#else
 751static inline void imx28_ehci_writel(const unsigned int val,
 752                volatile __u32 __iomem *addr)
 753{
 754}
 755#endif
 756static inline void ehci_writel(const struct ehci_hcd *ehci,
 757                const unsigned int val, __u32 __iomem *regs)
 758{
 759#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 760        ehci_big_endian_mmio(ehci) ?
 761                writel_be(val, regs) :
 762                writel(val, regs);
 763#else
 764        if (ehci->imx28_write_fix)
 765                imx28_ehci_writel(val, regs);
 766        else
 767                writel(val, regs);
 768#endif
 769}
 770
 771/*
 772 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
 773 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
 774 * Other common bits are dependent on has_amcc_usb23 quirk flag.
 775 */
 776#ifdef CONFIG_44x
 777static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 778{
 779        u32 hc_control;
 780
 781        hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
 782        if (operational)
 783                hc_control |= OHCI_USB_OPER;
 784        else
 785                hc_control |= OHCI_USB_SUSPEND;
 786
 787        writel_be(hc_control, ehci->ohci_hcctrl_reg);
 788        (void) readl_be(ehci->ohci_hcctrl_reg);
 789}
 790#else
 791static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 792{ }
 793#endif
 794
 795/*-------------------------------------------------------------------------*/
 796
 797/*
 798 * The AMCC 440EPx not only implements its EHCI registers in big-endian
 799 * format, but also its DMA data structures (descriptors).
 800 *
 801 * EHCI controllers accessed through PCI work normally (little-endian
 802 * everywhere), so we won't bother supporting a BE-only mode for now.
 803 */
 804#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 805#define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 806
 807/* cpu to ehci */
 808static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 809{
 810        return ehci_big_endian_desc(ehci)
 811                ? (__force __hc32)cpu_to_be32(x)
 812                : (__force __hc32)cpu_to_le32(x);
 813}
 814
 815/* ehci to cpu */
 816static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 817{
 818        return ehci_big_endian_desc(ehci)
 819                ? be32_to_cpu((__force __be32)x)
 820                : le32_to_cpu((__force __le32)x);
 821}
 822
 823static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 824{
 825        return ehci_big_endian_desc(ehci)
 826                ? be32_to_cpup((__force __be32 *)x)
 827                : le32_to_cpup((__force __le32 *)x);
 828}
 829
 830#else
 831
 832/* cpu to ehci */
 833static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 834{
 835        return cpu_to_le32(x);
 836}
 837
 838/* ehci to cpu */
 839static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 840{
 841        return le32_to_cpu(x);
 842}
 843
 844static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 845{
 846        return le32_to_cpup(x);
 847}
 848
 849#endif
 850
 851/*-------------------------------------------------------------------------*/
 852
 853#define ehci_dbg(ehci, fmt, args...) \
 854        dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
 855#define ehci_err(ehci, fmt, args...) \
 856        dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
 857#define ehci_info(ehci, fmt, args...) \
 858        dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
 859#define ehci_warn(ehci, fmt, args...) \
 860        dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
 861
 862
 863#ifndef CONFIG_DYNAMIC_DEBUG
 864#define STUB_DEBUG_FILES
 865#endif
 866
 867/*-------------------------------------------------------------------------*/
 868
 869/* Declarations of things exported for use by ehci platform drivers */
 870
 871struct ehci_driver_overrides {
 872        size_t          extra_priv_size;
 873        int             (*reset)(struct usb_hcd *hcd);
 874        int             (*port_power)(struct usb_hcd *hcd,
 875                                int portnum, bool enable);
 876};
 877
 878extern void     ehci_init_driver(struct hc_driver *drv,
 879                                const struct ehci_driver_overrides *over);
 880extern int      ehci_setup(struct usb_hcd *hcd);
 881extern int      ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
 882                                u32 mask, u32 done, int usec);
 883extern int      ehci_reset(struct ehci_hcd *ehci);
 884
 885#ifdef CONFIG_PM
 886extern int      ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
 887extern int      ehci_resume(struct usb_hcd *hcd, bool force_reset);
 888extern void     ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
 889                        bool suspending, bool do_wakeup);
 890#endif  /* CONFIG_PM */
 891
 892extern int      ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 893                                 u16 wIndex, char *buf, u16 wLength);
 894
 895#endif /* __LINUX_EHCI_HCD_H */
 896