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24#ifndef __LINUX_XHCI_HCD_H
25#define __LINUX_XHCI_HCD_H
26
27#include <linux/usb.h>
28#include <linux/timer.h>
29#include <linux/kernel.h>
30#include <linux/usb/hcd.h>
31
32
33#include "xhci-ext-caps.h"
34#include "pci-quirks.h"
35
36
37#define XHCI_SBRN_OFFSET (0x60)
38
39
40#define MAX_HC_SLOTS 256
41
42#define MAX_HC_PORTS 127
43
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59
60struct xhci_cap_regs {
61 __le32 hc_capbase;
62 __le32 hcs_params1;
63 __le32 hcs_params2;
64 __le32 hcs_params3;
65 __le32 hcc_params;
66 __le32 db_off;
67 __le32 run_regs_off;
68
69};
70
71
72
73#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
74
75#define HC_VERSION(p) (((p) >> 16) & 0xffff)
76
77
78
79#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
80#define HCS_SLOTS_MASK 0xff
81
82#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
83
84#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
85
86
87
88
89#define HCS_IST(p) (((p) >> 0) & 0xf)
90
91#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
92
93
94
95#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
96
97
98
99#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
100
101#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
102
103
104
105#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
106
107#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
108
109
110
111#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
112
113#define HCC_PPC(p) ((p) & (1 << 3))
114
115#define HCS_INDICATOR(p) ((p) & (1 << 4))
116
117#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
118
119#define HCC_LTC(p) ((p) & (1 << 6))
120
121#define HCC_NSS(p) ((p) & (1 << 7))
122
123#define HCC_SPC(p) ((p) & (1 << 9))
124
125#define HCC_CFC(p) ((p) & (1 << 11))
126
127#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
128
129#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
130
131
132#define DBOFF_MASK (~0x3)
133
134
135#define RTSOFF_MASK (~0x1f)
136
137
138
139#define NUM_PORT_REGS 4
140
141#define PORTSC 0
142#define PORTPMSC 1
143#define PORTLI 2
144#define PORTHLPMC 3
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168struct xhci_op_regs {
169 __le32 command;
170 __le32 status;
171 __le32 page_size;
172 __le32 reserved1;
173 __le32 reserved2;
174 __le32 dev_notification;
175 __le64 cmd_ring;
176
177 __le32 reserved3[4];
178 __le64 dcbaa_ptr;
179 __le32 config_reg;
180
181 __le32 reserved4[241];
182
183 __le32 port_status_base;
184 __le32 port_power_base;
185 __le32 port_link_base;
186 __le32 reserved5;
187
188 __le32 reserved6[NUM_PORT_REGS*254];
189};
190
191
192
193#define CMD_RUN XHCI_CMD_RUN
194
195
196
197
198#define CMD_RESET (1 << 1)
199
200#define CMD_EIE XHCI_CMD_EIE
201
202#define CMD_HSEIE XHCI_CMD_HSEIE
203
204
205#define CMD_LRESET (1 << 7)
206
207#define CMD_CSS (1 << 8)
208#define CMD_CRS (1 << 9)
209
210#define CMD_EWE XHCI_CMD_EWE
211
212
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214
215
216#define CMD_PM_INDEX (1 << 11)
217
218
219
220#define IMAN_IE (1 << 1)
221#define IMAN_IP (1 << 0)
222
223
224
225#define STS_HALT XHCI_STS_HALT
226
227#define STS_FATAL (1 << 2)
228
229#define STS_EINT (1 << 3)
230
231#define STS_PORT (1 << 4)
232
233
234#define STS_SAVE (1 << 8)
235
236#define STS_RESTORE (1 << 9)
237
238#define STS_SRE (1 << 10)
239
240#define STS_CNR XHCI_STS_CNR
241
242#define STS_HCE (1 << 12)
243
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249
250#define DEV_NOTE_MASK (0xffff)
251#define ENABLE_DEV_NOTE(x) (1 << (x))
252
253
254
255#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
256
257
258
259
260#define CMD_RING_PAUSE (1 << 1)
261
262#define CMD_RING_ABORT (1 << 2)
263
264#define CMD_RING_RUNNING (1 << 3)
265
266
267#define CMD_RING_RSVD_BITS (0x3f)
268
269
270
271#define MAX_DEVS(p) ((p) & 0xff)
272
273
274
275
276#define PORT_CONNECT (1 << 0)
277
278#define PORT_PE (1 << 1)
279
280
281#define PORT_OC (1 << 3)
282
283#define PORT_RESET (1 << 4)
284
285
286
287
288#define PORT_PLS_MASK (0xf << 5)
289#define XDEV_U0 (0x0 << 5)
290#define XDEV_U2 (0x2 << 5)
291#define XDEV_U3 (0x3 << 5)
292#define XDEV_INACTIVE (0x6 << 5)
293#define XDEV_RESUME (0xf << 5)
294
295#define PORT_POWER (1 << 9)
296
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303
304#define DEV_SPEED_MASK (0xf << 10)
305#define XDEV_FS (0x1 << 10)
306#define XDEV_LS (0x2 << 10)
307#define XDEV_HS (0x3 << 10)
308#define XDEV_SS (0x4 << 10)
309#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
310#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
311#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
312#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
313#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
314
315#define SLOT_SPEED_FS (XDEV_FS << 10)
316#define SLOT_SPEED_LS (XDEV_LS << 10)
317#define SLOT_SPEED_HS (XDEV_HS << 10)
318#define SLOT_SPEED_SS (XDEV_SS << 10)
319
320#define PORT_LED_OFF (0 << 14)
321#define PORT_LED_AMBER (1 << 14)
322#define PORT_LED_GREEN (2 << 14)
323#define PORT_LED_MASK (3 << 14)
324
325#define PORT_LINK_STROBE (1 << 16)
326
327#define PORT_CSC (1 << 17)
328
329#define PORT_PEC (1 << 18)
330
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334
335#define PORT_WRC (1 << 19)
336
337#define PORT_OCC (1 << 20)
338
339#define PORT_RC (1 << 21)
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352
353#define PORT_PLC (1 << 22)
354
355#define PORT_CEC (1 << 23)
356
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359
360#define PORT_CAS (1 << 24)
361
362#define PORT_WKCONN_E (1 << 25)
363
364#define PORT_WKDISC_E (1 << 26)
365
366#define PORT_WKOC_E (1 << 27)
367
368
369#define PORT_DEV_REMOVE (1 << 30)
370
371#define PORT_WR (1 << 31)
372
373
374#define DUPLICATE_ENTRY ((u8)(-1))
375
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379
380#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
381#define PORT_U1_TIMEOUT_MASK 0xff
382
383#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
384#define PORT_U2_TIMEOUT_MASK (0xff << 8)
385
386
387
388#define PORT_L1S_MASK 7
389#define PORT_L1S_SUCCESS 1
390#define PORT_RWE (1 << 3)
391#define PORT_HIRD(p) (((p) & 0xf) << 4)
392#define PORT_HIRD_MASK (0xf << 4)
393#define PORT_L1DS_MASK (0xff << 8)
394#define PORT_L1DS(p) (((p) & 0xff) << 8)
395#define PORT_HLE (1 << 16)
396
397
398
399#define PORT_HIRDM(p)((p) & 3)
400#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
401#define PORT_BESLD(p)(((p) & 0xf) << 10)
402
403
404#define XHCI_L1_TIMEOUT 512
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415
416#define XHCI_DEFAULT_BESL 4
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435struct xhci_intr_reg {
436 __le32 irq_pending;
437 __le32 irq_control;
438 __le32 erst_size;
439 __le32 rsvd;
440 __le64 erst_base;
441 __le64 erst_dequeue;
442};
443
444
445#define ER_IRQ_PENDING(p) ((p) & 0x1)
446
447
448#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
449#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
450#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
451
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456
457#define ER_IRQ_INTERVAL_MASK (0xffff)
458
459#define ER_IRQ_COUNTER_MASK (0xffff << 16)
460
461
462
463#define ERST_SIZE_MASK (0xffff << 16)
464
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468
469#define ERST_DESI_MASK (0x7)
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473#define ERST_EHB (1 << 3)
474#define ERST_PTR_MASK (0xf)
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484
485struct xhci_run_regs {
486 __le32 microframe_index;
487 __le32 rsvd[7];
488 struct xhci_intr_reg ir_set[128];
489};
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499
500struct xhci_doorbell_array {
501 __le32 doorbell[256];
502};
503
504#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
505#define DB_VALUE_HOST 0x00000000
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514
515struct xhci_protocol_caps {
516 u32 revision;
517 u32 name_string;
518 u32 port_info;
519};
520
521#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
522#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
523#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
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534
535struct xhci_container_ctx {
536 unsigned type;
537#define XHCI_CTX_TYPE_DEVICE 0x1
538#define XHCI_CTX_TYPE_INPUT 0x2
539
540 int size;
541
542 u8 *bytes;
543 dma_addr_t dma;
544};
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557struct xhci_slot_ctx {
558 __le32 dev_info;
559 __le32 dev_info2;
560 __le32 tt_info;
561 __le32 dev_state;
562
563 __le32 reserved[4];
564};
565
566
567
568#define ROUTE_STRING_MASK (0xfffff)
569
570#define DEV_SPEED (0xf << 20)
571
572
573#define DEV_MTT (0x1 << 25)
574
575#define DEV_HUB (0x1 << 26)
576
577#define LAST_CTX_MASK (0x1f << 27)
578#define LAST_CTX(p) ((p) << 27)
579#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
580#define SLOT_FLAG (1 << 0)
581#define EP0_FLAG (1 << 1)
582
583
584
585#define MAX_EXIT (0xffff)
586
587#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
588#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
589
590#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
591
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597
598#define TT_SLOT (0xff)
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603#define TT_PORT (0xff << 8)
604#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
605
606
607
608#define DEV_ADDR_MASK (0xff)
609
610
611#define SLOT_STATE (0x1f << 27)
612#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
613
614#define SLOT_STATE_DISABLED 0
615#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
616#define SLOT_STATE_DEFAULT 1
617#define SLOT_STATE_ADDRESSED 2
618#define SLOT_STATE_CONFIGURED 3
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638struct xhci_ep_ctx {
639 __le32 ep_info;
640 __le32 ep_info2;
641 __le64 deq;
642 __le32 tx_info;
643
644 __le32 reserved[3];
645};
646
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656
657#define EP_STATE_MASK (0xf)
658#define EP_STATE_DISABLED 0
659#define EP_STATE_RUNNING 1
660#define EP_STATE_HALTED 2
661#define EP_STATE_STOPPED 3
662#define EP_STATE_ERROR 4
663
664#define EP_MULT(p) (((p) & 0x3) << 8)
665#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
666
667
668
669#define EP_INTERVAL(p) (((p) & 0xff) << 16)
670#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
671#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
672#define EP_MAXPSTREAMS_MASK (0x1f << 10)
673#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
674
675#define EP_HAS_LSA (1 << 15)
676
677
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680
681
682#define FORCE_EVENT (0x1)
683#define ERROR_COUNT(p) (((p) & 0x3) << 1)
684#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
685#define EP_TYPE(p) ((p) << 3)
686#define ISOC_OUT_EP 1
687#define BULK_OUT_EP 2
688#define INT_OUT_EP 3
689#define CTRL_EP 4
690#define ISOC_IN_EP 5
691#define BULK_IN_EP 6
692#define INT_IN_EP 7
693
694
695#define MAX_BURST(p) (((p)&0xff) << 8)
696#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
697#define MAX_PACKET(p) (((p)&0xffff) << 16)
698#define MAX_PACKET_MASK (0xffff << 16)
699#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
700
701
702
703
704#define GET_MAX_PACKET(p) ((p) & 0x7ff)
705
706
707#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
708#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
709#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
710
711
712#define EP_CTX_CYCLE_MASK (1 << 0)
713#define SCTX_DEQ_MASK (~0xfL)
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721
722
723struct xhci_input_control_ctx {
724 __le32 drop_flags;
725 __le32 add_flags;
726 __le32 rsvd2[6];
727};
728
729#define EP_IS_ADDED(ctrl_ctx, i) \
730 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
731#define EP_IS_DROPPED(ctrl_ctx, i) \
732 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
733
734
735
736
737
738struct xhci_command {
739
740 struct xhci_container_ctx *in_ctx;
741 u32 status;
742
743
744
745 struct completion *completion;
746 union xhci_trb *command_trb;
747 struct list_head cmd_list;
748};
749
750
751#define DROP_EP(x) (0x1 << x)
752
753#define ADD_EP(x) (0x1 << x)
754
755struct xhci_stream_ctx {
756
757 __le64 stream_ring;
758
759 __le32 reserved[2];
760};
761
762
763#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
764
765#define SCT_SEC_TR 0
766
767#define SCT_PRI_TR 1
768
769#define SCT_SSA_8 2
770#define SCT_SSA_16 3
771#define SCT_SSA_32 4
772#define SCT_SSA_64 5
773#define SCT_SSA_128 6
774#define SCT_SSA_256 7
775
776
777struct xhci_stream_info {
778 struct xhci_ring **stream_rings;
779
780 unsigned int num_streams;
781
782
783
784 struct xhci_stream_ctx *stream_ctx_array;
785 unsigned int num_stream_ctxs;
786 dma_addr_t ctx_array_dma;
787
788 struct radix_tree_root trb_address_map;
789 struct xhci_command *free_streams_command;
790};
791
792#define SMALL_STREAM_ARRAY_SIZE 256
793#define MEDIUM_STREAM_ARRAY_SIZE 1024
794
795
796
797
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799
800
801struct xhci_bw_info {
802
803 unsigned int ep_interval;
804
805 unsigned int mult;
806 unsigned int num_packets;
807 unsigned int max_packet_size;
808 unsigned int max_esit_payload;
809 unsigned int type;
810};
811
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815
816
817#define FS_BLOCK 1
818#define HS_BLOCK 4
819#define SS_BLOCK 16
820#define DMI_BLOCK 32
821
822
823
824
825
826
827#define DMI_OVERHEAD 8
828#define DMI_OVERHEAD_BURST 4
829#define SS_OVERHEAD 8
830#define SS_OVERHEAD_BURST 32
831#define HS_OVERHEAD 26
832#define FS_OVERHEAD 20
833#define LS_OVERHEAD 128
834
835
836
837
838
839#define TT_HS_OVERHEAD (31 + 94)
840#define TT_DMI_OVERHEAD (25 + 12)
841
842
843#define FS_BW_LIMIT 1285
844#define TT_BW_LIMIT 1320
845#define HS_BW_LIMIT 1607
846#define SS_BW_LIMIT_IN 3906
847#define DMI_BW_LIMIT_IN 3906
848#define SS_BW_LIMIT_OUT 3906
849#define DMI_BW_LIMIT_OUT 3906
850
851
852#define FS_BW_RESERVED 10
853#define HS_BW_RESERVED 20
854#define SS_BW_RESERVED 10
855
856struct xhci_virt_ep {
857 struct xhci_ring *ring;
858
859 struct xhci_stream_info *stream_info;
860
861
862
863 struct xhci_ring *new_ring;
864 unsigned int ep_state;
865#define SET_DEQ_PENDING (1 << 0)
866#define EP_HALTED (1 << 1)
867#define EP_HALT_PENDING (1 << 2)
868
869#define EP_GETTING_STREAMS (1 << 3)
870#define EP_HAS_STREAMS (1 << 4)
871
872#define EP_GETTING_NO_STREAMS (1 << 5)
873
874 struct list_head cancelled_td_list;
875 struct xhci_td *stopped_td;
876 unsigned int stopped_stream;
877
878 struct timer_list stop_cmd_timer;
879 int stop_cmds_pending;
880 struct xhci_hcd *xhci;
881
882
883
884
885 struct xhci_segment *queued_deq_seg;
886 union xhci_trb *queued_deq_ptr;
887
888
889
890
891
892
893
894 bool skip;
895
896 struct xhci_bw_info bw_info;
897 struct list_head bw_endpoint_list;
898
899 int next_frame_id;
900};
901
902enum xhci_overhead_type {
903 LS_OVERHEAD_TYPE = 0,
904 FS_OVERHEAD_TYPE,
905 HS_OVERHEAD_TYPE,
906};
907
908struct xhci_interval_bw {
909 unsigned int num_packets;
910
911
912
913 struct list_head endpoints;
914
915 unsigned int overhead[3];
916};
917
918#define XHCI_MAX_INTERVAL 16
919
920struct xhci_interval_bw_table {
921 unsigned int interval0_esit_payload;
922 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
923
924 unsigned int bw_used;
925 unsigned int ss_bw_in;
926 unsigned int ss_bw_out;
927};
928
929
930struct xhci_virt_device {
931 struct usb_device *udev;
932
933
934
935
936
937
938
939
940 struct xhci_container_ctx *out_ctx;
941
942 struct xhci_container_ctx *in_ctx;
943
944 struct xhci_ring **ring_cache;
945 int num_rings_cached;
946#define XHCI_MAX_RINGS_CACHED 31
947 struct xhci_virt_ep eps[31];
948 struct completion cmd_completion;
949 u8 fake_port;
950 u8 real_port;
951 struct xhci_interval_bw_table *bw_table;
952 struct xhci_tt_bw_info *tt_info;
953
954 u16 current_mel;
955};
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963
964
965struct xhci_root_port_bw_info {
966 struct list_head tts;
967 unsigned int num_active_tts;
968 struct xhci_interval_bw_table bw_table;
969};
970
971struct xhci_tt_bw_info {
972 struct list_head tt_list;
973 int slot_id;
974 int ttport;
975 struct xhci_interval_bw_table bw_table;
976 int active_eps;
977};
978
979
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981
982
983
984struct xhci_device_context_array {
985
986 __le64 dev_context_ptrs[MAX_HC_SLOTS];
987
988 dma_addr_t dma;
989};
990
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992
993
994
995
996
997struct xhci_transfer_event {
998
999 __le64 buffer;
1000 __le32 transfer_len;
1001
1002 __le32 flags;
1003};
1004
1005
1006
1007#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1008
1009
1010#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1011
1012
1013#define COMP_CODE_MASK (0xff << 24)
1014#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1015#define COMP_SUCCESS 1
1016
1017#define COMP_DB_ERR 2
1018
1019#define COMP_BABBLE 3
1020
1021#define COMP_TX_ERR 4
1022
1023#define COMP_TRB_ERR 5
1024
1025#define COMP_STALL 6
1026
1027#define COMP_ENOMEM 7
1028
1029#define COMP_BW_ERR 8
1030
1031#define COMP_ENOSLOTS 9
1032
1033#define COMP_STREAM_ERR 10
1034
1035#define COMP_EBADSLT 11
1036
1037#define COMP_EBADEP 12
1038
1039#define COMP_SHORT_TX 13
1040
1041#define COMP_UNDERRUN 14
1042
1043#define COMP_OVERRUN 15
1044
1045#define COMP_VF_FULL 16
1046
1047#define COMP_EINVAL 17
1048
1049#define COMP_BW_OVER 18
1050
1051#define COMP_CTX_STATE 19
1052
1053#define COMP_PING_ERR 20
1054
1055#define COMP_ER_FULL 21
1056
1057#define COMP_DEV_ERR 22
1058
1059#define COMP_MISSED_INT 23
1060
1061#define COMP_CMD_STOP 24
1062
1063#define COMP_CMD_ABORT 25
1064
1065#define COMP_STOP 26
1066
1067#define COMP_STOP_INVAL 27
1068
1069#define COMP_STOP_SHORT 28
1070
1071#define COMP_MEL_ERR 29
1072
1073
1074#define COMP_BUFF_OVER 31
1075
1076#define COMP_ISSUES 32
1077
1078#define COMP_UNKNOWN 33
1079
1080#define COMP_STRID_ERR 34
1081
1082#define COMP_2ND_BW_ERR 35
1083
1084#define COMP_SPLIT_ERR 36
1085
1086struct xhci_link_trb {
1087
1088 __le64 segment_ptr;
1089 __le32 intr_target;
1090 __le32 control;
1091};
1092
1093
1094#define LINK_TOGGLE (0x1<<1)
1095
1096
1097struct xhci_event_cmd {
1098
1099 __le64 cmd_trb;
1100 __le32 status;
1101 __le32 flags;
1102};
1103
1104
1105
1106
1107#define TRB_BSR (1<<9)
1108enum xhci_setup_dev {
1109 SETUP_CONTEXT_ONLY,
1110 SETUP_CONTEXT_ADDRESS,
1111};
1112
1113
1114
1115#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1116#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1117
1118
1119#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1120#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1121
1122#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1123#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1124#define LAST_EP_INDEX 30
1125
1126
1127#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1128#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1129#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1130
1131
1132
1133
1134#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1135
1136
1137
1138#define TRB_LEN(p) ((p) & 0x1ffff)
1139
1140#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1141#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1142#define TRB_TBC(p) (((p) & 0x3) << 7)
1143#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1144
1145
1146#define TRB_CYCLE (1<<0)
1147
1148
1149
1150
1151#define TRB_ENT (1<<1)
1152
1153#define TRB_ISP (1<<2)
1154
1155#define TRB_NO_SNOOP (1<<3)
1156
1157#define TRB_CHAIN (1<<4)
1158
1159#define TRB_IOC (1<<5)
1160
1161#define TRB_IDT (1<<6)
1162
1163
1164#define TRB_BEI (1<<9)
1165
1166
1167#define TRB_DIR_IN (1<<16)
1168#define TRB_TX_TYPE(p) ((p) << 16)
1169#define TRB_DATA_OUT 2
1170#define TRB_DATA_IN 3
1171
1172
1173#define TRB_SIA (1<<31)
1174#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1175
1176struct xhci_generic_trb {
1177 __le32 field[4];
1178};
1179
1180union xhci_trb {
1181 struct xhci_link_trb link;
1182 struct xhci_transfer_event trans_event;
1183 struct xhci_event_cmd event_cmd;
1184 struct xhci_generic_trb generic;
1185};
1186
1187
1188#define TRB_TYPE_BITMASK (0xfc00)
1189#define TRB_TYPE(p) ((p) << 10)
1190#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1191
1192
1193#define TRB_NORMAL 1
1194
1195#define TRB_SETUP 2
1196
1197#define TRB_DATA 3
1198
1199#define TRB_STATUS 4
1200
1201#define TRB_ISOC 5
1202
1203#define TRB_LINK 6
1204#define TRB_EVENT_DATA 7
1205
1206#define TRB_TR_NOOP 8
1207
1208
1209#define TRB_ENABLE_SLOT 9
1210
1211#define TRB_DISABLE_SLOT 10
1212
1213#define TRB_ADDR_DEV 11
1214
1215#define TRB_CONFIG_EP 12
1216
1217#define TRB_EVAL_CONTEXT 13
1218
1219#define TRB_RESET_EP 14
1220
1221#define TRB_STOP_RING 15
1222
1223#define TRB_SET_DEQ 16
1224
1225#define TRB_RESET_DEV 17
1226
1227#define TRB_FORCE_EVENT 18
1228
1229#define TRB_NEG_BANDWIDTH 19
1230
1231#define TRB_SET_LT 20
1232
1233#define TRB_GET_BW 21
1234
1235#define TRB_FORCE_HEADER 22
1236
1237#define TRB_CMD_NOOP 23
1238
1239
1240
1241#define TRB_TRANSFER 32
1242
1243#define TRB_COMPLETION 33
1244
1245#define TRB_PORT_STATUS 34
1246
1247#define TRB_BANDWIDTH_EVENT 35
1248
1249#define TRB_DOORBELL 36
1250
1251#define TRB_HC_EVENT 37
1252
1253#define TRB_DEV_NOTE 38
1254
1255#define TRB_MFINDEX_WRAP 39
1256
1257
1258
1259#define TRB_NEC_CMD_COMP 48
1260
1261#define TRB_NEC_GET_FW 49
1262
1263#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1264
1265#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1266 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1267#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1268 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1269
1270#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1271#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1272
1273
1274
1275
1276
1277
1278#define TRBS_PER_SEGMENT 256
1279
1280#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1281#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1282#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1283
1284#define TRB_MAX_BUFF_SHIFT 16
1285#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1286
1287struct xhci_segment {
1288 union xhci_trb *trbs;
1289
1290 struct xhci_segment *next;
1291 dma_addr_t dma;
1292};
1293
1294struct xhci_td {
1295 struct list_head td_list;
1296 struct list_head cancelled_td_list;
1297 struct urb *urb;
1298 struct xhci_segment *start_seg;
1299 union xhci_trb *first_trb;
1300 union xhci_trb *last_trb;
1301
1302 bool urb_length_set;
1303};
1304
1305
1306#define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1307
1308
1309struct xhci_cd {
1310 struct xhci_command *command;
1311 union xhci_trb *cmd_trb;
1312};
1313
1314struct xhci_dequeue_state {
1315 struct xhci_segment *new_deq_seg;
1316 union xhci_trb *new_deq_ptr;
1317 int new_cycle_state;
1318};
1319
1320enum xhci_ring_type {
1321 TYPE_CTRL = 0,
1322 TYPE_ISOC,
1323 TYPE_BULK,
1324 TYPE_INTR,
1325 TYPE_STREAM,
1326 TYPE_COMMAND,
1327 TYPE_EVENT,
1328};
1329
1330struct xhci_ring {
1331 struct xhci_segment *first_seg;
1332 struct xhci_segment *last_seg;
1333 union xhci_trb *enqueue;
1334 struct xhci_segment *enq_seg;
1335 unsigned int enq_updates;
1336 union xhci_trb *dequeue;
1337 struct xhci_segment *deq_seg;
1338 unsigned int deq_updates;
1339 struct list_head td_list;
1340
1341
1342
1343
1344
1345 u32 cycle_state;
1346 unsigned int stream_id;
1347 unsigned int num_segs;
1348 unsigned int num_trbs_free;
1349 unsigned int num_trbs_free_temp;
1350 enum xhci_ring_type type;
1351 bool last_td_was_short;
1352 struct radix_tree_root *trb_address_map;
1353};
1354
1355struct xhci_erst_entry {
1356
1357 __le64 seg_addr;
1358 __le32 seg_size;
1359
1360 __le32 rsvd;
1361};
1362
1363struct xhci_erst {
1364 struct xhci_erst_entry *entries;
1365 unsigned int num_entries;
1366
1367 dma_addr_t erst_dma_addr;
1368
1369 unsigned int erst_size;
1370};
1371
1372struct xhci_scratchpad {
1373 u64 *sp_array;
1374 dma_addr_t sp_dma;
1375 void **sp_buffers;
1376 dma_addr_t *sp_dma_buffers;
1377};
1378
1379struct urb_priv {
1380 int length;
1381 int td_cnt;
1382 struct xhci_td *td[0];
1383};
1384
1385
1386
1387
1388
1389
1390#define ERST_NUM_SEGS 1
1391
1392#define ERST_SIZE 64
1393
1394#define ERST_ENTRIES 1
1395
1396#define POLL_TIMEOUT 60
1397
1398#define XHCI_STOP_EP_CMD_TIMEOUT 5
1399
1400
1401struct s3_save {
1402 u32 command;
1403 u32 dev_nt;
1404 u64 dcbaa_ptr;
1405 u32 config_reg;
1406 u32 irq_pending;
1407 u32 irq_control;
1408 u32 erst_size;
1409 u64 erst_base;
1410 u64 erst_dequeue;
1411};
1412
1413
1414struct dev_info {
1415 u32 dev_id;
1416 struct list_head list;
1417};
1418
1419struct xhci_bus_state {
1420 unsigned long bus_suspended;
1421 unsigned long next_statechange;
1422
1423
1424
1425 u32 port_c_suspend;
1426 u32 suspended_ports;
1427 u32 port_remote_wakeup;
1428 unsigned long resume_done[USB_MAXCHILDREN];
1429
1430 unsigned long resuming_ports;
1431
1432 unsigned long rexit_ports;
1433 struct completion rexit_done[USB_MAXCHILDREN];
1434};
1435
1436
1437
1438
1439
1440
1441#define XHCI_MAX_REXIT_TIMEOUT (20 * 1000)
1442
1443static inline unsigned int hcd_index(struct usb_hcd *hcd)
1444{
1445 if (hcd->speed == HCD_USB3)
1446 return 0;
1447 else
1448 return 1;
1449}
1450
1451
1452struct xhci_hcd {
1453 struct usb_hcd *main_hcd;
1454 struct usb_hcd *shared_hcd;
1455
1456 struct xhci_cap_regs __iomem *cap_regs;
1457 struct xhci_op_regs __iomem *op_regs;
1458 struct xhci_run_regs __iomem *run_regs;
1459 struct xhci_doorbell_array __iomem *dba;
1460
1461 struct xhci_intr_reg __iomem *ir_set;
1462
1463
1464 __u32 hcs_params1;
1465 __u32 hcs_params2;
1466 __u32 hcs_params3;
1467 __u32 hcc_params;
1468
1469 spinlock_t lock;
1470
1471
1472 u8 sbrn;
1473 u16 hci_version;
1474 u8 max_slots;
1475 u8 max_interrupters;
1476 u8 max_ports;
1477 u8 isoc_threshold;
1478 int event_ring_max;
1479 int addr_64;
1480
1481 int page_size;
1482
1483 int page_shift;
1484
1485 int msix_count;
1486 struct msix_entry *msix_entries;
1487
1488 struct clk *clk;
1489
1490 struct xhci_device_context_array *dcbaa;
1491 struct xhci_ring *cmd_ring;
1492 unsigned int cmd_ring_state;
1493#define CMD_RING_STATE_RUNNING (1 << 0)
1494#define CMD_RING_STATE_ABORTED (1 << 1)
1495#define CMD_RING_STATE_STOPPED (1 << 2)
1496 struct list_head cmd_list;
1497 unsigned int cmd_ring_reserved_trbs;
1498 struct timer_list cmd_timer;
1499 struct xhci_command *current_cmd;
1500 struct xhci_ring *event_ring;
1501 struct xhci_erst erst;
1502
1503 struct xhci_scratchpad *scratchpad;
1504
1505 struct list_head lpm_failed_devs;
1506
1507
1508
1509 struct mutex mutex;
1510 struct completion addr_dev;
1511 int slot_id;
1512
1513 struct xhci_command *lpm_command;
1514
1515 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1516
1517 struct xhci_root_port_bw_info *rh_bw;
1518
1519
1520 struct dma_pool *device_pool;
1521 struct dma_pool *segment_pool;
1522 struct dma_pool *small_streams_pool;
1523 struct dma_pool *medium_streams_pool;
1524
1525
1526 unsigned int xhc_state;
1527
1528 u32 command;
1529 struct s3_save s3;
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542#define XHCI_STATE_DYING (1 << 0)
1543#define XHCI_STATE_HALTED (1 << 1)
1544
1545 int error_bitmask;
1546 unsigned int quirks;
1547#define XHCI_LINK_TRB_QUIRK (1 << 0)
1548#define XHCI_RESET_EP_QUIRK (1 << 1)
1549#define XHCI_NEC_HOST (1 << 2)
1550#define XHCI_AMD_PLL_FIX (1 << 3)
1551#define XHCI_SPURIOUS_SUCCESS (1 << 4)
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561#define XHCI_EP_LIMIT_QUIRK (1 << 5)
1562#define XHCI_BROKEN_MSI (1 << 6)
1563#define XHCI_RESET_ON_RESUME (1 << 7)
1564#define XHCI_SW_BW_CHECKING (1 << 8)
1565#define XHCI_AMD_0x96_HOST (1 << 9)
1566#define XHCI_TRUST_TX_LENGTH (1 << 10)
1567#define XHCI_LPM_SUPPORT (1 << 11)
1568#define XHCI_INTEL_HOST (1 << 12)
1569#define XHCI_SPURIOUS_REBOOT (1 << 13)
1570#define XHCI_COMP_MODE_QUIRK (1 << 14)
1571#define XHCI_AVOID_BEI (1 << 15)
1572#define XHCI_PLAT (1 << 16)
1573#define XHCI_SLOW_SUSPEND (1 << 17)
1574#define XHCI_SPURIOUS_WAKEUP (1 << 18)
1575
1576#define XHCI_BROKEN_STREAMS (1 << 19)
1577#define XHCI_PME_STUCK_QUIRK (1 << 20)
1578 unsigned int num_active_eps;
1579 unsigned int limit_active_eps;
1580
1581 struct xhci_bus_state bus_state[2];
1582
1583 u8 *port_array;
1584
1585 __le32 __iomem **usb3_ports;
1586 unsigned int num_usb3_ports;
1587
1588 __le32 __iomem **usb2_ports;
1589 unsigned int num_usb2_ports;
1590
1591 unsigned sw_lpm_support:1;
1592
1593 unsigned hw_lpm_support:1;
1594
1595 u32 *ext_caps;
1596 unsigned int num_ext_caps;
1597
1598 struct timer_list comp_mode_recovery_timer;
1599 u32 port_status_u0;
1600
1601#define COMP_MODE_RCVRY_MSECS 2000
1602};
1603
1604
1605struct xhci_driver_overrides {
1606 size_t extra_priv_size;
1607 int (*reset)(struct usb_hcd *hcd);
1608 int (*start)(struct usb_hcd *hcd);
1609};
1610
1611#define XHCI_CFC_DELAY 10
1612
1613
1614static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1615{
1616 struct usb_hcd *primary_hcd;
1617
1618 if (usb_hcd_is_primary_hcd(hcd))
1619 primary_hcd = hcd;
1620 else
1621 primary_hcd = hcd->primary_hcd;
1622
1623 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1624}
1625
1626static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1627{
1628 return xhci->main_hcd;
1629}
1630
1631#define xhci_dbg(xhci, fmt, args...) \
1632 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1633#define xhci_err(xhci, fmt, args...) \
1634 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1635#define xhci_warn(xhci, fmt, args...) \
1636 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1637#define xhci_warn_ratelimited(xhci, fmt, args...) \
1638 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1639#define xhci_info(xhci, fmt, args...) \
1640 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1652 __le64 __iomem *regs)
1653{
1654 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1655 u64 val_lo = readl(ptr);
1656 u64 val_hi = readl(ptr + 1);
1657 return val_lo + (val_hi << 32);
1658}
1659static inline void xhci_write_64(struct xhci_hcd *xhci,
1660 const u64 val, __le64 __iomem *regs)
1661{
1662 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1663 u32 val_lo = lower_32_bits(val);
1664 u32 val_hi = upper_32_bits(val);
1665
1666 writel(val_lo, ptr);
1667 writel(val_hi, ptr + 1);
1668}
1669
1670static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1671{
1672 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1673}
1674
1675
1676void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1677void xhci_print_registers(struct xhci_hcd *xhci);
1678void xhci_dbg_regs(struct xhci_hcd *xhci);
1679void xhci_print_run_regs(struct xhci_hcd *xhci);
1680void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1681void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1682void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1683void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1684void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1685void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1686void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1687void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1688char *xhci_get_slot_state(struct xhci_hcd *xhci,
1689 struct xhci_container_ctx *ctx);
1690void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1691 unsigned int slot_id, unsigned int ep_index,
1692 struct xhci_virt_ep *ep);
1693void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1694 const char *fmt, ...);
1695
1696
1697void xhci_mem_cleanup(struct xhci_hcd *xhci);
1698int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1699void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1700int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1701int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1702void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1703 struct usb_device *udev);
1704unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1705unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1706unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1707unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1708unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1709void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1710void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1711 struct xhci_bw_info *ep_bw,
1712 struct xhci_interval_bw_table *bw_table,
1713 struct usb_device *udev,
1714 struct xhci_virt_ep *virt_ep,
1715 struct xhci_tt_bw_info *tt_info);
1716void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1717 struct xhci_virt_device *virt_dev,
1718 int old_active_eps);
1719void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1720void xhci_update_bw_info(struct xhci_hcd *xhci,
1721 struct xhci_container_ctx *in_ctx,
1722 struct xhci_input_control_ctx *ctrl_ctx,
1723 struct xhci_virt_device *virt_dev);
1724void xhci_endpoint_copy(struct xhci_hcd *xhci,
1725 struct xhci_container_ctx *in_ctx,
1726 struct xhci_container_ctx *out_ctx,
1727 unsigned int ep_index);
1728void xhci_slot_copy(struct xhci_hcd *xhci,
1729 struct xhci_container_ctx *in_ctx,
1730 struct xhci_container_ctx *out_ctx);
1731int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1732 struct usb_device *udev, struct usb_host_endpoint *ep,
1733 gfp_t mem_flags);
1734void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1735int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1736 unsigned int num_trbs, gfp_t flags);
1737void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1738 struct xhci_virt_device *virt_dev,
1739 unsigned int ep_index);
1740struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1741 unsigned int num_stream_ctxs,
1742 unsigned int num_streams, gfp_t flags);
1743void xhci_free_stream_info(struct xhci_hcd *xhci,
1744 struct xhci_stream_info *stream_info);
1745void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1746 struct xhci_ep_ctx *ep_ctx,
1747 struct xhci_stream_info *stream_info);
1748void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
1749 struct xhci_virt_ep *ep);
1750void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1751 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1752struct xhci_ring *xhci_dma_to_transfer_ring(
1753 struct xhci_virt_ep *ep,
1754 u64 address);
1755struct xhci_ring *xhci_stream_id_to_ring(
1756 struct xhci_virt_device *dev,
1757 unsigned int ep_index,
1758 unsigned int stream_id);
1759struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1760 bool allocate_in_ctx, bool allocate_completion,
1761 gfp_t mem_flags);
1762void xhci_urb_free_priv(struct urb_priv *urb_priv);
1763void xhci_free_command(struct xhci_hcd *xhci,
1764 struct xhci_command *command);
1765
1766
1767typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1768int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
1769void xhci_quiesce(struct xhci_hcd *xhci);
1770int xhci_halt(struct xhci_hcd *xhci);
1771int xhci_reset(struct xhci_hcd *xhci);
1772int xhci_init(struct usb_hcd *hcd);
1773int xhci_run(struct usb_hcd *hcd);
1774void xhci_stop(struct usb_hcd *hcd);
1775void xhci_shutdown(struct usb_hcd *hcd);
1776int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1777void xhci_init_driver(struct hc_driver *drv,
1778 const struct xhci_driver_overrides *over);
1779
1780#ifdef CONFIG_PM
1781int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1782int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1783#else
1784#define xhci_suspend NULL
1785#define xhci_resume NULL
1786#endif
1787
1788int xhci_get_frame(struct usb_hcd *hcd);
1789irqreturn_t xhci_irq(struct usb_hcd *hcd);
1790irqreturn_t xhci_msi_irq(int irq, void *hcd);
1791int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1792void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1793int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1794 struct xhci_virt_device *virt_dev,
1795 struct usb_device *hdev,
1796 struct usb_tt *tt, gfp_t mem_flags);
1797int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1798 struct usb_host_endpoint **eps, unsigned int num_eps,
1799 unsigned int num_streams, gfp_t mem_flags);
1800int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1801 struct usb_host_endpoint **eps, unsigned int num_eps,
1802 gfp_t mem_flags);
1803int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1804int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev);
1805int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1806int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1807 struct usb_device *udev, int enable);
1808int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1809 struct usb_tt *tt, gfp_t mem_flags);
1810int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1811int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1812int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1813int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1814void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1815int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1816int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1817void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1818
1819
1820dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1821struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1822 struct xhci_segment *start_seg, union xhci_trb *start_trb,
1823 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
1824int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1825void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1826int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
1827 u32 trb_type, u32 slot_id);
1828int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1829 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
1830int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
1831 u32 field1, u32 field2, u32 field3, u32 field4);
1832int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
1833 int slot_id, unsigned int ep_index, int suspend);
1834int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1835 int slot_id, unsigned int ep_index);
1836int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1837 int slot_id, unsigned int ep_index);
1838int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1839 int slot_id, unsigned int ep_index);
1840int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1841 struct urb *urb, int slot_id, unsigned int ep_index);
1842int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
1843 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
1844 bool command_must_succeed);
1845int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
1846 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
1847int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
1848 int slot_id, unsigned int ep_index);
1849int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1850 u32 slot_id);
1851void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1852 unsigned int slot_id, unsigned int ep_index,
1853 unsigned int stream_id, struct xhci_td *cur_td,
1854 struct xhci_dequeue_state *state);
1855void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1856 unsigned int slot_id, unsigned int ep_index,
1857 unsigned int stream_id,
1858 struct xhci_dequeue_state *deq_state);
1859void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1860 unsigned int ep_index, struct xhci_td *td);
1861void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1862 unsigned int slot_id, unsigned int ep_index,
1863 struct xhci_dequeue_state *deq_state);
1864void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1865void xhci_handle_command_timeout(unsigned long data);
1866
1867void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1868 unsigned int ep_index, unsigned int stream_id);
1869void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
1870
1871
1872void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1873 int port_id, u32 link_state);
1874int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
1875 struct usb_device *udev, enum usb3_link_state state);
1876int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
1877 struct usb_device *udev, enum usb3_link_state state);
1878void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1879 int port_id, u32 port_bit);
1880int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1881 char *buf, u16 wLength);
1882int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1883int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1884
1885#ifdef CONFIG_PM
1886int xhci_bus_suspend(struct usb_hcd *hcd);
1887int xhci_bus_resume(struct usb_hcd *hcd);
1888#else
1889#define xhci_bus_suspend NULL
1890#define xhci_bus_resume NULL
1891#endif
1892
1893u32 xhci_port_state_to_neutral(u32 state);
1894int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1895 u16 port);
1896void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1897
1898
1899struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
1900struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1901struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1902
1903#endif
1904