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23#ifndef __LINUX_MFD_MAX8998_PRIV_H
24#define __LINUX_MFD_MAX8998_PRIV_H
25
26#define MAX8998_NUM_IRQ_REGS 4
27
28
29enum {
30 MAX8998_REG_IRQ1,
31 MAX8998_REG_IRQ2,
32 MAX8998_REG_IRQ3,
33 MAX8998_REG_IRQ4,
34 MAX8998_REG_IRQM1,
35 MAX8998_REG_IRQM2,
36 MAX8998_REG_IRQM3,
37 MAX8998_REG_IRQM4,
38 MAX8998_REG_STATUS1,
39 MAX8998_REG_STATUS2,
40 MAX8998_REG_STATUSM1,
41 MAX8998_REG_STATUSM2,
42 MAX8998_REG_CHGR1,
43 MAX8998_REG_CHGR2,
44 MAX8998_REG_LDO_ACTIVE_DISCHARGE1,
45 MAX8998_REG_LDO_ACTIVE_DISCHARGE2,
46 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
47 MAX8998_REG_ONOFF1,
48 MAX8998_REG_ONOFF2,
49 MAX8998_REG_ONOFF3,
50 MAX8998_REG_ONOFF4,
51 MAX8998_REG_BUCK1_VOLTAGE1,
52 MAX8998_REG_BUCK1_VOLTAGE2,
53 MAX8998_REG_BUCK1_VOLTAGE3,
54 MAX8998_REG_BUCK1_VOLTAGE4,
55 MAX8998_REG_BUCK2_VOLTAGE1,
56 MAX8998_REG_BUCK2_VOLTAGE2,
57 MAX8998_REG_BUCK3,
58 MAX8998_REG_BUCK4,
59 MAX8998_REG_LDO2_LDO3,
60 MAX8998_REG_LDO4,
61 MAX8998_REG_LDO5,
62 MAX8998_REG_LDO6,
63 MAX8998_REG_LDO7,
64 MAX8998_REG_LDO8_LDO9,
65 MAX8998_REG_LDO10_LDO11,
66 MAX8998_REG_LDO12,
67 MAX8998_REG_LDO13,
68 MAX8998_REG_LDO14,
69 MAX8998_REG_LDO15,
70 MAX8998_REG_LDO16,
71 MAX8998_REG_LDO17,
72 MAX8998_REG_BKCHR,
73 MAX8998_REG_LBCNFG1,
74 MAX8998_REG_LBCNFG2,
75};
76
77
78enum {
79 MAX8998_IRQ_DCINF,
80 MAX8998_IRQ_DCINR,
81 MAX8998_IRQ_JIGF,
82 MAX8998_IRQ_JIGR,
83 MAX8998_IRQ_PWRONF,
84 MAX8998_IRQ_PWRONR,
85
86 MAX8998_IRQ_WTSREVNT,
87 MAX8998_IRQ_SMPLEVNT,
88 MAX8998_IRQ_ALARM1,
89 MAX8998_IRQ_ALARM0,
90
91 MAX8998_IRQ_ONKEY1S,
92 MAX8998_IRQ_TOPOFFR,
93 MAX8998_IRQ_DCINOVPR,
94 MAX8998_IRQ_CHGRSTF,
95 MAX8998_IRQ_DONER,
96 MAX8998_IRQ_CHGFAULT,
97
98 MAX8998_IRQ_LOBAT1,
99 MAX8998_IRQ_LOBAT2,
100
101 MAX8998_IRQ_NR,
102};
103
104
105enum {
106 TYPE_MAX8998 = 0,
107 TYPE_LP3974,
108 TYPE_LP3979,
109};
110
111#define MAX8998_IRQ_DCINF_MASK (1 << 2)
112#define MAX8998_IRQ_DCINR_MASK (1 << 3)
113#define MAX8998_IRQ_JIGF_MASK (1 << 4)
114#define MAX8998_IRQ_JIGR_MASK (1 << 5)
115#define MAX8998_IRQ_PWRONF_MASK (1 << 6)
116#define MAX8998_IRQ_PWRONR_MASK (1 << 7)
117
118#define MAX8998_IRQ_WTSREVNT_MASK (1 << 0)
119#define MAX8998_IRQ_SMPLEVNT_MASK (1 << 1)
120#define MAX8998_IRQ_ALARM1_MASK (1 << 2)
121#define MAX8998_IRQ_ALARM0_MASK (1 << 3)
122
123#define MAX8998_IRQ_ONKEY1S_MASK (1 << 0)
124#define MAX8998_IRQ_TOPOFFR_MASK (1 << 2)
125#define MAX8998_IRQ_DCINOVPR_MASK (1 << 3)
126#define MAX8998_IRQ_CHGRSTF_MASK (1 << 4)
127#define MAX8998_IRQ_DONER_MASK (1 << 5)
128#define MAX8998_IRQ_CHGFAULT_MASK (1 << 7)
129
130#define MAX8998_IRQ_LOBAT1_MASK (1 << 0)
131#define MAX8998_IRQ_LOBAT2_MASK (1 << 1)
132
133#define MAX8998_ENRAMP (1 << 4)
134
135struct irq_domain;
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151
152struct max8998_dev {
153 struct device *dev;
154 struct max8998_platform_data *pdata;
155 struct i2c_client *i2c;
156 struct i2c_client *rtc;
157 struct mutex iolock;
158 struct mutex irqlock;
159
160 unsigned int irq_base;
161 struct irq_domain *irq_domain;
162 int irq;
163 int ono;
164 u8 irq_masks_cur[MAX8998_NUM_IRQ_REGS];
165 u8 irq_masks_cache[MAX8998_NUM_IRQ_REGS];
166 unsigned long type;
167 bool wakeup;
168};
169
170int max8998_irq_init(struct max8998_dev *max8998);
171void max8998_irq_exit(struct max8998_dev *max8998);
172int max8998_irq_resume(struct max8998_dev *max8998);
173
174extern int max8998_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
175extern int max8998_bulk_read(struct i2c_client *i2c, u8 reg, int count,
176 u8 *buf);
177extern int max8998_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
178extern int max8998_bulk_write(struct i2c_client *i2c, u8 reg, int count,
179 u8 *buf);
180extern int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
181
182#endif
183