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19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24
25#include <asm/tlb.h>
26#include <asm/mach/map.h>
27
28#include <linux/omap-dma.h>
29
30#include "omap_hwmod.h"
31#include "soc.h"
32#include "iomap.h"
33#include "voltage.h"
34#include "powerdomain.h"
35#include "clockdomain.h"
36#include "common.h"
37#include "clock.h"
38#include "clock2xxx.h"
39#include "clock3xxx.h"
40#include "omap-pm.h"
41#include "sdrc.h"
42#include "control.h"
43#include "serial.h"
44#include "sram.h"
45#include "cm2xxx.h"
46#include "cm3xxx.h"
47#include "cm33xx.h"
48#include "cm44xx.h"
49#include "prm.h"
50#include "cm.h"
51#include "prcm_mpu44xx.h"
52#include "prminst44xx.h"
53#include "prm2xxx.h"
54#include "prm3xxx.h"
55#include "prm33xx.h"
56#include "prm44xx.h"
57#include "opp2xxx.h"
58
59
60
61
62
63static int (*omap_clk_soc_init)(void);
64
65
66
67
68
69
70#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
71static struct map_desc omap24xx_io_desc[] __initdata = {
72 {
73 .virtual = L3_24XX_VIRT,
74 .pfn = __phys_to_pfn(L3_24XX_PHYS),
75 .length = L3_24XX_SIZE,
76 .type = MT_DEVICE
77 },
78 {
79 .virtual = L4_24XX_VIRT,
80 .pfn = __phys_to_pfn(L4_24XX_PHYS),
81 .length = L4_24XX_SIZE,
82 .type = MT_DEVICE
83 },
84};
85
86#ifdef CONFIG_SOC_OMAP2420
87static struct map_desc omap242x_io_desc[] __initdata = {
88 {
89 .virtual = DSP_MEM_2420_VIRT,
90 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
91 .length = DSP_MEM_2420_SIZE,
92 .type = MT_DEVICE
93 },
94 {
95 .virtual = DSP_IPI_2420_VIRT,
96 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
97 .length = DSP_IPI_2420_SIZE,
98 .type = MT_DEVICE
99 },
100 {
101 .virtual = DSP_MMU_2420_VIRT,
102 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
103 .length = DSP_MMU_2420_SIZE,
104 .type = MT_DEVICE
105 },
106};
107
108#endif
109
110#ifdef CONFIG_SOC_OMAP2430
111static struct map_desc omap243x_io_desc[] __initdata = {
112 {
113 .virtual = L4_WK_243X_VIRT,
114 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
115 .length = L4_WK_243X_SIZE,
116 .type = MT_DEVICE
117 },
118 {
119 .virtual = OMAP243X_GPMC_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
121 .length = OMAP243X_GPMC_SIZE,
122 .type = MT_DEVICE
123 },
124 {
125 .virtual = OMAP243X_SDRC_VIRT,
126 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
127 .length = OMAP243X_SDRC_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = OMAP243X_SMS_VIRT,
132 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
133 .length = OMAP243X_SMS_SIZE,
134 .type = MT_DEVICE
135 },
136};
137#endif
138#endif
139
140#ifdef CONFIG_ARCH_OMAP3
141static struct map_desc omap34xx_io_desc[] __initdata = {
142 {
143 .virtual = L3_34XX_VIRT,
144 .pfn = __phys_to_pfn(L3_34XX_PHYS),
145 .length = L3_34XX_SIZE,
146 .type = MT_DEVICE
147 },
148 {
149 .virtual = L4_34XX_VIRT,
150 .pfn = __phys_to_pfn(L4_34XX_PHYS),
151 .length = L4_34XX_SIZE,
152 .type = MT_DEVICE
153 },
154 {
155 .virtual = OMAP34XX_GPMC_VIRT,
156 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
157 .length = OMAP34XX_GPMC_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = OMAP343X_SMS_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
163 .length = OMAP343X_SMS_SIZE,
164 .type = MT_DEVICE
165 },
166 {
167 .virtual = OMAP343X_SDRC_VIRT,
168 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
169 .length = OMAP343X_SDRC_SIZE,
170 .type = MT_DEVICE
171 },
172 {
173 .virtual = L4_PER_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
175 .length = L4_PER_34XX_SIZE,
176 .type = MT_DEVICE
177 },
178 {
179 .virtual = L4_EMU_34XX_VIRT,
180 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
181 .length = L4_EMU_34XX_SIZE,
182 .type = MT_DEVICE
183 },
184};
185#endif
186
187#ifdef CONFIG_SOC_TI81XX
188static struct map_desc omapti81xx_io_desc[] __initdata = {
189 {
190 .virtual = L4_34XX_VIRT,
191 .pfn = __phys_to_pfn(L4_34XX_PHYS),
192 .length = L4_34XX_SIZE,
193 .type = MT_DEVICE
194 }
195};
196#endif
197
198#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
199static struct map_desc omapam33xx_io_desc[] __initdata = {
200 {
201 .virtual = L4_34XX_VIRT,
202 .pfn = __phys_to_pfn(L4_34XX_PHYS),
203 .length = L4_34XX_SIZE,
204 .type = MT_DEVICE
205 },
206 {
207 .virtual = L4_WK_AM33XX_VIRT,
208 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
209 .length = L4_WK_AM33XX_SIZE,
210 .type = MT_DEVICE
211 }
212};
213#endif
214
215#ifdef CONFIG_ARCH_OMAP4
216static struct map_desc omap44xx_io_desc[] __initdata = {
217 {
218 .virtual = L3_44XX_VIRT,
219 .pfn = __phys_to_pfn(L3_44XX_PHYS),
220 .length = L3_44XX_SIZE,
221 .type = MT_DEVICE,
222 },
223 {
224 .virtual = L4_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_44XX_PHYS),
226 .length = L4_44XX_SIZE,
227 .type = MT_DEVICE,
228 },
229 {
230 .virtual = L4_PER_44XX_VIRT,
231 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
232 .length = L4_PER_44XX_SIZE,
233 .type = MT_DEVICE,
234 },
235};
236#endif
237
238#ifdef CONFIG_SOC_OMAP5
239static struct map_desc omap54xx_io_desc[] __initdata = {
240 {
241 .virtual = L3_54XX_VIRT,
242 .pfn = __phys_to_pfn(L3_54XX_PHYS),
243 .length = L3_54XX_SIZE,
244 .type = MT_DEVICE,
245 },
246 {
247 .virtual = L4_54XX_VIRT,
248 .pfn = __phys_to_pfn(L4_54XX_PHYS),
249 .length = L4_54XX_SIZE,
250 .type = MT_DEVICE,
251 },
252 {
253 .virtual = L4_WK_54XX_VIRT,
254 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
255 .length = L4_WK_54XX_SIZE,
256 .type = MT_DEVICE,
257 },
258 {
259 .virtual = L4_PER_54XX_VIRT,
260 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
261 .length = L4_PER_54XX_SIZE,
262 .type = MT_DEVICE,
263 },
264};
265#endif
266
267#ifdef CONFIG_SOC_DRA7XX
268static struct map_desc dra7xx_io_desc[] __initdata = {
269 {
270 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
271 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
272 .length = L4_CFG_MPU_DRA7XX_SIZE,
273 .type = MT_DEVICE,
274 },
275 {
276 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
277 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
278 .length = L3_MAIN_SN_DRA7XX_SIZE,
279 .type = MT_DEVICE,
280 },
281 {
282 .virtual = L4_PER1_DRA7XX_VIRT,
283 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
284 .length = L4_PER1_DRA7XX_SIZE,
285 .type = MT_DEVICE,
286 },
287 {
288 .virtual = L4_PER2_DRA7XX_VIRT,
289 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
290 .length = L4_PER2_DRA7XX_SIZE,
291 .type = MT_DEVICE,
292 },
293 {
294 .virtual = L4_PER3_DRA7XX_VIRT,
295 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
296 .length = L4_PER3_DRA7XX_SIZE,
297 .type = MT_DEVICE,
298 },
299 {
300 .virtual = L4_CFG_DRA7XX_VIRT,
301 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
302 .length = L4_CFG_DRA7XX_SIZE,
303 .type = MT_DEVICE,
304 },
305 {
306 .virtual = L4_WKUP_DRA7XX_VIRT,
307 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
308 .length = L4_WKUP_DRA7XX_SIZE,
309 .type = MT_DEVICE,
310 },
311};
312#endif
313
314#ifdef CONFIG_SOC_OMAP2420
315void __init omap242x_map_io(void)
316{
317 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
318 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
319}
320#endif
321
322#ifdef CONFIG_SOC_OMAP2430
323void __init omap243x_map_io(void)
324{
325 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
326 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
327}
328#endif
329
330#ifdef CONFIG_ARCH_OMAP3
331void __init omap3_map_io(void)
332{
333 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
334}
335#endif
336
337#ifdef CONFIG_SOC_TI81XX
338void __init ti81xx_map_io(void)
339{
340 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
341}
342#endif
343
344#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
345void __init am33xx_map_io(void)
346{
347 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
348}
349#endif
350
351#ifdef CONFIG_ARCH_OMAP4
352void __init omap4_map_io(void)
353{
354 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
355 omap_barriers_init();
356}
357#endif
358
359#ifdef CONFIG_SOC_OMAP5
360void __init omap5_map_io(void)
361{
362 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
363 omap_barriers_init();
364}
365#endif
366
367#ifdef CONFIG_SOC_DRA7XX
368void __init dra7xx_map_io(void)
369{
370 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
371}
372#endif
373
374
375
376
377
378
379
380
381
382
383static int __init _omap2_init_reprogram_sdrc(void)
384{
385 struct clk *dpll3_m2_ck;
386 int v = -EINVAL;
387 long rate;
388
389 if (!cpu_is_omap34xx())
390 return 0;
391
392 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
393 if (IS_ERR(dpll3_m2_ck))
394 return -EINVAL;
395
396 rate = clk_get_rate(dpll3_m2_ck);
397 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
398 v = clk_set_rate(dpll3_m2_ck, rate);
399 if (v)
400 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
401
402 clk_put(dpll3_m2_ck);
403
404 return v;
405}
406
407static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
408{
409 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
410}
411
412static void __init omap_hwmod_init_postsetup(void)
413{
414 u8 postsetup_state;
415
416
417#ifdef CONFIG_PM
418 postsetup_state = _HWMOD_STATE_IDLE;
419#else
420 postsetup_state = _HWMOD_STATE_ENABLED;
421#endif
422 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
423
424 omap_pm_if_early_init();
425}
426
427static void __init __maybe_unused omap_common_late_init(void)
428{
429 omap_mux_late_init();
430 omap2_common_pm_late_init();
431 omap_soc_device_init();
432}
433
434#ifdef CONFIG_SOC_OMAP2420
435void __init omap2420_init_early(void)
436{
437 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
438 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
439 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
440 omap2_control_base_init();
441 omap2xxx_check_revision();
442 omap2_prcm_base_init();
443 omap2xxx_voltagedomains_init();
444 omap242x_powerdomains_init();
445 omap242x_clockdomains_init();
446 omap2420_hwmod_init();
447 omap_hwmod_init_postsetup();
448 omap_clk_soc_init = omap2420_dt_clk_init;
449 rate_table = omap2420_rate_table;
450}
451
452void __init omap2420_init_late(void)
453{
454 omap_common_late_init();
455 omap2_pm_init();
456 omap2_clk_enable_autoidle_all();
457}
458#endif
459
460#ifdef CONFIG_SOC_OMAP2430
461void __init omap2430_init_early(void)
462{
463 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
464 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
465 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
466 omap2_control_base_init();
467 omap2xxx_check_revision();
468 omap2_prcm_base_init();
469 omap2xxx_voltagedomains_init();
470 omap243x_powerdomains_init();
471 omap243x_clockdomains_init();
472 omap2430_hwmod_init();
473 omap_hwmod_init_postsetup();
474 omap_clk_soc_init = omap2430_dt_clk_init;
475 rate_table = omap2430_rate_table;
476}
477
478void __init omap2430_init_late(void)
479{
480 omap_common_late_init();
481 omap2_pm_init();
482 omap2_clk_enable_autoidle_all();
483}
484#endif
485
486
487
488
489
490#ifdef CONFIG_ARCH_OMAP3
491void __init omap3_init_early(void)
492{
493 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
494 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
495 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
496
497 if (!of_have_populated_dt()) {
498 omap2_set_globals_control(
499 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
500 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
501 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
502 NULL);
503 }
504 omap2_control_base_init();
505 omap3xxx_check_revision();
506 omap3xxx_check_features();
507 omap2_prcm_base_init();
508
509 if (!of_have_populated_dt()) {
510 omap3xxx_prm_init(NULL);
511 omap3xxx_cm_init(NULL);
512 }
513 omap3xxx_voltagedomains_init();
514 omap3xxx_powerdomains_init();
515 omap3xxx_clockdomains_init();
516 omap3xxx_hwmod_init();
517 omap_hwmod_init_postsetup();
518 if (!of_have_populated_dt()) {
519 omap3_control_legacy_iomap_init();
520 if (soc_is_am35xx())
521 omap_clk_soc_init = am35xx_clk_legacy_init;
522 else if (cpu_is_omap3630())
523 omap_clk_soc_init = omap36xx_clk_legacy_init;
524 else if (omap_rev() == OMAP3430_REV_ES1_0)
525 omap_clk_soc_init = omap3430es1_clk_legacy_init;
526 else
527 omap_clk_soc_init = omap3430_clk_legacy_init;
528 }
529}
530
531void __init omap3430_init_early(void)
532{
533 omap3_init_early();
534 if (of_have_populated_dt())
535 omap_clk_soc_init = omap3430_dt_clk_init;
536}
537
538void __init omap35xx_init_early(void)
539{
540 omap3_init_early();
541 if (of_have_populated_dt())
542 omap_clk_soc_init = omap3430_dt_clk_init;
543}
544
545void __init omap3630_init_early(void)
546{
547 omap3_init_early();
548 if (of_have_populated_dt())
549 omap_clk_soc_init = omap3630_dt_clk_init;
550}
551
552void __init am35xx_init_early(void)
553{
554 omap3_init_early();
555 if (of_have_populated_dt())
556 omap_clk_soc_init = am35xx_dt_clk_init;
557}
558
559void __init omap3_init_late(void)
560{
561 omap_common_late_init();
562 omap3_pm_init();
563 omap2_clk_enable_autoidle_all();
564}
565
566void __init omap3430_init_late(void)
567{
568 omap_common_late_init();
569 omap3_pm_init();
570 omap2_clk_enable_autoidle_all();
571}
572
573void __init omap35xx_init_late(void)
574{
575 omap_common_late_init();
576 omap3_pm_init();
577 omap2_clk_enable_autoidle_all();
578}
579
580void __init omap3630_init_late(void)
581{
582 omap_common_late_init();
583 omap3_pm_init();
584 omap2_clk_enable_autoidle_all();
585}
586
587void __init am35xx_init_late(void)
588{
589 omap_common_late_init();
590 omap3_pm_init();
591 omap2_clk_enable_autoidle_all();
592}
593
594void __init ti81xx_init_late(void)
595{
596 omap_common_late_init();
597 omap2_clk_enable_autoidle_all();
598}
599#endif
600
601#ifdef CONFIG_SOC_TI81XX
602void __init ti814x_init_early(void)
603{
604 omap2_set_globals_tap(TI814X_CLASS,
605 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
606 omap2_control_base_init();
607 omap3xxx_check_revision();
608 ti81xx_check_features();
609 omap2_prcm_base_init();
610 omap3xxx_voltagedomains_init();
611 omap3xxx_powerdomains_init();
612 ti814x_clockdomains_init();
613 dm814x_hwmod_init();
614 omap_hwmod_init_postsetup();
615 if (of_have_populated_dt())
616 omap_clk_soc_init = dm814x_dt_clk_init;
617}
618
619void __init ti816x_init_early(void)
620{
621 omap2_set_globals_tap(TI816X_CLASS,
622 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
623 omap2_control_base_init();
624 omap3xxx_check_revision();
625 ti81xx_check_features();
626 omap2_prcm_base_init();
627 omap3xxx_voltagedomains_init();
628 omap3xxx_powerdomains_init();
629 ti816x_clockdomains_init();
630 dm816x_hwmod_init();
631 omap_hwmod_init_postsetup();
632 if (of_have_populated_dt())
633 omap_clk_soc_init = dm816x_dt_clk_init;
634}
635#endif
636
637#ifdef CONFIG_SOC_AM33XX
638void __init am33xx_init_early(void)
639{
640 omap2_set_globals_tap(AM335X_CLASS,
641 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
642 omap2_control_base_init();
643 omap3xxx_check_revision();
644 am33xx_check_features();
645 omap2_prcm_base_init();
646 am33xx_powerdomains_init();
647 am33xx_clockdomains_init();
648 am33xx_hwmod_init();
649 omap_hwmod_init_postsetup();
650 omap_clk_soc_init = am33xx_dt_clk_init;
651}
652
653void __init am33xx_init_late(void)
654{
655 omap_common_late_init();
656}
657#endif
658
659#ifdef CONFIG_SOC_AM43XX
660void __init am43xx_init_early(void)
661{
662 omap2_set_globals_tap(AM335X_CLASS,
663 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
664 omap2_control_base_init();
665 omap3xxx_check_revision();
666 am33xx_check_features();
667 omap2_prcm_base_init();
668 am43xx_powerdomains_init();
669 am43xx_clockdomains_init();
670 am43xx_hwmod_init();
671 omap_hwmod_init_postsetup();
672 omap_l2_cache_init();
673 omap_clk_soc_init = am43xx_dt_clk_init;
674}
675
676void __init am43xx_init_late(void)
677{
678 omap_common_late_init();
679 omap2_clk_enable_autoidle_all();
680}
681#endif
682
683#ifdef CONFIG_ARCH_OMAP4
684void __init omap4430_init_early(void)
685{
686 omap2_set_globals_tap(OMAP443X_CLASS,
687 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
688 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
689 omap2_control_base_init();
690 omap4xxx_check_revision();
691 omap4xxx_check_features();
692 omap2_prcm_base_init();
693 omap4_pm_init_early();
694 omap44xx_voltagedomains_init();
695 omap44xx_powerdomains_init();
696 omap44xx_clockdomains_init();
697 omap44xx_hwmod_init();
698 omap_hwmod_init_postsetup();
699 omap_l2_cache_init();
700 omap_clk_soc_init = omap4xxx_dt_clk_init;
701}
702
703void __init omap4430_init_late(void)
704{
705 omap_common_late_init();
706 omap4_pm_init();
707 omap2_clk_enable_autoidle_all();
708}
709#endif
710
711#ifdef CONFIG_SOC_OMAP5
712void __init omap5_init_early(void)
713{
714 omap2_set_globals_tap(OMAP54XX_CLASS,
715 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
716 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
717 omap2_control_base_init();
718 omap4_pm_init_early();
719 omap2_prcm_base_init();
720 omap5xxx_check_revision();
721 omap54xx_voltagedomains_init();
722 omap54xx_powerdomains_init();
723 omap54xx_clockdomains_init();
724 omap54xx_hwmod_init();
725 omap_hwmod_init_postsetup();
726 omap_clk_soc_init = omap5xxx_dt_clk_init;
727}
728
729void __init omap5_init_late(void)
730{
731 omap_common_late_init();
732 omap4_pm_init();
733 omap2_clk_enable_autoidle_all();
734}
735#endif
736
737#ifdef CONFIG_SOC_DRA7XX
738void __init dra7xx_init_early(void)
739{
740 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
741 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
742 omap2_control_base_init();
743 omap4_pm_init_early();
744 omap2_prcm_base_init();
745 dra7xxx_check_revision();
746 dra7xx_powerdomains_init();
747 dra7xx_clockdomains_init();
748 dra7xx_hwmod_init();
749 omap_hwmod_init_postsetup();
750 omap_clk_soc_init = dra7xx_dt_clk_init;
751}
752
753void __init dra7xx_init_late(void)
754{
755 omap_common_late_init();
756 omap4_pm_init();
757 omap2_clk_enable_autoidle_all();
758}
759#endif
760
761
762void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
763 struct omap_sdrc_params *sdrc_cs1)
764{
765 omap_sram_init();
766
767 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
768 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
769 _omap2_init_reprogram_sdrc();
770 }
771}
772
773int __init omap_clk_init(void)
774{
775 int ret = 0;
776
777 if (!omap_clk_soc_init)
778 return 0;
779
780 ti_clk_init_features();
781
782 omap2_clk_setup_ll_ops();
783
784 if (of_have_populated_dt()) {
785 ret = omap_control_init();
786 if (ret)
787 return ret;
788
789 ret = omap_prcm_init();
790 if (ret)
791 return ret;
792
793 of_clk_init(NULL);
794
795 ti_dt_clk_init_retry_clks();
796
797 ti_dt_clockdomains_setup();
798 }
799
800 ret = omap_clk_soc_init();
801
802 return ret;
803}
804
