1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/platform_data/hsmmc-omap.h>
23#include <linux/power/smartreflex.h>
24#include <linux/i2c-omap.h>
25
26#include <linux/omap-dma.h>
27#include <linux/platform_data/spi-omap2-mcspi.h>
28#include <linux/platform_data/asoc-ti-mcbsp.h>
29#include <plat/dmtimer.h>
30
31#include "omap_hwmod.h"
32#include "omap_hwmod_common_data.h"
33#include "cm1_54xx.h"
34#include "cm2_54xx.h"
35#include "prm54xx.h"
36#include "i2c.h"
37#include "wd_timer.h"
38
39
40#define OMAP54XX_IRQ_GIC_START 32
41
42
43#define OMAP54XX_DMA_REQ_START 1
44
45
46
47
48
49
50
51
52
53
54static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
55 .name = "dmm",
56};
57
58
59static struct omap_hwmod omap54xx_dmm_hwmod = {
60 .name = "dmm",
61 .class = &omap54xx_dmm_hwmod_class,
62 .clkdm_name = "emif_clkdm",
63 .prcm = {
64 .omap4 = {
65 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
66 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
67 },
68 },
69};
70
71
72
73
74
75static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
76 .name = "l3",
77};
78
79
80static struct omap_hwmod omap54xx_l3_instr_hwmod = {
81 .name = "l3_instr",
82 .class = &omap54xx_l3_hwmod_class,
83 .clkdm_name = "l3instr_clkdm",
84 .prcm = {
85 .omap4 = {
86 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
87 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
88 .modulemode = MODULEMODE_HWCTRL,
89 },
90 },
91};
92
93
94static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
95 .name = "l3_main_1",
96 .class = &omap54xx_l3_hwmod_class,
97 .clkdm_name = "l3main1_clkdm",
98 .prcm = {
99 .omap4 = {
100 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
101 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
102 },
103 },
104};
105
106
107static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
108 .name = "l3_main_2",
109 .class = &omap54xx_l3_hwmod_class,
110 .clkdm_name = "l3main2_clkdm",
111 .prcm = {
112 .omap4 = {
113 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
114 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
115 },
116 },
117};
118
119
120static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
121 .name = "l3_main_3",
122 .class = &omap54xx_l3_hwmod_class,
123 .clkdm_name = "l3instr_clkdm",
124 .prcm = {
125 .omap4 = {
126 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
127 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
128 .modulemode = MODULEMODE_HWCTRL,
129 },
130 },
131};
132
133
134
135
136
137static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
138 .name = "l4",
139};
140
141
142static struct omap_hwmod omap54xx_l4_abe_hwmod = {
143 .name = "l4_abe",
144 .class = &omap54xx_l4_hwmod_class,
145 .clkdm_name = "abe_clkdm",
146 .prcm = {
147 .omap4 = {
148 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
149 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
150 },
151 },
152};
153
154
155static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
156 .name = "l4_cfg",
157 .class = &omap54xx_l4_hwmod_class,
158 .clkdm_name = "l4cfg_clkdm",
159 .prcm = {
160 .omap4 = {
161 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
162 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
163 },
164 },
165};
166
167
168static struct omap_hwmod omap54xx_l4_per_hwmod = {
169 .name = "l4_per",
170 .class = &omap54xx_l4_hwmod_class,
171 .clkdm_name = "l4per_clkdm",
172 .prcm = {
173 .omap4 = {
174 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
175 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
176 },
177 },
178};
179
180
181static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
182 .name = "l4_wkup",
183 .class = &omap54xx_l4_hwmod_class,
184 .clkdm_name = "wkupaon_clkdm",
185 .prcm = {
186 .omap4 = {
187 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
188 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
189 },
190 },
191};
192
193
194
195
196
197static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
198 .name = "mpu_bus",
199};
200
201
202static struct omap_hwmod omap54xx_mpu_private_hwmod = {
203 .name = "mpu_private",
204 .class = &omap54xx_mpu_bus_hwmod_class,
205 .clkdm_name = "mpu_clkdm",
206 .prcm = {
207 .omap4 = {
208 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
209 },
210 },
211};
212
213
214
215
216
217
218static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
219 .rev_offs = 0x0000,
220 .sysc_offs = 0x0010,
221 .sysc_flags = SYSC_HAS_SIDLEMODE,
222 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
223 .sysc_fields = &omap_hwmod_sysc_type1,
224};
225
226static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
227 .name = "counter",
228 .sysc = &omap54xx_counter_sysc,
229};
230
231
232static struct omap_hwmod omap54xx_counter_32k_hwmod = {
233 .name = "counter_32k",
234 .class = &omap54xx_counter_hwmod_class,
235 .clkdm_name = "wkupaon_clkdm",
236 .flags = HWMOD_SWSUP_SIDLE,
237 .main_clk = "wkupaon_iclk_mux",
238 .prcm = {
239 .omap4 = {
240 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
241 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
242 },
243 },
244};
245
246
247
248
249
250
251
252static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
253 .rev_offs = 0x0000,
254 .sysc_offs = 0x002c,
255 .syss_offs = 0x0028,
256 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
257 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
258 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
259 SYSS_HAS_RESET_STATUS),
260 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
261 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
262 .sysc_fields = &omap_hwmod_sysc_type1,
263};
264
265static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
266 .name = "dma",
267 .sysc = &omap54xx_dma_sysc,
268};
269
270
271static struct omap_dma_dev_attr dma_dev_attr = {
272 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
273 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
274 .lch_count = 32,
275};
276
277
278static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
279 { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
280 { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
281 { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
282 { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
283 { .irq = -1 }
284};
285
286static struct omap_hwmod omap54xx_dma_system_hwmod = {
287 .name = "dma_system",
288 .class = &omap54xx_dma_hwmod_class,
289 .clkdm_name = "dma_clkdm",
290 .mpu_irqs = omap54xx_dma_system_irqs,
291 .xlate_irq = omap4_xlate_irq,
292 .main_clk = "l3_iclk_div",
293 .prcm = {
294 .omap4 = {
295 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
296 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
297 },
298 },
299 .dev_attr = &dma_dev_attr,
300};
301
302
303
304
305
306
307static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
308 .rev_offs = 0x0000,
309 .sysc_offs = 0x0010,
310 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
311 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
312 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
313 SIDLE_SMART_WKUP),
314 .sysc_fields = &omap_hwmod_sysc_type2,
315};
316
317static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
318 .name = "dmic",
319 .sysc = &omap54xx_dmic_sysc,
320};
321
322
323static struct omap_hwmod omap54xx_dmic_hwmod = {
324 .name = "dmic",
325 .class = &omap54xx_dmic_hwmod_class,
326 .clkdm_name = "abe_clkdm",
327 .main_clk = "dmic_gfclk",
328 .prcm = {
329 .omap4 = {
330 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
331 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
332 .modulemode = MODULEMODE_SWCTRL,
333 },
334 },
335};
336
337
338
339
340
341static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
342 .rev_offs = 0x0000,
343 .syss_offs = 0x0014,
344 .sysc_flags = SYSS_HAS_RESET_STATUS,
345};
346
347static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
348 .name = "dss",
349 .sysc = &omap54xx_dss_sysc,
350 .reset = omap_dss_reset,
351};
352
353
354static struct omap_hwmod_opt_clk dss_opt_clks[] = {
355 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
356 { .role = "sys_clk", .clk = "dss_sys_clk" },
357 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
358};
359
360static struct omap_hwmod omap54xx_dss_hwmod = {
361 .name = "dss_core",
362 .class = &omap54xx_dss_hwmod_class,
363 .clkdm_name = "dss_clkdm",
364 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
365 .main_clk = "dss_dss_clk",
366 .prcm = {
367 .omap4 = {
368 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
369 .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
370 .modulemode = MODULEMODE_SWCTRL,
371 },
372 },
373 .opt_clks = dss_opt_clks,
374 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
375};
376
377
378
379
380
381
382static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
383 .rev_offs = 0x0000,
384 .sysc_offs = 0x0010,
385 .syss_offs = 0x0014,
386 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
387 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
388 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
389 SYSS_HAS_RESET_STATUS),
390 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
391 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
392 .sysc_fields = &omap_hwmod_sysc_type1,
393};
394
395static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
396 .name = "dispc",
397 .sysc = &omap54xx_dispc_sysc,
398};
399
400
401static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
402 { .role = "sys_clk", .clk = "dss_sys_clk" },
403};
404
405
406static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
407 .has_framedonetv_irq = 1,
408 .manager_count = 4,
409};
410
411static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
412 .name = "dss_dispc",
413 .class = &omap54xx_dispc_hwmod_class,
414 .clkdm_name = "dss_clkdm",
415 .main_clk = "dss_dss_clk",
416 .prcm = {
417 .omap4 = {
418 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
419 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
420 },
421 },
422 .opt_clks = dss_dispc_opt_clks,
423 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
424 .dev_attr = &dss_dispc_dev_attr,
425 .parent_hwmod = &omap54xx_dss_hwmod,
426};
427
428
429
430
431
432
433static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
434 .rev_offs = 0x0000,
435 .sysc_offs = 0x0010,
436 .syss_offs = 0x0014,
437 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
438 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
439 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
440 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
441 .sysc_fields = &omap_hwmod_sysc_type1,
442};
443
444static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
445 .name = "dsi1",
446 .sysc = &omap54xx_dsi1_sysc,
447};
448
449
450static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
451 { .role = "sys_clk", .clk = "dss_sys_clk" },
452};
453
454static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
455 .name = "dss_dsi1",
456 .class = &omap54xx_dsi1_hwmod_class,
457 .clkdm_name = "dss_clkdm",
458 .main_clk = "dss_dss_clk",
459 .prcm = {
460 .omap4 = {
461 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
462 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
463 },
464 },
465 .opt_clks = dss_dsi1_a_opt_clks,
466 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
467 .parent_hwmod = &omap54xx_dss_hwmod,
468};
469
470
471static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
472 { .role = "sys_clk", .clk = "dss_sys_clk" },
473};
474
475static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
476 .name = "dss_dsi2",
477 .class = &omap54xx_dsi1_hwmod_class,
478 .clkdm_name = "dss_clkdm",
479 .main_clk = "dss_dss_clk",
480 .prcm = {
481 .omap4 = {
482 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
483 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
484 },
485 },
486 .opt_clks = dss_dsi1_c_opt_clks,
487 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
488 .parent_hwmod = &omap54xx_dss_hwmod,
489};
490
491
492
493
494
495
496static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
497 .rev_offs = 0x0000,
498 .sysc_offs = 0x0010,
499 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
500 SYSC_HAS_SOFTRESET),
501 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
502 SIDLE_SMART_WKUP),
503 .sysc_fields = &omap_hwmod_sysc_type2,
504};
505
506static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
507 .name = "hdmi",
508 .sysc = &omap54xx_hdmi_sysc,
509};
510
511static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
512 { .role = "sys_clk", .clk = "dss_sys_clk" },
513};
514
515static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
516 .name = "dss_hdmi",
517 .class = &omap54xx_hdmi_hwmod_class,
518 .clkdm_name = "dss_clkdm",
519 .main_clk = "dss_48mhz_clk",
520 .prcm = {
521 .omap4 = {
522 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
523 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
524 },
525 },
526 .opt_clks = dss_hdmi_opt_clks,
527 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
528 .parent_hwmod = &omap54xx_dss_hwmod,
529};
530
531
532
533
534
535
536static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
537 .rev_offs = 0x0000,
538 .sysc_offs = 0x0010,
539 .syss_offs = 0x0014,
540 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
541 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
542 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
543 .sysc_fields = &omap_hwmod_sysc_type1,
544};
545
546static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
547 .name = "rfbi",
548 .sysc = &omap54xx_rfbi_sysc,
549};
550
551
552static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
553 { .role = "ick", .clk = "l3_iclk_div" },
554};
555
556static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
557 .name = "dss_rfbi",
558 .class = &omap54xx_rfbi_hwmod_class,
559 .clkdm_name = "dss_clkdm",
560 .prcm = {
561 .omap4 = {
562 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
563 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
564 },
565 },
566 .opt_clks = dss_rfbi_opt_clks,
567 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
568 .parent_hwmod = &omap54xx_dss_hwmod,
569};
570
571
572
573
574
575
576static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
577 .rev_offs = 0x0000,
578};
579
580static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
581 .name = "emif",
582 .sysc = &omap54xx_emif_sysc,
583};
584
585
586static struct omap_hwmod omap54xx_emif1_hwmod = {
587 .name = "emif1",
588 .class = &omap54xx_emif_hwmod_class,
589 .clkdm_name = "emif_clkdm",
590 .flags = HWMOD_INIT_NO_IDLE,
591 .main_clk = "dpll_core_h11x2_ck",
592 .prcm = {
593 .omap4 = {
594 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
595 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
596 .modulemode = MODULEMODE_HWCTRL,
597 },
598 },
599};
600
601
602static struct omap_hwmod omap54xx_emif2_hwmod = {
603 .name = "emif2",
604 .class = &omap54xx_emif_hwmod_class,
605 .clkdm_name = "emif_clkdm",
606 .flags = HWMOD_INIT_NO_IDLE,
607 .main_clk = "dpll_core_h11x2_ck",
608 .prcm = {
609 .omap4 = {
610 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
611 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
612 .modulemode = MODULEMODE_HWCTRL,
613 },
614 },
615};
616
617
618
619
620
621
622static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
623 .rev_offs = 0x0000,
624 .sysc_offs = 0x0010,
625 .syss_offs = 0x0114,
626 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
627 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
628 SYSS_HAS_RESET_STATUS),
629 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
630 SIDLE_SMART_WKUP),
631 .sysc_fields = &omap_hwmod_sysc_type1,
632};
633
634static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
635 .name = "gpio",
636 .sysc = &omap54xx_gpio_sysc,
637 .rev = 2,
638};
639
640
641static struct omap_gpio_dev_attr gpio_dev_attr = {
642 .bank_width = 32,
643 .dbck_flag = true,
644};
645
646
647static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
648 { .role = "dbclk", .clk = "gpio1_dbclk" },
649};
650
651static struct omap_hwmod omap54xx_gpio1_hwmod = {
652 .name = "gpio1",
653 .class = &omap54xx_gpio_hwmod_class,
654 .clkdm_name = "wkupaon_clkdm",
655 .main_clk = "wkupaon_iclk_mux",
656 .prcm = {
657 .omap4 = {
658 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
659 .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
660 .modulemode = MODULEMODE_HWCTRL,
661 },
662 },
663 .opt_clks = gpio1_opt_clks,
664 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
665 .dev_attr = &gpio_dev_attr,
666};
667
668
669static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
670 { .role = "dbclk", .clk = "gpio2_dbclk" },
671};
672
673static struct omap_hwmod omap54xx_gpio2_hwmod = {
674 .name = "gpio2",
675 .class = &omap54xx_gpio_hwmod_class,
676 .clkdm_name = "l4per_clkdm",
677 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
678 .main_clk = "l4_root_clk_div",
679 .prcm = {
680 .omap4 = {
681 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
682 .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
683 .modulemode = MODULEMODE_HWCTRL,
684 },
685 },
686 .opt_clks = gpio2_opt_clks,
687 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
688 .dev_attr = &gpio_dev_attr,
689};
690
691
692static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
693 { .role = "dbclk", .clk = "gpio3_dbclk" },
694};
695
696static struct omap_hwmod omap54xx_gpio3_hwmod = {
697 .name = "gpio3",
698 .class = &omap54xx_gpio_hwmod_class,
699 .clkdm_name = "l4per_clkdm",
700 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
701 .main_clk = "l4_root_clk_div",
702 .prcm = {
703 .omap4 = {
704 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
705 .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
706 .modulemode = MODULEMODE_HWCTRL,
707 },
708 },
709 .opt_clks = gpio3_opt_clks,
710 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
711 .dev_attr = &gpio_dev_attr,
712};
713
714
715static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
716 { .role = "dbclk", .clk = "gpio4_dbclk" },
717};
718
719static struct omap_hwmod omap54xx_gpio4_hwmod = {
720 .name = "gpio4",
721 .class = &omap54xx_gpio_hwmod_class,
722 .clkdm_name = "l4per_clkdm",
723 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
724 .main_clk = "l4_root_clk_div",
725 .prcm = {
726 .omap4 = {
727 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
728 .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
729 .modulemode = MODULEMODE_HWCTRL,
730 },
731 },
732 .opt_clks = gpio4_opt_clks,
733 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
734 .dev_attr = &gpio_dev_attr,
735};
736
737
738static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
739 { .role = "dbclk", .clk = "gpio5_dbclk" },
740};
741
742static struct omap_hwmod omap54xx_gpio5_hwmod = {
743 .name = "gpio5",
744 .class = &omap54xx_gpio_hwmod_class,
745 .clkdm_name = "l4per_clkdm",
746 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
747 .main_clk = "l4_root_clk_div",
748 .prcm = {
749 .omap4 = {
750 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
751 .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
752 .modulemode = MODULEMODE_HWCTRL,
753 },
754 },
755 .opt_clks = gpio5_opt_clks,
756 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
757 .dev_attr = &gpio_dev_attr,
758};
759
760
761static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
762 { .role = "dbclk", .clk = "gpio6_dbclk" },
763};
764
765static struct omap_hwmod omap54xx_gpio6_hwmod = {
766 .name = "gpio6",
767 .class = &omap54xx_gpio_hwmod_class,
768 .clkdm_name = "l4per_clkdm",
769 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
770 .main_clk = "l4_root_clk_div",
771 .prcm = {
772 .omap4 = {
773 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
774 .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
775 .modulemode = MODULEMODE_HWCTRL,
776 },
777 },
778 .opt_clks = gpio6_opt_clks,
779 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
780 .dev_attr = &gpio_dev_attr,
781};
782
783
784static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
785 { .role = "dbclk", .clk = "gpio7_dbclk" },
786};
787
788static struct omap_hwmod omap54xx_gpio7_hwmod = {
789 .name = "gpio7",
790 .class = &omap54xx_gpio_hwmod_class,
791 .clkdm_name = "l4per_clkdm",
792 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
793 .main_clk = "l4_root_clk_div",
794 .prcm = {
795 .omap4 = {
796 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
797 .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
798 .modulemode = MODULEMODE_HWCTRL,
799 },
800 },
801 .opt_clks = gpio7_opt_clks,
802 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
803 .dev_attr = &gpio_dev_attr,
804};
805
806
807static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
808 { .role = "dbclk", .clk = "gpio8_dbclk" },
809};
810
811static struct omap_hwmod omap54xx_gpio8_hwmod = {
812 .name = "gpio8",
813 .class = &omap54xx_gpio_hwmod_class,
814 .clkdm_name = "l4per_clkdm",
815 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
816 .main_clk = "l4_root_clk_div",
817 .prcm = {
818 .omap4 = {
819 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
820 .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
821 .modulemode = MODULEMODE_HWCTRL,
822 },
823 },
824 .opt_clks = gpio8_opt_clks,
825 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
826 .dev_attr = &gpio_dev_attr,
827};
828
829
830
831
832
833
834static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
835 .sysc_offs = 0x0010,
836 .syss_offs = 0x0090,
837 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
838 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
839 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
840 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
841 SIDLE_SMART_WKUP),
842 .clockact = CLOCKACT_TEST_ICLK,
843 .sysc_fields = &omap_hwmod_sysc_type1,
844};
845
846static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
847 .name = "i2c",
848 .sysc = &omap54xx_i2c_sysc,
849 .reset = &omap_i2c_reset,
850 .rev = OMAP_I2C_IP_VERSION_2,
851};
852
853
854static struct omap_i2c_dev_attr i2c_dev_attr = {
855 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
856};
857
858
859static struct omap_hwmod omap54xx_i2c1_hwmod = {
860 .name = "i2c1",
861 .class = &omap54xx_i2c_hwmod_class,
862 .clkdm_name = "l4per_clkdm",
863 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
864 .main_clk = "func_96m_fclk",
865 .prcm = {
866 .omap4 = {
867 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
868 .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
869 .modulemode = MODULEMODE_SWCTRL,
870 },
871 },
872 .dev_attr = &i2c_dev_attr,
873};
874
875
876static struct omap_hwmod omap54xx_i2c2_hwmod = {
877 .name = "i2c2",
878 .class = &omap54xx_i2c_hwmod_class,
879 .clkdm_name = "l4per_clkdm",
880 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
881 .main_clk = "func_96m_fclk",
882 .prcm = {
883 .omap4 = {
884 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
885 .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
886 .modulemode = MODULEMODE_SWCTRL,
887 },
888 },
889 .dev_attr = &i2c_dev_attr,
890};
891
892
893static struct omap_hwmod omap54xx_i2c3_hwmod = {
894 .name = "i2c3",
895 .class = &omap54xx_i2c_hwmod_class,
896 .clkdm_name = "l4per_clkdm",
897 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
898 .main_clk = "func_96m_fclk",
899 .prcm = {
900 .omap4 = {
901 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
902 .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
903 .modulemode = MODULEMODE_SWCTRL,
904 },
905 },
906 .dev_attr = &i2c_dev_attr,
907};
908
909
910static struct omap_hwmod omap54xx_i2c4_hwmod = {
911 .name = "i2c4",
912 .class = &omap54xx_i2c_hwmod_class,
913 .clkdm_name = "l4per_clkdm",
914 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
915 .main_clk = "func_96m_fclk",
916 .prcm = {
917 .omap4 = {
918 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
919 .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
920 .modulemode = MODULEMODE_SWCTRL,
921 },
922 },
923 .dev_attr = &i2c_dev_attr,
924};
925
926
927static struct omap_hwmod omap54xx_i2c5_hwmod = {
928 .name = "i2c5",
929 .class = &omap54xx_i2c_hwmod_class,
930 .clkdm_name = "l4per_clkdm",
931 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
932 .main_clk = "func_96m_fclk",
933 .prcm = {
934 .omap4 = {
935 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
936 .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
937 .modulemode = MODULEMODE_SWCTRL,
938 },
939 },
940 .dev_attr = &i2c_dev_attr,
941};
942
943
944
945
946
947
948static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
949 .rev_offs = 0x0000,
950 .sysc_offs = 0x0010,
951 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
952 SYSC_HAS_SOFTRESET),
953 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
954 .sysc_fields = &omap_hwmod_sysc_type1,
955};
956
957static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
958 .name = "kbd",
959 .sysc = &omap54xx_kbd_sysc,
960};
961
962
963static struct omap_hwmod omap54xx_kbd_hwmod = {
964 .name = "kbd",
965 .class = &omap54xx_kbd_hwmod_class,
966 .clkdm_name = "wkupaon_clkdm",
967 .main_clk = "sys_32k_ck",
968 .prcm = {
969 .omap4 = {
970 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
971 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
972 .modulemode = MODULEMODE_SWCTRL,
973 },
974 },
975};
976
977
978
979
980
981
982
983static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
984 .rev_offs = 0x0000,
985 .sysc_offs = 0x0010,
986 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
987 SYSC_HAS_SOFTRESET),
988 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
989 .sysc_fields = &omap_hwmod_sysc_type2,
990};
991
992static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
993 .name = "mailbox",
994 .sysc = &omap54xx_mailbox_sysc,
995};
996
997
998static struct omap_hwmod omap54xx_mailbox_hwmod = {
999 .name = "mailbox",
1000 .class = &omap54xx_mailbox_hwmod_class,
1001 .clkdm_name = "l4cfg_clkdm",
1002 .prcm = {
1003 .omap4 = {
1004 .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1005 .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1006 },
1007 },
1008};
1009
1010
1011
1012
1013
1014
1015static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
1016 .sysc_offs = 0x008c,
1017 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1018 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1019 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1020 .sysc_fields = &omap_hwmod_sysc_type1,
1021};
1022
1023static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
1024 .name = "mcbsp",
1025 .sysc = &omap54xx_mcbsp_sysc,
1026 .rev = MCBSP_CONFIG_TYPE4,
1027};
1028
1029
1030static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1031 { .role = "pad_fck", .clk = "pad_clks_ck" },
1032 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1033};
1034
1035static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
1036 .name = "mcbsp1",
1037 .class = &omap54xx_mcbsp_hwmod_class,
1038 .clkdm_name = "abe_clkdm",
1039 .main_clk = "mcbsp1_gfclk",
1040 .prcm = {
1041 .omap4 = {
1042 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
1043 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1044 .modulemode = MODULEMODE_SWCTRL,
1045 },
1046 },
1047 .opt_clks = mcbsp1_opt_clks,
1048 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1049};
1050
1051
1052static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1053 { .role = "pad_fck", .clk = "pad_clks_ck" },
1054 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1055};
1056
1057static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
1058 .name = "mcbsp2",
1059 .class = &omap54xx_mcbsp_hwmod_class,
1060 .clkdm_name = "abe_clkdm",
1061 .main_clk = "mcbsp2_gfclk",
1062 .prcm = {
1063 .omap4 = {
1064 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
1065 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1066 .modulemode = MODULEMODE_SWCTRL,
1067 },
1068 },
1069 .opt_clks = mcbsp2_opt_clks,
1070 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
1071};
1072
1073
1074static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1075 { .role = "pad_fck", .clk = "pad_clks_ck" },
1076 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1077};
1078
1079static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
1080 .name = "mcbsp3",
1081 .class = &omap54xx_mcbsp_hwmod_class,
1082 .clkdm_name = "abe_clkdm",
1083 .main_clk = "mcbsp3_gfclk",
1084 .prcm = {
1085 .omap4 = {
1086 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
1087 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1088 .modulemode = MODULEMODE_SWCTRL,
1089 },
1090 },
1091 .opt_clks = mcbsp3_opt_clks,
1092 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
1093};
1094
1095
1096
1097
1098
1099
1100
1101static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
1102 .rev_offs = 0x0000,
1103 .sysc_offs = 0x0010,
1104 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1105 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1106 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1107 SIDLE_SMART_WKUP),
1108 .sysc_fields = &omap_hwmod_sysc_type2,
1109};
1110
1111static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
1112 .name = "mcpdm",
1113 .sysc = &omap54xx_mcpdm_sysc,
1114};
1115
1116
1117static struct omap_hwmod omap54xx_mcpdm_hwmod = {
1118 .name = "mcpdm",
1119 .class = &omap54xx_mcpdm_hwmod_class,
1120 .clkdm_name = "abe_clkdm",
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1134 .main_clk = "pad_clks_ck",
1135 .prcm = {
1136 .omap4 = {
1137 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
1138 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
1139 .modulemode = MODULEMODE_SWCTRL,
1140 },
1141 },
1142};
1143
1144
1145
1146
1147
1148
1149
1150static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
1151 .rev_offs = 0x0000,
1152 .sysc_offs = 0x0010,
1153 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1154 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1155 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1156 SIDLE_SMART_WKUP),
1157 .sysc_fields = &omap_hwmod_sysc_type2,
1158};
1159
1160static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
1161 .name = "mcspi",
1162 .sysc = &omap54xx_mcspi_sysc,
1163 .rev = OMAP4_MCSPI_REV,
1164};
1165
1166
1167
1168static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1169 .num_chipselect = 4,
1170};
1171
1172static struct omap_hwmod omap54xx_mcspi1_hwmod = {
1173 .name = "mcspi1",
1174 .class = &omap54xx_mcspi_hwmod_class,
1175 .clkdm_name = "l4per_clkdm",
1176 .main_clk = "func_48m_fclk",
1177 .prcm = {
1178 .omap4 = {
1179 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1180 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1181 .modulemode = MODULEMODE_SWCTRL,
1182 },
1183 },
1184 .dev_attr = &mcspi1_dev_attr,
1185};
1186
1187
1188
1189static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1190 .num_chipselect = 2,
1191};
1192
1193static struct omap_hwmod omap54xx_mcspi2_hwmod = {
1194 .name = "mcspi2",
1195 .class = &omap54xx_mcspi_hwmod_class,
1196 .clkdm_name = "l4per_clkdm",
1197 .main_clk = "func_48m_fclk",
1198 .prcm = {
1199 .omap4 = {
1200 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1201 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1202 .modulemode = MODULEMODE_SWCTRL,
1203 },
1204 },
1205 .dev_attr = &mcspi2_dev_attr,
1206};
1207
1208
1209
1210static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1211 .num_chipselect = 2,
1212};
1213
1214static struct omap_hwmod omap54xx_mcspi3_hwmod = {
1215 .name = "mcspi3",
1216 .class = &omap54xx_mcspi_hwmod_class,
1217 .clkdm_name = "l4per_clkdm",
1218 .main_clk = "func_48m_fclk",
1219 .prcm = {
1220 .omap4 = {
1221 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1222 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1223 .modulemode = MODULEMODE_SWCTRL,
1224 },
1225 },
1226 .dev_attr = &mcspi3_dev_attr,
1227};
1228
1229
1230
1231static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1232 .num_chipselect = 1,
1233};
1234
1235static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1236 .name = "mcspi4",
1237 .class = &omap54xx_mcspi_hwmod_class,
1238 .clkdm_name = "l4per_clkdm",
1239 .main_clk = "func_48m_fclk",
1240 .prcm = {
1241 .omap4 = {
1242 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1243 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1244 .modulemode = MODULEMODE_SWCTRL,
1245 },
1246 },
1247 .dev_attr = &mcspi4_dev_attr,
1248};
1249
1250
1251
1252
1253
1254
1255static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1256 .rev_offs = 0x0000,
1257 .sysc_offs = 0x0010,
1258 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1259 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1260 SYSC_HAS_SOFTRESET),
1261 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1262 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1263 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1264 .sysc_fields = &omap_hwmod_sysc_type2,
1265};
1266
1267static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1268 .name = "mmc",
1269 .sysc = &omap54xx_mmc_sysc,
1270};
1271
1272
1273static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1274 { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1275};
1276
1277
1278static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1279 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1280};
1281
1282static struct omap_hwmod omap54xx_mmc1_hwmod = {
1283 .name = "mmc1",
1284 .class = &omap54xx_mmc_hwmod_class,
1285 .clkdm_name = "l3init_clkdm",
1286 .main_clk = "mmc1_fclk",
1287 .prcm = {
1288 .omap4 = {
1289 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1290 .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1291 .modulemode = MODULEMODE_SWCTRL,
1292 },
1293 },
1294 .opt_clks = mmc1_opt_clks,
1295 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1296 .dev_attr = &mmc1_dev_attr,
1297};
1298
1299
1300static struct omap_hwmod omap54xx_mmc2_hwmod = {
1301 .name = "mmc2",
1302 .class = &omap54xx_mmc_hwmod_class,
1303 .clkdm_name = "l3init_clkdm",
1304 .main_clk = "mmc2_fclk",
1305 .prcm = {
1306 .omap4 = {
1307 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1308 .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1309 .modulemode = MODULEMODE_SWCTRL,
1310 },
1311 },
1312};
1313
1314
1315static struct omap_hwmod omap54xx_mmc3_hwmod = {
1316 .name = "mmc3",
1317 .class = &omap54xx_mmc_hwmod_class,
1318 .clkdm_name = "l4per_clkdm",
1319 .main_clk = "func_48m_fclk",
1320 .prcm = {
1321 .omap4 = {
1322 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1323 .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1324 .modulemode = MODULEMODE_SWCTRL,
1325 },
1326 },
1327};
1328
1329
1330static struct omap_hwmod omap54xx_mmc4_hwmod = {
1331 .name = "mmc4",
1332 .class = &omap54xx_mmc_hwmod_class,
1333 .clkdm_name = "l4per_clkdm",
1334 .main_clk = "func_48m_fclk",
1335 .prcm = {
1336 .omap4 = {
1337 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1338 .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1339 .modulemode = MODULEMODE_SWCTRL,
1340 },
1341 },
1342};
1343
1344
1345static struct omap_hwmod omap54xx_mmc5_hwmod = {
1346 .name = "mmc5",
1347 .class = &omap54xx_mmc_hwmod_class,
1348 .clkdm_name = "l4per_clkdm",
1349 .main_clk = "func_96m_fclk",
1350 .prcm = {
1351 .omap4 = {
1352 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1353 .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1354 .modulemode = MODULEMODE_SWCTRL,
1355 },
1356 },
1357};
1358
1359
1360
1361
1362
1363
1364
1365static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
1366 .rev_offs = 0x0000,
1367 .sysc_offs = 0x0010,
1368 .syss_offs = 0x0014,
1369 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1370 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1371 SYSS_HAS_RESET_STATUS),
1372 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1373 .sysc_fields = &omap_hwmod_sysc_type1,
1374};
1375
1376static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
1377 .name = "mmu",
1378 .sysc = &omap54xx_mmu_sysc,
1379};
1380
1381static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
1382 { .name = "mmu_cache", .rst_shift = 1 },
1383};
1384
1385static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
1386 .name = "mmu_dsp",
1387 .class = &omap54xx_mmu_hwmod_class,
1388 .clkdm_name = "dsp_clkdm",
1389 .rst_lines = omap54xx_mmu_dsp_resets,
1390 .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
1391 .main_clk = "dpll_iva_h11x2_ck",
1392 .prcm = {
1393 .omap4 = {
1394 .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
1395 .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
1396 .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
1397 .modulemode = MODULEMODE_HWCTRL,
1398 },
1399 },
1400};
1401
1402
1403static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
1404 { .name = "mmu_cache", .rst_shift = 2 },
1405};
1406
1407static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
1408 .name = "mmu_ipu",
1409 .class = &omap54xx_mmu_hwmod_class,
1410 .clkdm_name = "ipu_clkdm",
1411 .rst_lines = omap54xx_mmu_ipu_resets,
1412 .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
1413 .main_clk = "dpll_core_h22x2_ck",
1414 .prcm = {
1415 .omap4 = {
1416 .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1417 .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1418 .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1419 .modulemode = MODULEMODE_HWCTRL,
1420 },
1421 },
1422};
1423
1424
1425
1426
1427
1428
1429static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1430 .name = "mpu",
1431};
1432
1433
1434static struct omap_hwmod omap54xx_mpu_hwmod = {
1435 .name = "mpu",
1436 .class = &omap54xx_mpu_hwmod_class,
1437 .clkdm_name = "mpu_clkdm",
1438 .flags = HWMOD_INIT_NO_IDLE,
1439 .main_clk = "dpll_mpu_m2_ck",
1440 .prcm = {
1441 .omap4 = {
1442 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1443 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1444 },
1445 },
1446};
1447
1448
1449
1450
1451
1452
1453
1454static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
1455 .rev_offs = 0x0000,
1456 .sysc_offs = 0x0010,
1457 .syss_offs = 0x0014,
1458 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1459 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1460 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1461 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1462 .sysc_fields = &omap_hwmod_sysc_type1,
1463};
1464
1465static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
1466 .name = "spinlock",
1467 .sysc = &omap54xx_spinlock_sysc,
1468};
1469
1470
1471static struct omap_hwmod omap54xx_spinlock_hwmod = {
1472 .name = "spinlock",
1473 .class = &omap54xx_spinlock_hwmod_class,
1474 .clkdm_name = "l4cfg_clkdm",
1475 .prcm = {
1476 .omap4 = {
1477 .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1478 .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1479 },
1480 },
1481};
1482
1483
1484
1485
1486
1487
1488
1489static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
1490 .rev_offs = 0x0000,
1491 .sysc_offs = 0x0010,
1492 .syss_offs = 0x0014,
1493 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1494 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1495 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1496 .sysc_fields = &omap_hwmod_sysc_type1,
1497};
1498
1499static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
1500 .name = "ocp2scp",
1501 .sysc = &omap54xx_ocp2scp_sysc,
1502};
1503
1504
1505static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
1506 .name = "ocp2scp1",
1507 .class = &omap54xx_ocp2scp_hwmod_class,
1508 .clkdm_name = "l3init_clkdm",
1509 .main_clk = "l4_root_clk_div",
1510 .prcm = {
1511 .omap4 = {
1512 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1513 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1514 .modulemode = MODULEMODE_HWCTRL,
1515 },
1516 },
1517};
1518
1519
1520
1521
1522
1523
1524
1525static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1526 .rev_offs = 0x0000,
1527 .sysc_offs = 0x0010,
1528 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1529 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1530 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1531 SIDLE_SMART_WKUP),
1532 .sysc_fields = &omap_hwmod_sysc_type2,
1533 .clockact = CLOCKACT_TEST_ICLK,
1534};
1535
1536static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1537 .name = "timer",
1538 .sysc = &omap54xx_timer_1ms_sysc,
1539};
1540
1541static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1542 .rev_offs = 0x0000,
1543 .sysc_offs = 0x0010,
1544 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1545 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1546 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1547 SIDLE_SMART_WKUP),
1548 .sysc_fields = &omap_hwmod_sysc_type2,
1549};
1550
1551static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1552 .name = "timer",
1553 .sysc = &omap54xx_timer_sysc,
1554};
1555
1556
1557static struct omap_hwmod omap54xx_timer1_hwmod = {
1558 .name = "timer1",
1559 .class = &omap54xx_timer_1ms_hwmod_class,
1560 .clkdm_name = "wkupaon_clkdm",
1561 .main_clk = "timer1_gfclk_mux",
1562 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1563 .prcm = {
1564 .omap4 = {
1565 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1566 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1567 .modulemode = MODULEMODE_SWCTRL,
1568 },
1569 },
1570};
1571
1572
1573static struct omap_hwmod omap54xx_timer2_hwmod = {
1574 .name = "timer2",
1575 .class = &omap54xx_timer_1ms_hwmod_class,
1576 .clkdm_name = "l4per_clkdm",
1577 .main_clk = "timer2_gfclk_mux",
1578 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1579 .prcm = {
1580 .omap4 = {
1581 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1582 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1583 .modulemode = MODULEMODE_SWCTRL,
1584 },
1585 },
1586};
1587
1588
1589static struct omap_hwmod omap54xx_timer3_hwmod = {
1590 .name = "timer3",
1591 .class = &omap54xx_timer_hwmod_class,
1592 .clkdm_name = "l4per_clkdm",
1593 .main_clk = "timer3_gfclk_mux",
1594 .prcm = {
1595 .omap4 = {
1596 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1597 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1598 .modulemode = MODULEMODE_SWCTRL,
1599 },
1600 },
1601};
1602
1603
1604static struct omap_hwmod omap54xx_timer4_hwmod = {
1605 .name = "timer4",
1606 .class = &omap54xx_timer_hwmod_class,
1607 .clkdm_name = "l4per_clkdm",
1608 .main_clk = "timer4_gfclk_mux",
1609 .prcm = {
1610 .omap4 = {
1611 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1612 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1613 .modulemode = MODULEMODE_SWCTRL,
1614 },
1615 },
1616};
1617
1618
1619static struct omap_hwmod omap54xx_timer5_hwmod = {
1620 .name = "timer5",
1621 .class = &omap54xx_timer_hwmod_class,
1622 .clkdm_name = "abe_clkdm",
1623 .main_clk = "timer5_gfclk_mux",
1624 .prcm = {
1625 .omap4 = {
1626 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1627 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1628 .modulemode = MODULEMODE_SWCTRL,
1629 },
1630 },
1631};
1632
1633
1634static struct omap_hwmod omap54xx_timer6_hwmod = {
1635 .name = "timer6",
1636 .class = &omap54xx_timer_hwmod_class,
1637 .clkdm_name = "abe_clkdm",
1638 .main_clk = "timer6_gfclk_mux",
1639 .prcm = {
1640 .omap4 = {
1641 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1642 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1643 .modulemode = MODULEMODE_SWCTRL,
1644 },
1645 },
1646};
1647
1648
1649static struct omap_hwmod omap54xx_timer7_hwmod = {
1650 .name = "timer7",
1651 .class = &omap54xx_timer_hwmod_class,
1652 .clkdm_name = "abe_clkdm",
1653 .main_clk = "timer7_gfclk_mux",
1654 .prcm = {
1655 .omap4 = {
1656 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1657 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1658 .modulemode = MODULEMODE_SWCTRL,
1659 },
1660 },
1661};
1662
1663
1664static struct omap_hwmod omap54xx_timer8_hwmod = {
1665 .name = "timer8",
1666 .class = &omap54xx_timer_hwmod_class,
1667 .clkdm_name = "abe_clkdm",
1668 .main_clk = "timer8_gfclk_mux",
1669 .prcm = {
1670 .omap4 = {
1671 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1672 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1673 .modulemode = MODULEMODE_SWCTRL,
1674 },
1675 },
1676};
1677
1678
1679static struct omap_hwmod omap54xx_timer9_hwmod = {
1680 .name = "timer9",
1681 .class = &omap54xx_timer_hwmod_class,
1682 .clkdm_name = "l4per_clkdm",
1683 .main_clk = "timer9_gfclk_mux",
1684 .prcm = {
1685 .omap4 = {
1686 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1687 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1688 .modulemode = MODULEMODE_SWCTRL,
1689 },
1690 },
1691};
1692
1693
1694static struct omap_hwmod omap54xx_timer10_hwmod = {
1695 .name = "timer10",
1696 .class = &omap54xx_timer_1ms_hwmod_class,
1697 .clkdm_name = "l4per_clkdm",
1698 .main_clk = "timer10_gfclk_mux",
1699 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1700 .prcm = {
1701 .omap4 = {
1702 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1703 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1704 .modulemode = MODULEMODE_SWCTRL,
1705 },
1706 },
1707};
1708
1709
1710static struct omap_hwmod omap54xx_timer11_hwmod = {
1711 .name = "timer11",
1712 .class = &omap54xx_timer_hwmod_class,
1713 .clkdm_name = "l4per_clkdm",
1714 .main_clk = "timer11_gfclk_mux",
1715 .prcm = {
1716 .omap4 = {
1717 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1718 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1719 .modulemode = MODULEMODE_SWCTRL,
1720 },
1721 },
1722};
1723
1724
1725
1726
1727
1728
1729static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1730 .rev_offs = 0x0050,
1731 .sysc_offs = 0x0054,
1732 .syss_offs = 0x0058,
1733 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1734 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1735 SYSS_HAS_RESET_STATUS),
1736 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1737 SIDLE_SMART_WKUP),
1738 .sysc_fields = &omap_hwmod_sysc_type1,
1739};
1740
1741static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1742 .name = "uart",
1743 .sysc = &omap54xx_uart_sysc,
1744};
1745
1746
1747static struct omap_hwmod omap54xx_uart1_hwmod = {
1748 .name = "uart1",
1749 .class = &omap54xx_uart_hwmod_class,
1750 .clkdm_name = "l4per_clkdm",
1751 .main_clk = "func_48m_fclk",
1752 .prcm = {
1753 .omap4 = {
1754 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1755 .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1756 .modulemode = MODULEMODE_SWCTRL,
1757 },
1758 },
1759};
1760
1761
1762static struct omap_hwmod omap54xx_uart2_hwmod = {
1763 .name = "uart2",
1764 .class = &omap54xx_uart_hwmod_class,
1765 .clkdm_name = "l4per_clkdm",
1766 .main_clk = "func_48m_fclk",
1767 .prcm = {
1768 .omap4 = {
1769 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1770 .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1771 .modulemode = MODULEMODE_SWCTRL,
1772 },
1773 },
1774};
1775
1776
1777static struct omap_hwmod omap54xx_uart3_hwmod = {
1778 .name = "uart3",
1779 .class = &omap54xx_uart_hwmod_class,
1780 .clkdm_name = "l4per_clkdm",
1781 .flags = DEBUG_OMAP4UART3_FLAGS,
1782 .main_clk = "func_48m_fclk",
1783 .prcm = {
1784 .omap4 = {
1785 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1786 .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1787 .modulemode = MODULEMODE_SWCTRL,
1788 },
1789 },
1790};
1791
1792
1793static struct omap_hwmod omap54xx_uart4_hwmod = {
1794 .name = "uart4",
1795 .class = &omap54xx_uart_hwmod_class,
1796 .clkdm_name = "l4per_clkdm",
1797 .flags = DEBUG_OMAP4UART4_FLAGS,
1798 .main_clk = "func_48m_fclk",
1799 .prcm = {
1800 .omap4 = {
1801 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1802 .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1803 .modulemode = MODULEMODE_SWCTRL,
1804 },
1805 },
1806};
1807
1808
1809static struct omap_hwmod omap54xx_uart5_hwmod = {
1810 .name = "uart5",
1811 .class = &omap54xx_uart_hwmod_class,
1812 .clkdm_name = "l4per_clkdm",
1813 .main_clk = "func_48m_fclk",
1814 .prcm = {
1815 .omap4 = {
1816 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1817 .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1818 .modulemode = MODULEMODE_SWCTRL,
1819 },
1820 },
1821};
1822
1823
1824static struct omap_hwmod omap54xx_uart6_hwmod = {
1825 .name = "uart6",
1826 .class = &omap54xx_uart_hwmod_class,
1827 .clkdm_name = "l4per_clkdm",
1828 .main_clk = "func_48m_fclk",
1829 .prcm = {
1830 .omap4 = {
1831 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1832 .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1833 .modulemode = MODULEMODE_SWCTRL,
1834 },
1835 },
1836};
1837
1838
1839
1840
1841
1842
1843static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1844 .rev_offs = 0x0000,
1845 .sysc_offs = 0x0010,
1846 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1847 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1848 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1849 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1850 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1851 .sysc_fields = &omap_hwmod_sysc_type2,
1852};
1853
1854static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1855 .name = "usb_host_hs",
1856 .sysc = &omap54xx_usb_host_hs_sysc,
1857};
1858
1859static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1860 .name = "usb_host_hs",
1861 .class = &omap54xx_usb_host_hs_hwmod_class,
1862 .clkdm_name = "l3init_clkdm",
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1902 .main_clk = "l3init_60m_fclk",
1903 .prcm = {
1904 .omap4 = {
1905 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1906 .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1907 .modulemode = MODULEMODE_SWCTRL,
1908 },
1909 },
1910};
1911
1912
1913
1914
1915
1916
1917static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1918 .rev_offs = 0x0000,
1919 .sysc_offs = 0x0010,
1920 .syss_offs = 0x0014,
1921 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1922 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1923 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1924 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1925 .sysc_fields = &omap_hwmod_sysc_type1,
1926};
1927
1928static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1929 .name = "usb_tll_hs",
1930 .sysc = &omap54xx_usb_tll_hs_sysc,
1931};
1932
1933static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1934 .name = "usb_tll_hs",
1935 .class = &omap54xx_usb_tll_hs_hwmod_class,
1936 .clkdm_name = "l3init_clkdm",
1937 .main_clk = "l4_root_clk_div",
1938 .prcm = {
1939 .omap4 = {
1940 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1941 .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1942 .modulemode = MODULEMODE_HWCTRL,
1943 },
1944 },
1945};
1946
1947
1948
1949
1950
1951
1952static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1953 .rev_offs = 0x0000,
1954 .sysc_offs = 0x0010,
1955 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1956 SYSC_HAS_SIDLEMODE),
1957 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1958 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1959 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1960 .sysc_fields = &omap_hwmod_sysc_type2,
1961};
1962
1963static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1964 .name = "usb_otg_ss",
1965 .sysc = &omap54xx_usb_otg_ss_sysc,
1966};
1967
1968
1969static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1970 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1971};
1972
1973static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1974 .name = "usb_otg_ss",
1975 .class = &omap54xx_usb_otg_ss_hwmod_class,
1976 .clkdm_name = "l3init_clkdm",
1977 .flags = HWMOD_SWSUP_SIDLE,
1978 .main_clk = "dpll_core_h13x2_ck",
1979 .prcm = {
1980 .omap4 = {
1981 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1982 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1983 .modulemode = MODULEMODE_HWCTRL,
1984 },
1985 },
1986 .opt_clks = usb_otg_ss_opt_clks,
1987 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
1988};
1989
1990
1991
1992
1993
1994
1995
1996static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1997 .rev_offs = 0x0000,
1998 .sysc_offs = 0x0010,
1999 .syss_offs = 0x0014,
2000 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2001 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2002 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2003 SIDLE_SMART_WKUP),
2004 .sysc_fields = &omap_hwmod_sysc_type1,
2005};
2006
2007static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
2008 .name = "wd_timer",
2009 .sysc = &omap54xx_wd_timer_sysc,
2010 .pre_shutdown = &omap2_wd_timer_disable,
2011};
2012
2013
2014static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
2015 .name = "wd_timer2",
2016 .class = &omap54xx_wd_timer_hwmod_class,
2017 .clkdm_name = "wkupaon_clkdm",
2018 .main_clk = "sys_32k_ck",
2019 .prcm = {
2020 .omap4 = {
2021 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2022 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2023 .modulemode = MODULEMODE_SWCTRL,
2024 },
2025 },
2026};
2027
2028
2029
2030
2031
2032
2033
2034static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
2035
2036static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
2037 .master = &omap54xx_l4_cfg_hwmod,
2038 .slave = &omap54xx_ocp2scp3_hwmod,
2039 .clk = "l4_root_clk_div",
2040 .user = OCP_USER_MPU | OCP_USER_SDMA,
2041};
2042
2043static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
2044 .name = "ocp2scp3",
2045 .class = &omap54xx_ocp2scp_hwmod_class,
2046 .clkdm_name = "l3init_clkdm",
2047 .prcm = {
2048 .omap4 = {
2049 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2050 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2051 .modulemode = MODULEMODE_HWCTRL,
2052 },
2053 },
2054};
2055
2056
2057
2058
2059
2060
2061static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2062 .sysc_offs = 0x0000,
2063 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2064 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2065 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2066 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2067 .sysc_fields = &omap_hwmod_sysc_type2,
2068};
2069
2070static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2071 .name = "sata",
2072 .sysc = &omap54xx_sata_sysc,
2073};
2074
2075
2076static struct omap_hwmod omap54xx_sata_hwmod = {
2077 .name = "sata",
2078 .class = &omap54xx_sata_hwmod_class,
2079 .clkdm_name = "l3init_clkdm",
2080 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2081 .main_clk = "func_48m_fclk",
2082 .mpu_rt_idx = 1,
2083 .prcm = {
2084 .omap4 = {
2085 .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2086 .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2087 .modulemode = MODULEMODE_SWCTRL,
2088 },
2089 },
2090};
2091
2092
2093static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
2094 .master = &omap54xx_l4_cfg_hwmod,
2095 .slave = &omap54xx_sata_hwmod,
2096 .clk = "l3_iclk_div",
2097 .user = OCP_USER_MPU | OCP_USER_SDMA,
2098};
2099
2100
2101
2102
2103
2104
2105static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
2106 .master = &omap54xx_l3_main_1_hwmod,
2107 .slave = &omap54xx_dmm_hwmod,
2108 .clk = "l3_iclk_div",
2109 .user = OCP_USER_SDMA,
2110};
2111
2112
2113static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
2114 .master = &omap54xx_l3_main_3_hwmod,
2115 .slave = &omap54xx_l3_instr_hwmod,
2116 .clk = "l3_iclk_div",
2117 .user = OCP_USER_MPU | OCP_USER_SDMA,
2118};
2119
2120
2121static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
2122 .master = &omap54xx_l3_main_2_hwmod,
2123 .slave = &omap54xx_l3_main_1_hwmod,
2124 .clk = "l3_iclk_div",
2125 .user = OCP_USER_MPU | OCP_USER_SDMA,
2126};
2127
2128
2129static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
2130 .master = &omap54xx_l4_cfg_hwmod,
2131 .slave = &omap54xx_l3_main_1_hwmod,
2132 .clk = "l3_iclk_div",
2133 .user = OCP_USER_MPU | OCP_USER_SDMA,
2134};
2135
2136
2137static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
2138 .master = &omap54xx_l4_cfg_hwmod,
2139 .slave = &omap54xx_mmu_dsp_hwmod,
2140 .clk = "l4_root_clk_div",
2141 .user = OCP_USER_MPU | OCP_USER_SDMA,
2142};
2143
2144
2145static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
2146 .master = &omap54xx_mpu_hwmod,
2147 .slave = &omap54xx_l3_main_1_hwmod,
2148 .clk = "l3_iclk_div",
2149 .user = OCP_USER_MPU,
2150};
2151
2152
2153static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
2154 .master = &omap54xx_l3_main_1_hwmod,
2155 .slave = &omap54xx_l3_main_2_hwmod,
2156 .clk = "l3_iclk_div",
2157 .user = OCP_USER_MPU,
2158};
2159
2160
2161static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
2162 .master = &omap54xx_l4_cfg_hwmod,
2163 .slave = &omap54xx_l3_main_2_hwmod,
2164 .clk = "l3_iclk_div",
2165 .user = OCP_USER_MPU | OCP_USER_SDMA,
2166};
2167
2168
2169static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
2170 .master = &omap54xx_l3_main_2_hwmod,
2171 .slave = &omap54xx_mmu_ipu_hwmod,
2172 .clk = "l3_iclk_div",
2173 .user = OCP_USER_MPU | OCP_USER_SDMA,
2174};
2175
2176
2177static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
2178 .master = &omap54xx_l3_main_1_hwmod,
2179 .slave = &omap54xx_l3_main_3_hwmod,
2180 .clk = "l3_iclk_div",
2181 .user = OCP_USER_MPU,
2182};
2183
2184
2185static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
2186 .master = &omap54xx_l3_main_2_hwmod,
2187 .slave = &omap54xx_l3_main_3_hwmod,
2188 .clk = "l3_iclk_div",
2189 .user = OCP_USER_MPU | OCP_USER_SDMA,
2190};
2191
2192
2193static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
2194 .master = &omap54xx_l4_cfg_hwmod,
2195 .slave = &omap54xx_l3_main_3_hwmod,
2196 .clk = "l3_iclk_div",
2197 .user = OCP_USER_MPU | OCP_USER_SDMA,
2198};
2199
2200
2201static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
2202 .master = &omap54xx_l3_main_1_hwmod,
2203 .slave = &omap54xx_l4_abe_hwmod,
2204 .clk = "abe_iclk",
2205 .user = OCP_USER_MPU | OCP_USER_SDMA,
2206};
2207
2208
2209static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
2210 .master = &omap54xx_mpu_hwmod,
2211 .slave = &omap54xx_l4_abe_hwmod,
2212 .clk = "abe_iclk",
2213 .user = OCP_USER_MPU | OCP_USER_SDMA,
2214};
2215
2216
2217static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
2218 .master = &omap54xx_l3_main_1_hwmod,
2219 .slave = &omap54xx_l4_cfg_hwmod,
2220 .clk = "l4_root_clk_div",
2221 .user = OCP_USER_MPU | OCP_USER_SDMA,
2222};
2223
2224
2225static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
2226 .master = &omap54xx_l3_main_2_hwmod,
2227 .slave = &omap54xx_l4_per_hwmod,
2228 .clk = "l4_root_clk_div",
2229 .user = OCP_USER_MPU | OCP_USER_SDMA,
2230};
2231
2232
2233static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
2234 .master = &omap54xx_l3_main_1_hwmod,
2235 .slave = &omap54xx_l4_wkup_hwmod,
2236 .clk = "wkupaon_iclk_mux",
2237 .user = OCP_USER_MPU | OCP_USER_SDMA,
2238};
2239
2240
2241static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
2242 .master = &omap54xx_mpu_hwmod,
2243 .slave = &omap54xx_mpu_private_hwmod,
2244 .clk = "l3_iclk_div",
2245 .user = OCP_USER_MPU | OCP_USER_SDMA,
2246};
2247
2248
2249static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
2250 .master = &omap54xx_l4_wkup_hwmod,
2251 .slave = &omap54xx_counter_32k_hwmod,
2252 .clk = "wkupaon_iclk_mux",
2253 .user = OCP_USER_MPU | OCP_USER_SDMA,
2254};
2255
2256static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
2257 {
2258 .pa_start = 0x4a056000,
2259 .pa_end = 0x4a056fff,
2260 .flags = ADDR_TYPE_RT
2261 },
2262 { }
2263};
2264
2265
2266static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
2267 .master = &omap54xx_l4_cfg_hwmod,
2268 .slave = &omap54xx_dma_system_hwmod,
2269 .clk = "l4_root_clk_div",
2270 .addr = omap54xx_dma_system_addrs,
2271 .user = OCP_USER_MPU | OCP_USER_SDMA,
2272};
2273
2274
2275static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
2276 .master = &omap54xx_l4_abe_hwmod,
2277 .slave = &omap54xx_dmic_hwmod,
2278 .clk = "abe_iclk",
2279 .user = OCP_USER_MPU,
2280};
2281
2282
2283static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
2284 .master = &omap54xx_l3_main_2_hwmod,
2285 .slave = &omap54xx_dss_hwmod,
2286 .clk = "l3_iclk_div",
2287 .user = OCP_USER_MPU | OCP_USER_SDMA,
2288};
2289
2290
2291static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
2292 .master = &omap54xx_l3_main_2_hwmod,
2293 .slave = &omap54xx_dss_dispc_hwmod,
2294 .clk = "l3_iclk_div",
2295 .user = OCP_USER_MPU | OCP_USER_SDMA,
2296};
2297
2298
2299static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
2300 .master = &omap54xx_l3_main_2_hwmod,
2301 .slave = &omap54xx_dss_dsi1_a_hwmod,
2302 .clk = "l3_iclk_div",
2303 .user = OCP_USER_MPU | OCP_USER_SDMA,
2304};
2305
2306
2307static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
2308 .master = &omap54xx_l3_main_2_hwmod,
2309 .slave = &omap54xx_dss_dsi1_c_hwmod,
2310 .clk = "l3_iclk_div",
2311 .user = OCP_USER_MPU | OCP_USER_SDMA,
2312};
2313
2314
2315static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
2316 .master = &omap54xx_l3_main_2_hwmod,
2317 .slave = &omap54xx_dss_hdmi_hwmod,
2318 .clk = "l3_iclk_div",
2319 .user = OCP_USER_MPU | OCP_USER_SDMA,
2320};
2321
2322
2323static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
2324 .master = &omap54xx_l3_main_2_hwmod,
2325 .slave = &omap54xx_dss_rfbi_hwmod,
2326 .clk = "l3_iclk_div",
2327 .user = OCP_USER_MPU | OCP_USER_SDMA,
2328};
2329
2330
2331static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
2332 .master = &omap54xx_mpu_hwmod,
2333 .slave = &omap54xx_emif1_hwmod,
2334 .clk = "dpll_core_h11x2_ck",
2335 .user = OCP_USER_MPU | OCP_USER_SDMA,
2336};
2337
2338
2339static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
2340 .master = &omap54xx_mpu_hwmod,
2341 .slave = &omap54xx_emif2_hwmod,
2342 .clk = "dpll_core_h11x2_ck",
2343 .user = OCP_USER_MPU | OCP_USER_SDMA,
2344};
2345
2346
2347static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
2348 .master = &omap54xx_l4_wkup_hwmod,
2349 .slave = &omap54xx_gpio1_hwmod,
2350 .clk = "wkupaon_iclk_mux",
2351 .user = OCP_USER_MPU | OCP_USER_SDMA,
2352};
2353
2354
2355static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
2356 .master = &omap54xx_l4_per_hwmod,
2357 .slave = &omap54xx_gpio2_hwmod,
2358 .clk = "l4_root_clk_div",
2359 .user = OCP_USER_MPU | OCP_USER_SDMA,
2360};
2361
2362
2363static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
2364 .master = &omap54xx_l4_per_hwmod,
2365 .slave = &omap54xx_gpio3_hwmod,
2366 .clk = "l4_root_clk_div",
2367 .user = OCP_USER_MPU | OCP_USER_SDMA,
2368};
2369
2370
2371static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
2372 .master = &omap54xx_l4_per_hwmod,
2373 .slave = &omap54xx_gpio4_hwmod,
2374 .clk = "l4_root_clk_div",
2375 .user = OCP_USER_MPU | OCP_USER_SDMA,
2376};
2377
2378
2379static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
2380 .master = &omap54xx_l4_per_hwmod,
2381 .slave = &omap54xx_gpio5_hwmod,
2382 .clk = "l4_root_clk_div",
2383 .user = OCP_USER_MPU | OCP_USER_SDMA,
2384};
2385
2386
2387static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
2388 .master = &omap54xx_l4_per_hwmod,
2389 .slave = &omap54xx_gpio6_hwmod,
2390 .clk = "l4_root_clk_div",
2391 .user = OCP_USER_MPU | OCP_USER_SDMA,
2392};
2393
2394
2395static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
2396 .master = &omap54xx_l4_per_hwmod,
2397 .slave = &omap54xx_gpio7_hwmod,
2398 .clk = "l4_root_clk_div",
2399 .user = OCP_USER_MPU | OCP_USER_SDMA,
2400};
2401
2402
2403static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
2404 .master = &omap54xx_l4_per_hwmod,
2405 .slave = &omap54xx_gpio8_hwmod,
2406 .clk = "l4_root_clk_div",
2407 .user = OCP_USER_MPU | OCP_USER_SDMA,
2408};
2409
2410
2411static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
2412 .master = &omap54xx_l4_per_hwmod,
2413 .slave = &omap54xx_i2c1_hwmod,
2414 .clk = "l4_root_clk_div",
2415 .user = OCP_USER_MPU | OCP_USER_SDMA,
2416};
2417
2418
2419static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
2420 .master = &omap54xx_l4_per_hwmod,
2421 .slave = &omap54xx_i2c2_hwmod,
2422 .clk = "l4_root_clk_div",
2423 .user = OCP_USER_MPU | OCP_USER_SDMA,
2424};
2425
2426
2427static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
2428 .master = &omap54xx_l4_per_hwmod,
2429 .slave = &omap54xx_i2c3_hwmod,
2430 .clk = "l4_root_clk_div",
2431 .user = OCP_USER_MPU | OCP_USER_SDMA,
2432};
2433
2434
2435static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
2436 .master = &omap54xx_l4_per_hwmod,
2437 .slave = &omap54xx_i2c4_hwmod,
2438 .clk = "l4_root_clk_div",
2439 .user = OCP_USER_MPU | OCP_USER_SDMA,
2440};
2441
2442
2443static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
2444 .master = &omap54xx_l4_per_hwmod,
2445 .slave = &omap54xx_i2c5_hwmod,
2446 .clk = "l4_root_clk_div",
2447 .user = OCP_USER_MPU | OCP_USER_SDMA,
2448};
2449
2450
2451static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
2452 .master = &omap54xx_l4_wkup_hwmod,
2453 .slave = &omap54xx_kbd_hwmod,
2454 .clk = "wkupaon_iclk_mux",
2455 .user = OCP_USER_MPU | OCP_USER_SDMA,
2456};
2457
2458
2459static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
2460 .master = &omap54xx_l4_cfg_hwmod,
2461 .slave = &omap54xx_mailbox_hwmod,
2462 .clk = "l4_root_clk_div",
2463 .user = OCP_USER_MPU | OCP_USER_SDMA,
2464};
2465
2466
2467static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
2468 .master = &omap54xx_l4_abe_hwmod,
2469 .slave = &omap54xx_mcbsp1_hwmod,
2470 .clk = "abe_iclk",
2471 .user = OCP_USER_MPU,
2472};
2473
2474
2475static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
2476 .master = &omap54xx_l4_abe_hwmod,
2477 .slave = &omap54xx_mcbsp2_hwmod,
2478 .clk = "abe_iclk",
2479 .user = OCP_USER_MPU,
2480};
2481
2482
2483static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
2484 .master = &omap54xx_l4_abe_hwmod,
2485 .slave = &omap54xx_mcbsp3_hwmod,
2486 .clk = "abe_iclk",
2487 .user = OCP_USER_MPU,
2488};
2489
2490
2491static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
2492 .master = &omap54xx_l4_abe_hwmod,
2493 .slave = &omap54xx_mcpdm_hwmod,
2494 .clk = "abe_iclk",
2495 .user = OCP_USER_MPU,
2496};
2497
2498
2499static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
2500 .master = &omap54xx_l4_per_hwmod,
2501 .slave = &omap54xx_mcspi1_hwmod,
2502 .clk = "l4_root_clk_div",
2503 .user = OCP_USER_MPU | OCP_USER_SDMA,
2504};
2505
2506
2507static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
2508 .master = &omap54xx_l4_per_hwmod,
2509 .slave = &omap54xx_mcspi2_hwmod,
2510 .clk = "l4_root_clk_div",
2511 .user = OCP_USER_MPU | OCP_USER_SDMA,
2512};
2513
2514
2515static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
2516 .master = &omap54xx_l4_per_hwmod,
2517 .slave = &omap54xx_mcspi3_hwmod,
2518 .clk = "l4_root_clk_div",
2519 .user = OCP_USER_MPU | OCP_USER_SDMA,
2520};
2521
2522
2523static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
2524 .master = &omap54xx_l4_per_hwmod,
2525 .slave = &omap54xx_mcspi4_hwmod,
2526 .clk = "l4_root_clk_div",
2527 .user = OCP_USER_MPU | OCP_USER_SDMA,
2528};
2529
2530
2531static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
2532 .master = &omap54xx_l4_per_hwmod,
2533 .slave = &omap54xx_mmc1_hwmod,
2534 .clk = "l3_iclk_div",
2535 .user = OCP_USER_MPU | OCP_USER_SDMA,
2536};
2537
2538
2539static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
2540 .master = &omap54xx_l4_per_hwmod,
2541 .slave = &omap54xx_mmc2_hwmod,
2542 .clk = "l3_iclk_div",
2543 .user = OCP_USER_MPU | OCP_USER_SDMA,
2544};
2545
2546
2547static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
2548 .master = &omap54xx_l4_per_hwmod,
2549 .slave = &omap54xx_mmc3_hwmod,
2550 .clk = "l4_root_clk_div",
2551 .user = OCP_USER_MPU | OCP_USER_SDMA,
2552};
2553
2554
2555static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
2556 .master = &omap54xx_l4_per_hwmod,
2557 .slave = &omap54xx_mmc4_hwmod,
2558 .clk = "l4_root_clk_div",
2559 .user = OCP_USER_MPU | OCP_USER_SDMA,
2560};
2561
2562
2563static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
2564 .master = &omap54xx_l4_per_hwmod,
2565 .slave = &omap54xx_mmc5_hwmod,
2566 .clk = "l4_root_clk_div",
2567 .user = OCP_USER_MPU | OCP_USER_SDMA,
2568};
2569
2570
2571static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
2572 .master = &omap54xx_l4_cfg_hwmod,
2573 .slave = &omap54xx_mpu_hwmod,
2574 .clk = "l4_root_clk_div",
2575 .user = OCP_USER_MPU | OCP_USER_SDMA,
2576};
2577
2578
2579static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
2580 .master = &omap54xx_l4_cfg_hwmod,
2581 .slave = &omap54xx_spinlock_hwmod,
2582 .clk = "l4_root_clk_div",
2583 .user = OCP_USER_MPU | OCP_USER_SDMA,
2584};
2585
2586
2587static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
2588 .master = &omap54xx_l4_cfg_hwmod,
2589 .slave = &omap54xx_ocp2scp1_hwmod,
2590 .clk = "l4_root_clk_div",
2591 .user = OCP_USER_MPU | OCP_USER_SDMA,
2592};
2593
2594
2595static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
2596 .master = &omap54xx_l4_wkup_hwmod,
2597 .slave = &omap54xx_timer1_hwmod,
2598 .clk = "wkupaon_iclk_mux",
2599 .user = OCP_USER_MPU | OCP_USER_SDMA,
2600};
2601
2602
2603static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
2604 .master = &omap54xx_l4_per_hwmod,
2605 .slave = &omap54xx_timer2_hwmod,
2606 .clk = "l4_root_clk_div",
2607 .user = OCP_USER_MPU | OCP_USER_SDMA,
2608};
2609
2610
2611static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
2612 .master = &omap54xx_l4_per_hwmod,
2613 .slave = &omap54xx_timer3_hwmod,
2614 .clk = "l4_root_clk_div",
2615 .user = OCP_USER_MPU | OCP_USER_SDMA,
2616};
2617
2618
2619static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
2620 .master = &omap54xx_l4_per_hwmod,
2621 .slave = &omap54xx_timer4_hwmod,
2622 .clk = "l4_root_clk_div",
2623 .user = OCP_USER_MPU | OCP_USER_SDMA,
2624};
2625
2626
2627static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
2628 .master = &omap54xx_l4_abe_hwmod,
2629 .slave = &omap54xx_timer5_hwmod,
2630 .clk = "abe_iclk",
2631 .user = OCP_USER_MPU,
2632};
2633
2634
2635static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2636 .master = &omap54xx_l4_abe_hwmod,
2637 .slave = &omap54xx_timer6_hwmod,
2638 .clk = "abe_iclk",
2639 .user = OCP_USER_MPU,
2640};
2641
2642
2643static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2644 .master = &omap54xx_l4_abe_hwmod,
2645 .slave = &omap54xx_timer7_hwmod,
2646 .clk = "abe_iclk",
2647 .user = OCP_USER_MPU,
2648};
2649
2650
2651static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2652 .master = &omap54xx_l4_abe_hwmod,
2653 .slave = &omap54xx_timer8_hwmod,
2654 .clk = "abe_iclk",
2655 .user = OCP_USER_MPU,
2656};
2657
2658
2659static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2660 .master = &omap54xx_l4_per_hwmod,
2661 .slave = &omap54xx_timer9_hwmod,
2662 .clk = "l4_root_clk_div",
2663 .user = OCP_USER_MPU | OCP_USER_SDMA,
2664};
2665
2666
2667static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2668 .master = &omap54xx_l4_per_hwmod,
2669 .slave = &omap54xx_timer10_hwmod,
2670 .clk = "l4_root_clk_div",
2671 .user = OCP_USER_MPU | OCP_USER_SDMA,
2672};
2673
2674
2675static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2676 .master = &omap54xx_l4_per_hwmod,
2677 .slave = &omap54xx_timer11_hwmod,
2678 .clk = "l4_root_clk_div",
2679 .user = OCP_USER_MPU | OCP_USER_SDMA,
2680};
2681
2682
2683static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2684 .master = &omap54xx_l4_per_hwmod,
2685 .slave = &omap54xx_uart1_hwmod,
2686 .clk = "l4_root_clk_div",
2687 .user = OCP_USER_MPU | OCP_USER_SDMA,
2688};
2689
2690
2691static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2692 .master = &omap54xx_l4_per_hwmod,
2693 .slave = &omap54xx_uart2_hwmod,
2694 .clk = "l4_root_clk_div",
2695 .user = OCP_USER_MPU | OCP_USER_SDMA,
2696};
2697
2698
2699static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2700 .master = &omap54xx_l4_per_hwmod,
2701 .slave = &omap54xx_uart3_hwmod,
2702 .clk = "l4_root_clk_div",
2703 .user = OCP_USER_MPU | OCP_USER_SDMA,
2704};
2705
2706
2707static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2708 .master = &omap54xx_l4_per_hwmod,
2709 .slave = &omap54xx_uart4_hwmod,
2710 .clk = "l4_root_clk_div",
2711 .user = OCP_USER_MPU | OCP_USER_SDMA,
2712};
2713
2714
2715static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2716 .master = &omap54xx_l4_per_hwmod,
2717 .slave = &omap54xx_uart5_hwmod,
2718 .clk = "l4_root_clk_div",
2719 .user = OCP_USER_MPU | OCP_USER_SDMA,
2720};
2721
2722
2723static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2724 .master = &omap54xx_l4_per_hwmod,
2725 .slave = &omap54xx_uart6_hwmod,
2726 .clk = "l4_root_clk_div",
2727 .user = OCP_USER_MPU | OCP_USER_SDMA,
2728};
2729
2730
2731static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
2732 .master = &omap54xx_l4_cfg_hwmod,
2733 .slave = &omap54xx_usb_host_hs_hwmod,
2734 .clk = "l3_iclk_div",
2735 .user = OCP_USER_MPU | OCP_USER_SDMA,
2736};
2737
2738
2739static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
2740 .master = &omap54xx_l4_cfg_hwmod,
2741 .slave = &omap54xx_usb_tll_hs_hwmod,
2742 .clk = "l4_root_clk_div",
2743 .user = OCP_USER_MPU | OCP_USER_SDMA,
2744};
2745
2746
2747static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2748 .master = &omap54xx_l4_cfg_hwmod,
2749 .slave = &omap54xx_usb_otg_ss_hwmod,
2750 .clk = "dpll_core_h13x2_ck",
2751 .user = OCP_USER_MPU | OCP_USER_SDMA,
2752};
2753
2754
2755static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2756 .master = &omap54xx_l4_wkup_hwmod,
2757 .slave = &omap54xx_wd_timer2_hwmod,
2758 .clk = "wkupaon_iclk_mux",
2759 .user = OCP_USER_MPU | OCP_USER_SDMA,
2760};
2761
2762static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2763 &omap54xx_l3_main_1__dmm,
2764 &omap54xx_l3_main_3__l3_instr,
2765 &omap54xx_l3_main_2__l3_main_1,
2766 &omap54xx_l4_cfg__l3_main_1,
2767 &omap54xx_mpu__l3_main_1,
2768 &omap54xx_l3_main_1__l3_main_2,
2769 &omap54xx_l4_cfg__l3_main_2,
2770 &omap54xx_l3_main_1__l3_main_3,
2771 &omap54xx_l3_main_2__l3_main_3,
2772 &omap54xx_l4_cfg__l3_main_3,
2773 &omap54xx_l3_main_1__l4_abe,
2774 &omap54xx_mpu__l4_abe,
2775 &omap54xx_l3_main_1__l4_cfg,
2776 &omap54xx_l3_main_2__l4_per,
2777 &omap54xx_l3_main_1__l4_wkup,
2778 &omap54xx_mpu__mpu_private,
2779 &omap54xx_l4_wkup__counter_32k,
2780 &omap54xx_l4_cfg__dma_system,
2781 &omap54xx_l4_abe__dmic,
2782 &omap54xx_l4_cfg__mmu_dsp,
2783 &omap54xx_l3_main_2__dss,
2784 &omap54xx_l3_main_2__dss_dispc,
2785 &omap54xx_l3_main_2__dss_dsi1_a,
2786 &omap54xx_l3_main_2__dss_dsi1_c,
2787 &omap54xx_l3_main_2__dss_hdmi,
2788 &omap54xx_l3_main_2__dss_rfbi,
2789 &omap54xx_mpu__emif1,
2790 &omap54xx_mpu__emif2,
2791 &omap54xx_l4_wkup__gpio1,
2792 &omap54xx_l4_per__gpio2,
2793 &omap54xx_l4_per__gpio3,
2794 &omap54xx_l4_per__gpio4,
2795 &omap54xx_l4_per__gpio5,
2796 &omap54xx_l4_per__gpio6,
2797 &omap54xx_l4_per__gpio7,
2798 &omap54xx_l4_per__gpio8,
2799 &omap54xx_l4_per__i2c1,
2800 &omap54xx_l4_per__i2c2,
2801 &omap54xx_l4_per__i2c3,
2802 &omap54xx_l4_per__i2c4,
2803 &omap54xx_l4_per__i2c5,
2804 &omap54xx_l3_main_2__mmu_ipu,
2805 &omap54xx_l4_wkup__kbd,
2806 &omap54xx_l4_cfg__mailbox,
2807 &omap54xx_l4_abe__mcbsp1,
2808 &omap54xx_l4_abe__mcbsp2,
2809 &omap54xx_l4_abe__mcbsp3,
2810 &omap54xx_l4_abe__mcpdm,
2811 &omap54xx_l4_per__mcspi1,
2812 &omap54xx_l4_per__mcspi2,
2813 &omap54xx_l4_per__mcspi3,
2814 &omap54xx_l4_per__mcspi4,
2815 &omap54xx_l4_per__mmc1,
2816 &omap54xx_l4_per__mmc2,
2817 &omap54xx_l4_per__mmc3,
2818 &omap54xx_l4_per__mmc4,
2819 &omap54xx_l4_per__mmc5,
2820 &omap54xx_l4_cfg__mpu,
2821 &omap54xx_l4_cfg__spinlock,
2822 &omap54xx_l4_cfg__ocp2scp1,
2823 &omap54xx_l4_wkup__timer1,
2824 &omap54xx_l4_per__timer2,
2825 &omap54xx_l4_per__timer3,
2826 &omap54xx_l4_per__timer4,
2827 &omap54xx_l4_abe__timer5,
2828 &omap54xx_l4_abe__timer6,
2829 &omap54xx_l4_abe__timer7,
2830 &omap54xx_l4_abe__timer8,
2831 &omap54xx_l4_per__timer9,
2832 &omap54xx_l4_per__timer10,
2833 &omap54xx_l4_per__timer11,
2834 &omap54xx_l4_per__uart1,
2835 &omap54xx_l4_per__uart2,
2836 &omap54xx_l4_per__uart3,
2837 &omap54xx_l4_per__uart4,
2838 &omap54xx_l4_per__uart5,
2839 &omap54xx_l4_per__uart6,
2840 &omap54xx_l4_cfg__usb_host_hs,
2841 &omap54xx_l4_cfg__usb_tll_hs,
2842 &omap54xx_l4_cfg__usb_otg_ss,
2843 &omap54xx_l4_wkup__wd_timer2,
2844 &omap54xx_l4_cfg__ocp2scp3,
2845 &omap54xx_l4_cfg__sata,
2846 NULL,
2847};
2848
2849int __init omap54xx_hwmod_init(void)
2850{
2851 omap_hwmod_init();
2852 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2853}
2854